fpga: rfnoc: Add Signal Generator RFNoC block

1 files changed, 24 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/Makefile.srcs b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/Makefile.srcs
new file mode 100644
index 000000000..336cc8cfa
--- /dev/null
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/Makefile.srcs
@@ -0,0 +1,24 @@
+#
+# Copyright 2020 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# RFNoC Block Sources
+##################################################
+# Here, list all the files that are necessary to synthesize this block. Don't
+# include testbenches!
+# Make sure that the source files are nicely detectable by a regex. Best to put
+# one on each line.
+# The first argument to addprefix is the current path to this Makefile, so the
+# path list is always absolute, regardless of from where we're including or
+# calling this file. RFNOC_OOT_SRCS needs to be a simply expanded variable
+# (not a recursively expanded variable), and we take care of that in the build
+# infrastructure.
+RFNOC_OOT_SRCS += $(addprefix $(dir $(abspath $(lastword $(MAKEFILE_LIST)))), \
+noc_shell_siggen.v \
+rfnoc_siggen_core.v \
+rfnoc_block_siggen_regs.vh \
+rfnoc_block_siggen.v \
+)