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| author | Wade Fife <wade.fife@ettus.com> | 2020-05-26 10:47:09 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-05-28 15:12:20 -0500 |
| commit | 983fad664436301c31c3bc8c81b538a41537598b (patch) | |
| tree | 76d5a79101ce351a1e1883417c7d9dba61ad3937 /fpga/usrp3/lib/rfnoc/axi_rate_change.v | |
| parent | 6faec1d4a14a1af52681aabf19c9040dcee772ff (diff) | |
| download | uhd-983fad664436301c31c3bc8c81b538a41537598b.tar.gz uhd-983fad664436301c31c3bc8c81b538a41537598b.tar.bz2 uhd-983fad664436301c31c3bc8c81b538a41537598b.zip | |
fpga: rfnoc: Add defaults for rate changing
Add DEFAULT_M and DEFAULT_N parameters for rate changing cores.
This allows the host to not need to configure fixed rate change
cores.
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/axi_rate_change.v')
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/axi_rate_change.v | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/fpga/usrp3/lib/rfnoc/axi_rate_change.v b/fpga/usrp3/lib/rfnoc/axi_rate_change.v index 56b859219..40cff0fff 100644 --- a/fpga/usrp3/lib/rfnoc/axi_rate_change.v +++ b/fpga/usrp3/lib/rfnoc/axi_rate_change.v @@ -46,7 +46,9 @@ module axi_rate_change #( parameter SR_N_ADDR = 0, parameter SR_M_ADDR = 1, parameter SR_CONFIG_ADDR = 2, - parameter SR_TIME_INCR_ADDR = 3 + parameter SR_TIME_INCR_ADDR = 3, + parameter DEFAULT_N = 1, + parameter DEFAULT_M = 1 )( input clk, input reset, input clear, output clear_user, // Strobed after end of burst. Throttles input. Useful for resetting user code between bursts. @@ -65,8 +67,8 @@ module axi_rate_change #( output reg error_drop_pkt_lockup // Drop partial packet module is not accepting data even though user code is ready. ); - reg [$clog2(MAX_N+1)-1:0] n = 1; - reg [$clog2(MAX_M+1)-1:0] m = 1; + reg [$clog2(MAX_N+1)-1:0] n = DEFAULT_N; + reg [$clog2(MAX_M+1)-1:0] m = DEFAULT_M; wire [WIDTH-1:0] i_reg_tdata; wire i_reg_tvalid, i_reg_tready, i_reg_tlast; @@ -85,13 +87,13 @@ module axi_rate_change #( ********************************************************/ wire [$clog2(MAX_N+1)-1:0] sr_n; wire n_changed; - setting_reg #(.my_addr(SR_N_ADDR), .width($clog2(MAX_N+1)), .at_reset(1)) set_n ( + setting_reg #(.my_addr(SR_N_ADDR), .width($clog2(MAX_N+1)), .at_reset(DEFAULT_N)) set_n ( .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(sr_n), .changed(n_changed)); wire [$clog2(MAX_M+1)-1:0] sr_m; wire m_changed; - setting_reg #(.my_addr(SR_M_ADDR), .width($clog2(MAX_M+1)), .at_reset(1)) set_m ( + setting_reg #(.my_addr(SR_M_ADDR), .width($clog2(MAX_M+1)), .at_reset(DEFAULT_M)) set_m ( .clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(sr_m), .changed(m_changed)); @@ -169,8 +171,8 @@ module axi_rate_change #( always @(posedge clk) begin if (reset | clear) begin - n <= 1; - m <= 1; + n <= DEFAULT_N; + m <= DEFAULT_M; rate_changed <= 1'b0; first_header <= 1'b1; partial_first_word <= 1'b1; @@ -297,7 +299,8 @@ module axi_rate_change #( .WIDTH(WIDTH+1), .HOLD_LAST_WORD(1), .MAX_PKT_SIZE(MAX_N), - .SR_PKT_SIZE_ADDR(SR_N_ADDR)) + .SR_PKT_SIZE_ADDR(SR_N_ADDR), + .DEFAULT_PKT_SIZE(DEFAULT_N)) axi_drop_partial_packet ( .clk(clk), .reset(reset), .clear(clear | send_done), .flush(word_cnt_div_n_tvalid & word_cnt_div_n_tready), // Flush on EOB |