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authorWade Fife <wade.fife@ettus.com>2020-06-19 15:40:12 -0500
committerAaron Rossetto <aaron.rossetto@ni.com>2020-07-30 12:51:41 -0500
commit1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4 (patch)
tree12ba30a59c8057e355971797d5cc7bf6910f520b /fpga/usrp3/lib/rfnoc/Makefile.srcs
parentb0b3849a18e1f2d3cb255a507b01ac5e7a9416a0 (diff)
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fpga: rfnoc: Add Signal Generator RFNoC block
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/Makefile.srcs')
-rw-r--r--fpga/usrp3/lib/rfnoc/Makefile.srcs1
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/rfnoc/Makefile.srcs b/fpga/usrp3/lib/rfnoc/Makefile.srcs
index cb97542ce..d6e079f67 100644
--- a/fpga/usrp3/lib/rfnoc/Makefile.srcs
+++ b/fpga/usrp3/lib/rfnoc/Makefile.srcs
@@ -102,6 +102,7 @@ ddc.v \
duc.v \
cic_decimate.v \
cic_interpolate.v \
+sine_tone.v \
axi_fir_filter.v \
fir_filter_slice.v \
axi_fir_filter_dec.v \