b2xx: Updating FPGA source with recent bugfixes.

1 files changed, 51 insertions, 4 deletions

diff --git a/fpga/usrp3/lib/packet_proc/eth_interface.v b/fpga/usrp3/lib/packet_proc/eth_interface.v
index 083badfea..e6fa3252d 100644
--- a/fpga/usrp3/lib/packet_proc/eth_interface.v
+++ b/fpga/usrp3/lib/packet_proc/eth_interface.v
@@ -21,7 +21,8 @@ module eth_interface
     // ZPU
     output [63:0] e2z_tdata, output [3:0] e2z_tuser, output e2z_tlast, output e2z_tvalid, input e2z_tready,
     input [63:0] z2e_tdata, input [3:0] z2e_tuser, input z2e_tlast, input z2e_tvalid, output z2e_tready,
-    
+    // Debug
+    output [31:0] debug_flags,
     output [31:0] debug
     );
 
@@ -36,7 +37,12 @@ module eth_interface
    wire [63:0] 	  epg_tdata_int;
    wire [3:0] 	  epg_tuser_int;
    wire 	  epg_tlast_int, epg_tvalid_int, epg_tready_int;
-
+   
+   //
+   // Packet gate ensures on entire ingressing packet is buffered before feeding it downstream so that it bursts
+   // efficiently internally without holding resources allocted for longer than optimal. This also means that an upstream
+   // error discovered in the packet can allow the packet to be destroyed here, before it gets deeper into the USRP.
+   //
    axi_packet_gate #(.WIDTH(68), .SIZE(10)) packet_gater //holds 8K pkts
      (.clk(clk), .reset(reset), .clear(clear),
 
@@ -47,10 +53,14 @@ module eth_interface
       .o_tdata({epg_tuser_int, epg_tdata_int}), .o_tlast(epg_tlast_int),
       .o_tvalid(epg_tvalid_int), .o_tready(epg_tready_int));
 
+   //
+   // Based on programmed rules, parse network headers and decide which internal destination(s) this packet will be forwarded to.
+   //
    wire [63:0] 	  e2z_tdata_int;
    wire [3:0] 	  e2z_tuser_int;
    wire 	  e2z_tlast_int, e2z_tvalid_int, e2z_tready_int;
-
+   wire [2:0]	  dispatch_debug_flags;
+   
    eth_dispatch #(.BASE(BASE+8)) eth_dispatch
      (.clk(clk), .reset(reset), .clear(clear),
       .set_stb(set_stb), .set_addr(set_addr) , .set_data(set_data),
@@ -58,8 +68,11 @@ module eth_interface
       .vita_tdata(e2v_tdata), .vita_tlast(e2v_tlast), .vita_tvalid(e2v_tvalid), .vita_tready(e2v_tready),
       .zpu_tdata(e2z_tdata_int), .zpu_tuser(e2z_tuser_int), .zpu_tlast(e2z_tlast_int), .zpu_tvalid(e2z_tvalid_int), .zpu_tready(e2z_tready_int),
       .xo_tdata(xo_tdata), .xo_tuser(xo_tuser), .xo_tlast(xo_tlast), .xo_tvalid(xo_tvalid), .xo_tready(xo_tready), // to other eth port
-      .debug(debug));
+      .debug_flags(dispatch_debug_flags),.debug(debug));
 
+   //
+   // ZPU can be slow to respond (relative to packet wirespeed) so extra buffer for packets destined there so it doesn't back up.
+   //
    axi_fifo #(.WIDTH(69),.SIZE(ZPU_FIFOSIZE)) zpu_fifo
      (.clk(clk), .reset(reset), .clear(clear),
       .i_tdata({e2z_tlast_int,e2z_tuser_int,e2z_tdata_int}), .i_tvalid(e2z_tvalid_int), .i_tready(e2z_tready_int),
@@ -110,4 +123,38 @@ module eth_interface
       .i_tdata({eth_tx_tlast_int,eth_tx_tuser_int,eth_tx_tdata_int}), .i_tvalid(eth_tx_tvalid_int), .i_tready(eth_tx_tready_int),
       .o_tdata({eth_tx_tlast,eth_tx_tuser,eth_tx_tdata}), .o_tvalid(eth_tx_tvalid), .o_tready(eth_tx_tready));
 
+
+   //
+   // Provide instrumentation so that abnormal FIFO conditions can be identifed.
+   //
+/* -----\/----- EXCLUDED -----\/-----
+
+   setting_reg #(.my_addr(BASE+15), .awidth(16), .width(1)) sr_reset_fifo_debug
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(clear_debug_flags));
+
+   always @(posedge clk)
+     if (reset)
+       debug_flags <= 0;
+     else if (clear_debug_flags)
+       debug_flags <= 0;
+     else
+       debug_flags <= debug_flags | {eth_rx_tuser[3],
+				     ~eth_tx_tready_int,
+				     ~xi_tready,
+				     ~v2e_tready,
+				     ~e2z_tready_int,
+				     ~eth_rx_tready,
+				     ~dispatch_debug_flags[2:0]};
+ -----/\----- EXCLUDED -----/\----- */
+   
+   assign debug_flags = {eth_rx_tuser[3],
+				     ~eth_tx_tready_int,
+				     ~xi_tready,
+				     ~v2e_tready,
+				     ~e2z_tready_int,
+				     ~eth_rx_tready,
+				     ~dispatch_debug_flags[2:0]};	  
+     
+
 endmodule // eth_interface