Pushing the bulk of UHD-3.7.0 code.

31 files changed, 466 insertions, 351 deletions

diff --git a/fpga/usrp3/lib/dsp/Makefile.srcs b/fpga/usrp3/lib/dsp/Makefile.srcs
index 3896ac5b5..44bd6f930 100644
--- a/fpga/usrp3/lib/dsp/Makefile.srcs
+++ b/fpga/usrp3/lib/dsp/Makefile.srcs
@@ -6,6 +6,7 @@
 # DSP Sources
 ##################################################
 DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/dsp/, \
+ddc_chain_x300.v \
 ddc_chain.v \
 duc_chain.v \
 sign_extend.v \
@@ -34,5 +35,6 @@ round.v \
 srl.v \
 acc.v \
 rx_frontend.v \
+tx_frontend.v \
 rx_dcoffset.v \
 ))
diff --git a/fpga/usrp3/lib/dsp/acc.v b/fpga/usrp3/lib/dsp/acc.v
index d5fc4b910..86b68512f 100644
--- a/fpga/usrp3/lib/dsp/acc.v
+++ b/fpga/usrp3/lib/dsp/acc.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 module acc
diff --git a/fpga/usrp3/lib/dsp/add2.v b/fpga/usrp3/lib/dsp/add2.v
index dcca84fd3..124f9d6ca 100644
--- a/fpga/usrp3/lib/dsp/add2.v
+++ b/fpga/usrp3/lib/dsp/add2.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 module add2
diff --git a/fpga/usrp3/lib/dsp/add2_and_round.v b/fpga/usrp3/lib/dsp/add2_and_round.v
index 7c347527c..9d0914414 100644
--- a/fpga/usrp3/lib/dsp/add2_and_round.v
+++ b/fpga/usrp3/lib/dsp/add2_and_round.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 module add2_and_round
diff --git a/fpga/usrp3/lib/dsp/add2_and_round_reg.v b/fpga/usrp3/lib/dsp/add2_and_round_reg.v
index 5c783bda3..cb20a3c1b 100644
--- a/fpga/usrp3/lib/dsp/add2_and_round_reg.v
+++ b/fpga/usrp3/lib/dsp/add2_and_round_reg.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 module add2_and_round_reg
diff --git a/fpga/usrp3/lib/dsp/add2_reg.v b/fpga/usrp3/lib/dsp/add2_reg.v
index 58d822a61..3ac93ae2e 100644
--- a/fpga/usrp3/lib/dsp/add2_reg.v
+++ b/fpga/usrp3/lib/dsp/add2_reg.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 module add2_reg
diff --git a/fpga/usrp3/lib/dsp/cic_dec_shifter.v b/fpga/usrp3/lib/dsp/cic_dec_shifter.v
index aa5ac895b..efc54c106 100644
--- a/fpga/usrp3/lib/dsp/cic_dec_shifter.v
+++ b/fpga/usrp3/lib/dsp/cic_dec_shifter.v
@@ -4,19 +4,7 @@
 //
 //  Copyright (C) 2003 Matt Ettus
 //
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+
 //
 
 
diff --git a/fpga/usrp3/lib/dsp/cic_decim.v b/fpga/usrp3/lib/dsp/cic_decim.v
index e6b6e9590..feb785de8 100644
--- a/fpga/usrp3/lib/dsp/cic_decim.v
+++ b/fpga/usrp3/lib/dsp/cic_decim.v
@@ -4,19 +4,7 @@
 //
 //  Copyright (C) 2003 Matt Ettus
 //
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+
 //
 
 
diff --git a/fpga/usrp3/lib/dsp/cic_int_shifter.v b/fpga/usrp3/lib/dsp/cic_int_shifter.v
index 18587fa8b..ff5a30d6a 100644
--- a/fpga/usrp3/lib/dsp/cic_int_shifter.v
+++ b/fpga/usrp3/lib/dsp/cic_int_shifter.v
@@ -4,19 +4,7 @@
 //
 //  Copyright (C) 2003 Matt Ettus
 //
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+
 //
 
 
diff --git a/fpga/usrp3/lib/dsp/cic_interp.v b/fpga/usrp3/lib/dsp/cic_interp.v
index 9b6928aa1..608c2d448 100644
--- a/fpga/usrp3/lib/dsp/cic_interp.v
+++ b/fpga/usrp3/lib/dsp/cic_interp.v
@@ -4,19 +4,7 @@
 //
 //  Copyright (C) 2003 Matt Ettus
 //
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+
 //
 
 
diff --git a/fpga/usrp3/lib/dsp/cic_strober.v b/fpga/usrp3/lib/dsp/cic_strober.v
index 40d76bdd9..269b85f75 100644
--- a/fpga/usrp3/lib/dsp/cic_strober.v
+++ b/fpga/usrp3/lib/dsp/cic_strober.v
@@ -3,19 +3,7 @@
 //
 //  Copyright (C) 2008 Matt Ettus
 //
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+
 //
 
 module cic_strober
diff --git a/fpga/usrp3/lib/dsp/clip.v b/fpga/usrp3/lib/dsp/clip.v
index 3e6b3a2e2..294c5e8ba 100644
--- a/fpga/usrp3/lib/dsp/clip.v
+++ b/fpga/usrp3/lib/dsp/clip.v
@@ -4,19 +4,7 @@
 //
 //  Copyright (C) 2008 Matt Ettus
 //
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+
 //
 
 // Clipping "macro", keeps the bottom bits
diff --git a/fpga/usrp3/lib/dsp/clip_reg.v b/fpga/usrp3/lib/dsp/clip_reg.v
index 9098fd5b8..ab9a5b79d 100644
--- a/fpga/usrp3/lib/dsp/clip_reg.v
+++ b/fpga/usrp3/lib/dsp/clip_reg.v
@@ -4,19 +4,7 @@
 //
 //  Copyright (C) 2008 Matt Ettus
 //
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+
 //
 
 // Clipping "macro", keeps the bottom bits
diff --git a/fpga/usrp3/lib/dsp/cordic_stage.v b/fpga/usrp3/lib/dsp/cordic_stage.v
index 641ff9108..7019ead52 100644
--- a/fpga/usrp3/lib/dsp/cordic_stage.v
+++ b/fpga/usrp3/lib/dsp/cordic_stage.v
@@ -4,19 +4,7 @@
 //
 //  Copyright (C) 2003 Matt Ettus
 //
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+
 //
 
 module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
diff --git a/fpga/usrp3/lib/dsp/cordic_z24.v b/fpga/usrp3/lib/dsp/cordic_z24.v
index 51b074a33..d9e983ccd 100644
--- a/fpga/usrp3/lib/dsp/cordic_z24.v
+++ b/fpga/usrp3/lib/dsp/cordic_z24.v
@@ -4,19 +4,7 @@
 //
 //  Copyright (C) 2003, 2007 Matt Ettus
 //
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+
 //
 
 module cordic_z24(clock, reset, enable, xi, yi, zi, xo, yo, zo );
diff --git a/fpga/usrp3/lib/dsp/ddc_chain.v b/fpga/usrp3/lib/dsp/ddc_chain.v
index b802416c1..365175bf1 100644
--- a/fpga/usrp3/lib/dsp/ddc_chain.v
+++ b/fpga/usrp3/lib/dsp/ddc_chain.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011-2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 //! The USRP digital down-conversion chain
 
diff --git a/fpga/usrp3/lib/dsp/ddc_chain_x300.v b/fpga/usrp3/lib/dsp/ddc_chain_x300.v
new file mode 100644
index 000000000..aed001c66
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/ddc_chain_x300.v
@@ -0,0 +1,262 @@
+//
+// Copyright 2011-2013 Ettus Research LLC
+//
+
+//! X300/X310 digital down-conversion chain
+
+module ddc_chain_x300
+  #(
+    parameter BASE = 0,
+    parameter DSPNO = 0,
+    parameter WIDTH = 24
+  )
+  (input clk, input rst, input clr,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   // From RX frontend
+   input [WIDTH-1:0] rx_fe_i,
+   input [WIDTH-1:0] rx_fe_q,
+
+   // To RX control
+   output [31:0] sample,
+   input run,
+   output strobe,
+   output [31:0] debug
+   );
+
+   localparam  cwidth = 25;
+   localparam  zwidth = 24;
+
+   wire [31:0] phase_inc;
+   reg [31:0]  phase;
+
+   wire [17:0] scale_factor;
+   wire [cwidth-1:0] i_cordic, q_cordic;
+   wire [WIDTH-1:0] i_cordic_clip, q_cordic_clip;
+   wire [WIDTH-1:0] i_cic, q_cic;
+   wire [46:0] 	    i_hb1, q_hb1;
+   wire [46:0] 	    i_hb2, q_hb2;
+   wire [47:0] 	    i_hb3, q_hb3;
+   
+   wire        strobe_cic, strobe_hb1, strobe_hb2, strobe_hb3;
+
+   wire [7:0]  cic_decim_rate;
+
+   reg [WIDTH-1:0]  rx_fe_i_mux, rx_fe_q_mux;
+   wire        realmode;
+   wire        swap_iq;
+   wire [1:0]  hb_rate;
+   wire [2:0]  enable_hb = { hb_rate == 2'b11, hb_rate[1] == 1'b1, hb_rate != 2'b00 };
+   
+   wire        reload_go, reload_we1, reload_we2, reload_we3, reload_ld1, reload_ld2, reload_ld3;
+   wire [17:0] coef_din;
+   
+   setting_reg #(.my_addr(BASE+0)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_inc),.changed());
+
+   setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(scale_factor),.changed());
+
+   setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({hb_rate, cic_decim_rate}),.changed());
+
+   setting_reg #(.my_addr(BASE+3), .width(2)) sr_3
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({realmode,swap_iq}),.changed());
+
+   setting_reg #(.my_addr(BASE+4), .width(24)) sr_4
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({reload_ld3,reload_we3,reload_ld2,reload_we2,reload_ld1,reload_we1,coef_din}),.changed(reload_go));
+   
+   // MUX so we can do realmode signals on either input
+   
+   always @(posedge clk)
+     if(swap_iq)
+       begin
+	  rx_fe_i_mux <= rx_fe_q;
+	  rx_fe_q_mux <= realmode ? 0 : rx_fe_i;
+       end
+     else
+       begin
+	  rx_fe_i_mux <= rx_fe_i;
+	  rx_fe_q_mux <= realmode ? 0 : rx_fe_q;
+       end
+
+   // NCO
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(~run)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+
+   //sign extension of cordic input
+   wire [cwidth-1:0] to_cordic_i, to_cordic_q;
+   sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_i (.in(rx_fe_i_mux), .out(to_cordic_i));
+   sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_q (.in(rx_fe_q_mux), .out(to_cordic_q));
+
+   // CORDIC  24-bit I/O
+   cordic_z24 #(.bitwidth(cwidth))
+     cordic(.clock(clk), .reset(rst), .enable(run),
+	    .xi(to_cordic_i),. yi(to_cordic_q), .zi(phase[31:32-zwidth]),
+	    .xo(i_cordic),.yo(q_cordic),.zo() );
+
+   clip_reg #(.bits_in(cwidth), .bits_out(WIDTH)) clip_cordic_i
+     (.clk(clk), .in(i_cordic), .strobe_in(1'b1), .out(i_cordic_clip));
+   clip_reg #(.bits_in(cwidth), .bits_out(WIDTH)) clip_cordic_q
+     (.clk(clk), .in(q_cordic), .strobe_in(1'b1), .out(q_cordic_clip));
+
+   // CIC decimator  24 bit I/O
+   cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
+			   .strobe_fast(1'b1),.strobe_slow(strobe_cic) );
+
+   cic_decim #(.bw(WIDTH))
+     decim_i (.clock(clk),.reset(rst),.enable(run),
+	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
+	      .signal_in(i_cordic_clip),.signal_out(i_cic));
+   
+   cic_decim #(.bw(WIDTH))
+     decim_q (.clock(clk),.reset(rst),.enable(run),
+	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
+	      .signal_in(q_cordic_clip),.signal_out(q_cic));
+
+   // Halfbands
+   wire 	     nd1, nd2, nd3;
+   wire 	     rfd1, rfd2, rfd3;
+   wire 	     rdy1, rdy2, rdy3;
+   wire 	     data_valid1, data_valid2, data_valid3;
+
+   localparam HB1_SCALE = 18;
+   localparam HB2_SCALE = 18;
+   localparam HB3_SCALE = 18;
+   
+   assign strobe_hb1 = data_valid1;
+   assign strobe_hb2 = data_valid2;
+   assign strobe_hb3 = data_valid3;
+   assign nd1 = strobe_cic;
+   assign nd2 = strobe_hb1;
+   assign nd3 = strobe_hb2;
+   
+   hbdec1 hbdec1
+     (.clk(clk), // input clk
+      .sclr(rst), // input sclr
+      .ce(enable_hb[0]), // input ce
+      .coef_ld(reload_go & reload_ld1), // input coef_ld
+      .coef_we(reload_go & reload_we1), // input coef_we
+      .coef_din(coef_din), // input [17 : 0] coef_din
+      .rfd(rfd1), // output rfd
+      .nd(nd1), // input nd
+      .din_1(i_cic), // input [23 : 0] din_1
+      .din_2(q_cic), // input [23 : 0] din_2
+      .rdy(rdy1), // output rdy
+      .data_valid(data_valid1), // output data_valid
+      .dout_1(i_hb1), // output [46 : 0] dout_1
+      .dout_2(q_hb1)); // output [46 : 0] dout_2
+
+   hbdec2 hbdec2
+     (.clk(clk), // input clk
+      .sclr(rst), // input sclr
+      .ce(enable_hb[1]), // input ce
+      .coef_ld(reload_go & reload_ld2), // input coef_ld
+      .coef_we(reload_go & reload_we2), // input coef_we
+      .coef_din(coef_din), // input [17 : 0] coef_din
+      .rfd(rfd2), // output rfd
+      .nd(nd2), // input nd
+      .din_1(i_hb1[23+HB1_SCALE:HB1_SCALE]), // input [23 : 0] din_1
+      .din_2(q_hb1[23+HB1_SCALE:HB1_SCALE]), // input [23 : 0] din_2
+      .rdy(rdy2), // output rdy
+      .data_valid(data_valid2), // output data_valid
+      .dout_1(i_hb2), // output [46 : 0] dout_1
+      .dout_2(q_hb2)); // output [46 : 0] dout_2
+
+   hbdec3 hbdec3
+     (.clk(clk), // input clk
+      .sclr(rst), // input sclr
+      .ce(enable_hb[2]), // input ce
+      .coef_ld(reload_go & reload_ld3), // input coef_ld
+      .coef_we(reload_go & reload_we3), // input coef_we
+      .coef_din(coef_din), // input [17 : 0] coef_din
+      .rfd(rfd3), // output rfd
+      .nd(strobe_hb2), // input nd
+      .din_1(i_hb2[23+HB2_SCALE:HB2_SCALE]), // input [23 : 0] din_1
+      .din_2(q_hb2[23+HB2_SCALE:HB2_SCALE]), // input [23 : 0] din_2
+      .rdy(rdy3), // output rdy
+      .data_valid(data_valid3), // output data_valid
+      .dout_1(i_hb3), // output [47 : 0] dout_1
+      .dout_2(q_hb3)); // output [47 : 0] dout_2
+
+   reg [23:0] 	     i_unscaled, q_unscaled;
+   reg 		     strobe_unscaled;
+   
+   always @(posedge clk)
+     case(hb_rate)
+       2'd0 :
+	 begin
+	    strobe_unscaled <= strobe_cic;
+	    i_unscaled <= i_cic[23:0];
+	    q_unscaled <= q_cic[23:0];
+	 end
+       2'd1 :
+	 begin
+	    strobe_unscaled <= strobe_hb1;
+	    i_unscaled <= i_hb1[23+HB1_SCALE:HB1_SCALE];
+	    q_unscaled <= q_hb1[23+HB1_SCALE:HB1_SCALE];
+	 end
+       2'd2 :
+	 begin
+	    strobe_unscaled <= strobe_hb2;
+	    i_unscaled <= i_hb2[23+HB2_SCALE:HB2_SCALE];
+	    q_unscaled <= q_hb2[23+HB2_SCALE:HB2_SCALE];
+	 end
+       2'd3 :
+	 begin
+	    strobe_unscaled <= strobe_hb3;
+	    i_unscaled <= i_hb3[23+HB3_SCALE:HB3_SCALE];
+	    q_unscaled <= q_hb3[23+HB3_SCALE:HB3_SCALE];
+	 end
+     endcase // case (hb_rate)
+
+   wire [42:0] i_scaled, q_scaled;
+   wire [23:0] i_clip, q_clip;
+   reg 	       strobe_scaled;
+   wire        strobe_clip;
+   
+   MULT_MACRO #(.DEVICE("7SERIES"),  // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES" 
+		.LATENCY(1),         // Desired clock cycle latency, 0-4
+		.WIDTH_A(25),        // Multiplier A-input bus width, 1-25
+		.WIDTH_B(18))        // Multiplier B-input bus width, 1-18
+   SCALE_I (.P(i_scaled),     // Multiplier output bus, width determined by WIDTH_P parameter 
+	    .A({i_unscaled[23],i_unscaled}),     // Multiplier input A bus, width determined by WIDTH_A parameter 
+	    .B(scale_factor),                    // Multiplier input B bus, width determined by WIDTH_B parameter 
+	    .CE(strobe_unscaled),   // 1-bit active high input clock enable
+	    .CLK(clk),              // 1-bit positive edge clock input
+	    .RST(rst));             // 1-bit input active high reset
+	       
+   MULT_MACRO #(.DEVICE("7SERIES"),  // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES" 
+		.LATENCY(1),         // Desired clock cycle latency, 0-4
+		.WIDTH_A(25),        // Multiplier A-input bus width, 1-25
+		.WIDTH_B(18))        // Multiplier B-input bus width, 1-18
+   SCALE_Q (.P(q_scaled),     // Multiplier output bus, width determined by WIDTH_P parameter 
+	    .A({q_unscaled[23],q_unscaled}),     // Multiplier input A bus, width determined by WIDTH_A parameter 
+	    .B(scale_factor),                    // Multiplier input B bus, width determined by WIDTH_B parameter 
+	    .CE(strobe_unscaled),   // 1-bit active high input clock enable
+	    .CLK(clk),              // 1-bit positive edge clock input
+	    .RST(rst));             // 1-bit input active high reset
+
+   always @(posedge clk)  strobe_scaled <= strobe_unscaled;
+   
+   clip_reg #(.bits_in(29), .bits_out(24), .STROBED(1)) clip_i
+     (.clk(clk), .in(i_scaled[42:14]), .strobe_in(strobe_scaled), .out(i_clip), .strobe_out(strobe_clip));
+   clip_reg #(.bits_in(29), .bits_out(24), .STROBED(1)) clip_q
+     (.clk(clk), .in(q_scaled[42:14]), .strobe_in(strobe_scaled), .out(q_clip), .strobe_out());
+
+   round_sd #(.WIDTH_IN(24), .WIDTH_OUT(16)) round_i
+     (.clk(clk), .reset(rst), .in(i_clip), .strobe_in(strobe_clip), .out(sample[31:16]), .strobe_out(strobe));
+   round_sd #(.WIDTH_IN(24), .WIDTH_OUT(16)) round_q
+     (.clk(clk), .reset(rst), .in(q_clip), .strobe_in(strobe_clip), .out(sample[15:0]), .strobe_out());
+   
+endmodule // ddc_chain
diff --git a/fpga/usrp3/lib/dsp/ddc_chain_x300_tb.v b/fpga/usrp3/lib/dsp/ddc_chain_x300_tb.v
new file mode 100644
index 000000000..b6b5e368b
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/ddc_chain_x300_tb.v
@@ -0,0 +1,58 @@
+`timescale 1ns/1ps
+
+module ddc_chain_x300_tb();
+   
+`ifdef ISIM
+`else //iverilog implied.
+//   xlnx_glbl glbl (.GSR(),.GTS());
+`endif
+   
+   localparam SR_TX_DSP        = 8;
+
+   reg clk    = 0;
+   reg reset  = 1;
+   
+   always #10 clk = ~clk;
+   
+   initial $dumpfile("ddc_chain_x300_tb.vcd");
+   initial $dumpvars(0,ddc_chain_x300_tb);
+   reg run = 0;
+   wire strobe;
+   
+   initial
+     begin
+	#1000 reset = 0;
+	@(posedge clk);
+	set_addr <= 0; set_data <= 32'd8434349; set_stb <= 1; @(posedge clk); // CORDIC
+	set_addr <= 1; set_data <= 18'd19800; set_stb <= 1; @(posedge clk); // Scale factor
+	set_addr <= 2; set_data <= 10'h003; set_stb <= 1; @(posedge clk); // Decim control
+	set_addr <= 3; set_data <= 0; set_stb <= 1; @(posedge clk); // Swap iq
+	set_addr <= 4; set_data <= 0; set_stb <= 1; @(posedge clk); // filter taps
+	set_stb <= 0;
+		
+	repeat(10)
+	  @(posedge clk);
+	run <= 1'b1;
+	#30000;
+	$finish;
+     end
+   
+   reg [7:0]   set_addr;
+   reg [31:0]  set_data;
+   reg 	       set_stb = 1'b0;
+
+   wire [15:0] i_out, q_out;
+   wire [23:0] rx_fe_i, rx_fe_q;
+
+   assign rx_fe_i = 24'd8388607;
+   assign rx_fe_q = 24'd8388607;
+   //assign rx_fe_q = 0;
+   
+   ddc_chain_x300 #(.BASE(0), .DSPNO(0), .WIDTH(24)) ddc_chain
+     (.clk(clk), .rst(reset), .clr(1'b0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
+      .sample({i_out,q_out}), .run(run), .strobe(strobe),
+      .debug() );
+   
+endmodule // new_tx_tb
diff --git a/fpga/usrp3/lib/dsp/duc_chain.v b/fpga/usrp3/lib/dsp/duc_chain.v
index 6c2381c90..06c87bd34 100644
--- a/fpga/usrp3/lib/dsp/duc_chain.v
+++ b/fpga/usrp3/lib/dsp/duc_chain.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011-2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 //! The USRP digital up-conversion chain
 
diff --git a/fpga/usrp3/lib/dsp/hb_dec.v b/fpga/usrp3/lib/dsp/hb_dec.v
index 8d21c21c0..65c771ca7 100644
--- a/fpga/usrp3/lib/dsp/hb_dec.v
+++ b/fpga/usrp3/lib/dsp/hb_dec.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 // Final halfband decimator 
 // Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A]
diff --git a/fpga/usrp3/lib/dsp/hb_interp.v b/fpga/usrp3/lib/dsp/hb_interp.v
index d89046db7..c0914255c 100644
--- a/fpga/usrp3/lib/dsp/hb_interp.v
+++ b/fpga/usrp3/lib/dsp/hb_interp.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 // First halfband iterpolator 
 // Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A]
diff --git a/fpga/usrp3/lib/dsp/round.v b/fpga/usrp3/lib/dsp/round.v
index 26d5a4cf4..7ecc10ff7 100644
--- a/fpga/usrp3/lib/dsp/round.v
+++ b/fpga/usrp3/lib/dsp/round.v
@@ -4,19 +4,7 @@
 //
 //  Copyright (C) 2011 Matt Ettus
 //
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+
 //
 
 // Rounding "macro"
diff --git a/fpga/usrp3/lib/dsp/round_reg.v b/fpga/usrp3/lib/dsp/round_reg.v
index 6f2e974d7..c8c77f518 100644
--- a/fpga/usrp3/lib/dsp/round_reg.v
+++ b/fpga/usrp3/lib/dsp/round_reg.v
@@ -4,19 +4,7 @@
 //
 //  Copyright (C) 2008 Matt Ettus
 //
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+
 //
 
 // Rounding "macro"
diff --git a/fpga/usrp3/lib/dsp/rx_dcoffset.v b/fpga/usrp3/lib/dsp/rx_dcoffset.v
index 04d7795c0..f74b0f1a0 100644
--- a/fpga/usrp3/lib/dsp/rx_dcoffset.v
+++ b/fpga/usrp3/lib/dsp/rx_dcoffset.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 
diff --git a/fpga/usrp3/lib/dsp/rx_frontend.v b/fpga/usrp3/lib/dsp/rx_frontend.v
index ebe19240c..e34a2954b 100644
--- a/fpga/usrp3/lib/dsp/rx_frontend.v
+++ b/fpga/usrp3/lib/dsp/rx_frontend.v
@@ -14,8 +14,9 @@ module rx_frontend
     );
    
    reg [15:0] 	  adc_i, adc_q;
-   wire [17:0] 	  adc_i_ofs, adc_q_ofs;
-   wire [35:0] 	  corr_i, corr_q; wire [17:0] 	  mag_corr,phase_corr;
+   wire [23:0] 	  adc_i_ofs, adc_q_ofs;
+   wire [35:0] 	  corr_i, corr_q; 
+   wire [17:0] 	  mag_corr,phase_corr;
    wire 	  swap_iq;
    
    setting_reg #(.my_addr(BASE), .width(1)) sr_8
@@ -36,43 +37,38 @@ module rx_frontend
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_corr),.changed());
 
+   rx_dcoffset #(.WIDTH(24),.ADDR(BASE+3)) rx_dcoffset_i
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .in({adc_i,8'b00}),.out(adc_i_ofs));
+   
+   rx_dcoffset #(.WIDTH(24),.ADDR(BASE+4)) rx_dcoffset_q
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .in({adc_q,8'b00}),.out(adc_q_ofs));
+   
    generate
       if(IQCOMP_EN == 1)
 	begin
-	   rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i
-	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-	      .in({adc_i,2'b00}),.out(adc_i_ofs));
-	   
-	   rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q
-	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-	      .in({adc_q,2'b00}),.out(adc_q_ofs));
-	   
 	   MULT18X18S mult_mag_corr
-	     (.P(corr_i), .A(adc_i_ofs), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); 
+	     (.P(corr_i), .A(adc_i_ofs[23:6]), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); 
 	   
 	   MULT18X18S mult_phase_corr
-	     (.P(corr_q), .A(adc_i_ofs), .B(phase_corr), .C(clk), .CE(1), .R(rst) );
+	     (.P(corr_q), .A(adc_i_ofs[23:6]), .B(phase_corr), .C(clk), .CE(1), .R(rst) );
 	   
 	   add2_and_clip_reg #(.WIDTH(24)) add_clip_i
 	     (.clk(clk), .rst(rst), 
-	      .in1({adc_i_ofs,6'd0}), .in2(corr_i[35:12]), .strobe_in(1'b1),
+	      .in1(adc_i_ofs), .in2(corr_i[35:12]), .strobe_in(1'b1),
 	      .sum(i_out), .strobe_out());
 	   
 	   add2_and_clip_reg #(.WIDTH(24)) add_clip_q
 	     (.clk(clk), .rst(rst), 
-	      .in1({adc_q_ofs,6'd0}), .in2(corr_q[35:12]), .strobe_in(1'b1),
+	      .in1(adc_q_ofs), .in2(corr_q[35:12]), .strobe_in(1'b1),
 	      .sum(q_out), .strobe_out());
 	end // if (IQCOMP_EN == 1)
       else
 	begin
-	   rx_dcoffset #(.WIDTH(24),.ADDR(BASE+3)) rx_dcoffset_i
-	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-	      .in({adc_i,8'b00}),.out(i_out));
-	   
-	   rx_dcoffset #(.WIDTH(24),.ADDR(BASE+4)) rx_dcoffset_q
-	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-	      .in({adc_q,8'b00}),.out(q_out));
+	   assign i_out = adc_i_ofs;
+	   assign q_out = adc_q_ofs;
 	end // else: !if(IQCOMP_EN == 1)
-      endgenerate
+   endgenerate
    
 endmodule // rx_frontend
diff --git a/fpga/usrp3/lib/dsp/rx_frontend_tb.v b/fpga/usrp3/lib/dsp/rx_frontend_tb.v
index 487b72687..f84b4ddc6 100644
--- a/fpga/usrp3/lib/dsp/rx_frontend_tb.v
+++ b/fpga/usrp3/lib/dsp/rx_frontend_tb.v
@@ -13,21 +13,21 @@ module rx_frontend_tb();
    initial $dumpvars(0,rx_frontend_tb);
 
    reg [15:0] adc_in;
-   wire [17:0] adc_out;
+   wire [23:0] adc_out;
 
    always @(posedge clk)
      begin
-	if(adc_in[13])
+	if(adc_in[15])
 	  $write("-%d,",-adc_in);
 	else
 	  $write("%d,",adc_in);
-	if(adc_out[13])
+	if(adc_out[23])
 	  $write("-%d\n",-adc_out);
 	else
 	  $write("%d\n",adc_out);
      end	
    
-   rx_frontend #(.BASE(0)) rx_frontend
+   rx_frontend #(.BASE(0), .IQCOMP_EN(1)) rx_frontend
      (.clk(clk),.rst(rst),
       .set_stb(0),.set_addr(0),.set_data(0),
       .adc_a(adc_in), .adc_ovf_a(0),
diff --git a/fpga/usrp3/lib/dsp/sign_extend.v b/fpga/usrp3/lib/dsp/sign_extend.v
index eae67faf2..7c85920aa 100644
--- a/fpga/usrp3/lib/dsp/sign_extend.v
+++ b/fpga/usrp3/lib/dsp/sign_extend.v
@@ -4,19 +4,7 @@
 //
 //  Copyright (C) 2003 Matt Ettus
 //
-//  This program is free software; you can redistribute it and/or modify
-//  it under the terms of the GNU General Public License as published by
-//  the Free Software Foundation; either version 2 of the License, or
-//  (at your option) any later version.
-//
-//  This program is distributed in the hope that it will be useful,
-//  but WITHOUT ANY WARRANTY; without even the implied warranty of
-//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//  GNU General Public License for more details.
-//
-//  You should have received a copy of the GNU General Public License
-//  along with this program; if not, write to the Free Software
-//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+
 //
 
 
diff --git a/fpga/usrp3/lib/dsp/small_hb_dec.v b/fpga/usrp3/lib/dsp/small_hb_dec.v
index c05a48b81..fc776c2d7 100644
--- a/fpga/usrp3/lib/dsp/small_hb_dec.v
+++ b/fpga/usrp3/lib/dsp/small_hb_dec.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 // Short halfband decimator (intended to be followed by another stage)
 // Implements impulse responses of the form [A 0 B 0.5 B 0 A]
diff --git a/fpga/usrp3/lib/dsp/small_hb_int.v b/fpga/usrp3/lib/dsp/small_hb_int.v
index ff17069cc..4b03b5d0c 100644
--- a/fpga/usrp3/lib/dsp/small_hb_int.v
+++ b/fpga/usrp3/lib/dsp/small_hb_int.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 // Short halfband decimator (intended to be followed by another stage)
 // Implements impulse responses of the form [A 0 B 0.5 B 0 A]
diff --git a/fpga/usrp3/lib/dsp/srl.v b/fpga/usrp3/lib/dsp/srl.v
index 6df226e8f..bbd8ac1c9 100644
--- a/fpga/usrp3/lib/dsp/srl.v
+++ b/fpga/usrp3/lib/dsp/srl.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 module srl
diff --git a/fpga/usrp3/lib/dsp/tx_frontend.v b/fpga/usrp3/lib/dsp/tx_frontend.v
new file mode 100644
index 000000000..cbb8aa6b2
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/tx_frontend.v
@@ -0,0 +1,97 @@
+
+module tx_frontend
+  #(parameter BASE=0,
+    parameter WIDTH_OUT=16,
+    parameter IQCOMP_EN=1)
+   (input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [23:0] tx_i, input [23:0] tx_q, input run,
+    output reg [WIDTH_OUT-1:0] dac_a, output reg [WIDTH_OUT-1:0] dac_b
+    );
+
+   // IQ balance --> DC offset --> rounding --> mux
+
+   wire [23:0] i_dco, q_dco, i_ofs, q_ofs;
+   wire [WIDTH_OUT-1:0] i_final, q_final;
+   wire [7:0]  mux_ctrl;
+   wire [35:0] corr_i, corr_q;
+   wire [23:0] i_bal, q_bal;
+   wire [17:0] mag_corr, phase_corr;
+   
+   setting_reg #(.my_addr(BASE+0), .width(24)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(i_dco),.changed());
+
+   setting_reg #(.my_addr(BASE+1), .width(24)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(q_dco),.changed());
+
+   setting_reg #(.my_addr(BASE+2),.width(18)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(mag_corr),.changed());
+   
+   setting_reg #(.my_addr(BASE+3),.width(18)) sr_3
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_corr),.changed());
+  
+   setting_reg #(.my_addr(BASE+4), .width(8)) sr_4
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(mux_ctrl),.changed());
+
+   generate
+      if(IQCOMP_EN==1)
+	begin
+	   // IQ Balance
+	   MULT18X18S mult_mag_corr
+	     (.P(corr_i), .A(tx_i[23:6]), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); 
+	   
+	   MULT18X18S mult_phase_corr
+	     (.P(corr_q), .A(tx_i[23:6]), .B(phase_corr), .C(clk), .CE(1), .R(rst) );
+	   
+	   add2_and_clip_reg #(.WIDTH(24)) add_clip_i
+	     (.clk(clk), .rst(rst), 
+	      .in1(tx_i), .in2(corr_i[35:12]), .strobe_in(1'b1),
+	      .sum(i_bal), .strobe_out());
+	   
+	   add2_and_clip_reg #(.WIDTH(24)) add_clip_q
+	     (.clk(clk), .rst(rst), 
+	      .in1(tx_q), .in2(corr_q[35:12]), .strobe_in(1'b1),
+	      .sum(q_bal), .strobe_out());
+	end // if (IQCOMP_EN==1)
+      else
+	begin
+	   assign i_bal = tx_i;
+	   assign q_bal = tx_q;
+	end // else: !if(IQCOMP_EN==1)
+   endgenerate
+   
+   // DC Offset
+   add2_and_clip_reg #(.WIDTH(24)) add_dco_i
+     (.clk(clk), .rst(rst), .in1(i_dco), .in2(i_bal), .strobe_in(1'b1), .sum(i_ofs), .strobe_out());
+   
+   add2_and_clip_reg #(.WIDTH(24)) add_dco_q
+     (.clk(clk), .rst(rst), .in1(q_dco), .in2(q_bal), .strobe_in(1'b1), .sum(q_ofs), .strobe_out());
+   
+   // Rounding
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_i
+     (.clk(clk), .reset(rst), .in(i_ofs),.strobe_in(1'b1), .out(i_final), .strobe_out());
+
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_q
+     (.clk(clk), .reset(rst), .in(q_ofs),.strobe_in(1'b1), .out(q_final), .strobe_out());
+
+   // Mux
+   always @(posedge clk)
+     case(mux_ctrl[3:0])
+       0 : dac_a <= i_final;
+       1 : dac_a <= q_final;
+       default : dac_a <= 0;
+     endcase // case (mux_ctrl[3:0])
+      
+   always @(posedge clk)
+     case(mux_ctrl[7:4])
+       0 : dac_b <= i_final;
+       1 : dac_b <= q_final;
+       default : dac_b <= 0;
+     endcase // case (mux_ctrl[7:4])
+      
+endmodule // tx_frontend