Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 144 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/dsp/variable_delay_line.v b/fpga/usrp3/lib/dsp/variable_delay_line.v
new file mode 100644
index 000000000..ccef6172f
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/variable_delay_line.v
@@ -0,0 +1,144 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: variable_delay_line
+// Description: 
+//   This module implements a variable length delay line. It can be used
+//   in filter implementation where the delay is either variable and/or
+//   longer than a few flip-flops
+//
+// Parameters:
+//   - WIDTH: Width of data_in and data_out
+//   - DYNAMIC_DELAY: Is the delay variable (configurable at runtime)
+//   - DEPTH: The depth of the delay line. Must be greater than 2.
+//            The output delay can be between 0 and DEPTH-1.
+//            If DYNAMIC_DELAY==0, then this is the static delay
+//   - DEFAULT_DATA: Data to output if time post-delay is negative 
+//   - OUT_REG: Add an output register. This adds a cycle of latency
+//   - DEVICE: FPGA device family
+// Signals:
+//   - data_in  : Input sample value
+//   - stb_in   : Is input sample valid?
+//   - delay    : Delay value for output (Must be between 0 and DEPTH-1)
+//   - data_out : Output sample value. data_out is updated 1 clock
+//                cycle (2 if OUT_REG == 1) after assertion of delay
+//
+
+module variable_delay_line #(
+  parameter             WIDTH         = 18,
+  parameter             DEPTH         = 256,
+  parameter             DYNAMIC_DELAY = 0,
+  parameter [WIDTH-1:0] DEFAULT_DATA  = 0,
+  parameter             OUT_REG       = 0,
+  parameter             DEVICE        = "7SERIES"
+) (
+  input  wire                     clk,
+  input  wire                     clk_en,
+  input  wire                     reset,
+  input  wire [WIDTH-1:0]         data_in,
+  input  wire                     stb_in,
+  input  wire [$clog2(DEPTH)-1:0] delay,
+  output wire [WIDTH-1:0]         data_out
+);
+   //FIXME: Change to localparam when Vivado doesn't freak out
+   //       about the use of clog2.
+  parameter  ADDR_W = $clog2(DEPTH+1);
+  localparam DATA_W = WIDTH;
+
+  //-----------------------------------------------------------
+  // RAM State Machine: FIFO write, random access read
+  //-----------------------------------------------------------
+  wire              w_en;
+  wire [DATA_W-1:0] r_data, w_data;
+  wire [ADDR_W-1:0] r_addr;
+  reg  [ADDR_W-1:0] w_addr = {ADDR_W{1'b0}}, occupied = {ADDR_W{1'b0}};
+  reg  [1:0]        use_default = 2'b11;
+
+  // FIFO write, random access read
+  always @(posedge clk) begin
+    if (reset) begin
+      w_addr <= {ADDR_W{1'b0}};
+      occupied <= {ADDR_W{1'b0}};
+    end else if (w_en) begin
+      w_addr <= w_addr + 1'b1;
+      if (occupied != DEPTH) begin
+        occupied <= occupied + 1'b1;
+      end
+    end
+  end
+
+  // Logic to handle negative delays
+  always @(posedge clk) begin
+    if (reset) begin
+      use_default <= 2'b11;
+    end else if (clk_en && (occupied != 0)) begin
+      use_default <= {use_default[0], (r_addr >= occupied ? 1'b1 : 1'b0)};
+    end
+  end
+
+  assign w_en     = stb_in & clk_en;
+  assign w_data   = data_in;
+  assign r_addr   = (DYNAMIC_DELAY == 0) ? DEPTH : delay;
+  assign data_out = use_default[OUT_REG] ? DEFAULT_DATA : r_data;
+
+  //-----------------------------------------------------------
+  // Delay Line RAM Implementation
+  //-----------------------------------------------------------
+  // Use a delay line implementation based on the depth. 
+  // The DEVICE parameter is passed in but SPARTAN6,
+  // 7Series, Ultrascale and Ultrascale+ have the same 
+  // MACROs for SRLs so we don't use the param quite yet.
+
+  genvar i;
+  generate
+    if (ADDR_W == 4 || ADDR_W == 5) begin
+      // SRLs don't have an output register to instantiate
+      // that plus the pipeline register manually
+      wire [DATA_W-1:0] r_data_srl;
+      reg  [DATA_W-1:0] r_data_shreg[0:1];
+      always @(posedge clk) begin
+        if (clk_en)
+          {r_data_shreg[1], r_data_shreg[0]} <= {r_data_shreg[0], r_data_srl};
+      end
+      assign r_data = r_data_shreg[OUT_REG];
+
+      for (i = 0; i < DATA_W; i = i + 1) begin: bits
+        // Pick SRL based on address width
+        if (ADDR_W == 4) begin
+          SRL16E #(
+            .INIT(16'h0000), .IS_CLK_INVERTED(1'b0)
+          ) srl16e_i (
+            .CLK(clk), .CE(w_en),
+            .D(w_data[i]),
+            .A0(r_addr[0]),.A1(r_addr[1]),.A2(r_addr[2]),.A3(r_addr[3]),
+            .Q(r_data_srl[i])
+          );
+        end else begin
+          SRLC32E #(
+            .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)
+          ) srlc32e_i (
+            .CLK(clk), .CE(w_en),
+            .D(w_data[i]),
+            .A(r_addr),
+            .Q(r_data_srl[i]), .Q31()
+         );
+        end
+      end
+    end else begin
+      // For ADDR_W < 4, the RAM should ideally get 
+      // synthesized down to flip-flops.
+      ram_2port #(
+        .DWIDTH (DATA_W), .AWIDTH(ADDR_W),
+        .RW_MODE("NO-CHANGE"), .OUT_REG(OUT_REG)
+      ) ram_i (
+        .clka (clk), .ena(clk_en), .wea(w_en),
+        .addra(w_addr), .dia(w_data), .doa(),
+        .clkb (clk), .enb(clk_en), .web(1'b0),
+        .addrb(w_addr - r_addr - 1), .dib(), .dob(r_data)
+      );
+    end
+  endgenerate
+
+endmodule // delay_line
\ No newline at end of file