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| author | michael-west <michael.west@ettus.com> | 2014-03-25 15:59:03 -0700 |
|---|---|---|
| committer | michael-west <michael.west@ettus.com> | 2014-03-25 15:59:03 -0700 |
| commit | 04292f9b109479b639add31f83fd240a6387f488 (patch) | |
| tree | 4b8723a4ae63626029704f901ee0083bb23bc1e9 /fpga/usrp3/lib/dsp/rx_frontend_tb.v | |
| parent | 09915aa57bc88099cbcbbe925946ae65bc0ad8f0 (diff) | |
| parent | ff8a1252f3a51369abe0a165d963b781089ec66c (diff) | |
| download | uhd-04292f9b109479b639add31f83fd240a6387f488.tar.gz uhd-04292f9b109479b639add31f83fd240a6387f488.tar.bz2 uhd-04292f9b109479b639add31f83fd240a6387f488.zip | |
Merge branch 'master' into mwest/b200_docs
Diffstat (limited to 'fpga/usrp3/lib/dsp/rx_frontend_tb.v')
| -rw-r--r-- | fpga/usrp3/lib/dsp/rx_frontend_tb.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/fpga/usrp3/lib/dsp/rx_frontend_tb.v b/fpga/usrp3/lib/dsp/rx_frontend_tb.v index 487b72687..f84b4ddc6 100644 --- a/fpga/usrp3/lib/dsp/rx_frontend_tb.v +++ b/fpga/usrp3/lib/dsp/rx_frontend_tb.v @@ -13,21 +13,21 @@ module rx_frontend_tb(); initial $dumpvars(0,rx_frontend_tb); reg [15:0] adc_in; - wire [17:0] adc_out; + wire [23:0] adc_out; always @(posedge clk) begin - if(adc_in[13]) + if(adc_in[15]) $write("-%d,",-adc_in); else $write("%d,",adc_in); - if(adc_out[13]) + if(adc_out[23]) $write("-%d\n",-adc_out); else $write("%d\n",adc_out); end - rx_frontend #(.BASE(0)) rx_frontend + rx_frontend #(.BASE(0), .IQCOMP_EN(1)) rx_frontend (.clk(clk),.rst(rst), .set_stb(0),.set_addr(0),.set_data(0), .adc_a(adc_in), .adc_ovf_a(0), |