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| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp3/lib/dsp/clip.v | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp3/lib/dsp/clip.v')
| -rw-r--r-- | fpga/usrp3/lib/dsp/clip.v | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/fpga/usrp3/lib/dsp/clip.v b/fpga/usrp3/lib/dsp/clip.v deleted file mode 100644 index 294c5e8ba..000000000 --- a/fpga/usrp3/lib/dsp/clip.v +++ /dev/null @@ -1,24 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2008 Matt Ettus -// - -// - -// Clipping "macro", keeps the bottom bits - -module clip - #(parameter bits_in=0, - parameter bits_out=0) - (input [bits_in-1:0] in, - output [bits_out-1:0] out); - - wire overflow = |in[bits_in-1:bits_out-1] & ~(&in[bits_in-1:bits_out-1]); - assign out = overflow ? - (in[bits_in-1] ? {1'b1,{(bits_out-1){1'b0}}} : {1'b0,{(bits_out-1){1'b1}}}) : - in[bits_out-1:0]; - -endmodule // clip - |