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| author | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
|---|---|---|
| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
| commit | 0df4b801a34697f2058b4a7b95e08d2a0576c9db (patch) | |
| tree | be10e78d1a97c037a9e7492360a178d1873b9c09 /fpga/usrp3/lib/dsp/Makefile.srcs | |
| parent | 6e7bc850b66e8188718248b76b729c7cf9c89700 (diff) | |
| download | uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.gz uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.bz2 uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.zip | |
Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Diffstat (limited to 'fpga/usrp3/lib/dsp/Makefile.srcs')
| -rw-r--r-- | fpga/usrp3/lib/dsp/Makefile.srcs | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/dsp/Makefile.srcs b/fpga/usrp3/lib/dsp/Makefile.srcs new file mode 100644 index 000000000..3896ac5b5 --- /dev/null +++ b/fpga/usrp3/lib/dsp/Makefile.srcs @@ -0,0 +1,38 @@ +# +# Copyright 2013 Ettus Research LLC +# + +################################################## +# DSP Sources +################################################## +DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/dsp/, \ +ddc_chain.v \ +duc_chain.v \ +sign_extend.v \ +cordic_z24.v \ +clip_reg.v \ +cordic_stage.v \ +clip.v \ +cic_strober.v \ +cic_decim.v \ +cic_interp.v \ +cic_dec_shifter.v \ +cic_int_shifter.v \ +small_hb_dec.v \ +small_hb_int.v \ +hb_dec.v \ +hb_interp.v \ +round_sd.v \ +add2_and_clip_reg.v \ +add2_and_clip.v \ +add2.v \ +add2_reg.v \ +add2_and_round_reg.v \ +add2_and_round.v \ +round_reg.v \ +round.v \ +srl.v \ +acc.v \ +rx_frontend.v \ +rx_dcoffset.v \ +)) |