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author | michael-west <michael.west@ettus.com> | 2014-03-25 15:59:03 -0700 |
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committer | michael-west <michael.west@ettus.com> | 2014-03-25 15:59:03 -0700 |
commit | 04292f9b109479b639add31f83fd240a6387f488 (patch) | |
tree | 4b8723a4ae63626029704f901ee0083bb23bc1e9 /fpga/usrp3/lib/control/serial_to_settings.v | |
parent | 09915aa57bc88099cbcbbe925946ae65bc0ad8f0 (diff) | |
parent | ff8a1252f3a51369abe0a165d963b781089ec66c (diff) | |
download | uhd-04292f9b109479b639add31f83fd240a6387f488.tar.gz uhd-04292f9b109479b639add31f83fd240a6387f488.tar.bz2 uhd-04292f9b109479b639add31f83fd240a6387f488.zip |
Merge branch 'master' into mwest/b200_docs
Diffstat (limited to 'fpga/usrp3/lib/control/serial_to_settings.v')
-rw-r--r-- | fpga/usrp3/lib/control/serial_to_settings.v | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/fpga/usrp3/lib/control/serial_to_settings.v b/fpga/usrp3/lib/control/serial_to_settings.v index 53e112a62..3dcd80b23 100644 --- a/fpga/usrp3/lib/control/serial_to_settings.v +++ b/fpga/usrp3/lib/control/serial_to_settings.v @@ -10,7 +10,9 @@ module serial_to_settings // Settngs bus out output reg set_stb, output reg [7:0] set_addr, - output reg [31:0] set_data + output reg [31:0] set_data, + // Debug + output [31:0] debug ); reg [2:0] state; @@ -105,6 +107,14 @@ module serial_to_settings endcase // case(state) end // else: !if(reset) + + assign debug = + { + counter[4:0], + state[2:0], + scl_reg, + sda_reg + }; |