Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 113 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/control/regport_to_xbar_settingsbus.v b/fpga/usrp3/lib/control/regport_to_xbar_settingsbus.v
new file mode 100644
index 000000000..be050dd20
--- /dev/null
+++ b/fpga/usrp3/lib/control/regport_to_xbar_settingsbus.v
@@ -0,0 +1,113 @@
+/////////////////////////////////////////////////////////////////////
+//
+// Copyright 2017 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: regport_to_xbar_settingsbus
+// Description:
+//   Converts regport to xbar setting bus.
+//   The module is designed only for the crossbar. The readback bus for the
+//   rfnoc crossbar reads from the same address as it writes to. Also
+//   there is an extra cycle delay in read data in the crossbar, which is
+//   why the rb_stb needs to be delayed by a cycle.
+//
+//   ADDRESSING: Set to "WORD" in case of settings bus. The settings bus
+//   uses word addressing and hence the address needs to be shifted by
+//   to convert to set_addr.
+//
+/////////////////////////////////////////////////////////////////////
+
+module regport_to_xbar_settingsbus #(
+  parameter BASE   = 14'h0,
+  parameter END_ADDR = 14'h3FFF,
+  parameter DWIDTH = 32,
+  parameter AWIDTH = 14,
+  parameter SR_AWIDTH = 12,
+  // Dealign for settings bus by shifting by 2
+  parameter ADDRESSING = "WORD",
+  parameter SHIFT = $clog2(DWIDTH/8)
+  )(
+  input                   clk,
+  input                   reset,
+
+  input                   reg_wr_req,
+  input [AWIDTH-1:0]      reg_wr_addr,
+  input [DWIDTH-1:0]      reg_wr_data,
+
+  input                   reg_rd_req,
+  input [AWIDTH-1:0]      reg_rd_addr,
+  output [DWIDTH-1:0]     reg_rd_data,
+  output                  reg_rd_resp,
+
+  output                  set_stb,
+  output [SR_AWIDTH-1:0]  set_addr,
+  output [DWIDTH-1:0]     set_data,
+
+  output                  rb_stb,
+  output [SR_AWIDTH-1:0]  rb_addr,
+  input  [DWIDTH-1:0]     rb_data
+);
+
+  reg               reg_rd_req_delay;
+  reg               reg_rd_req_delay2;
+  wire [AWIDTH-1:0] set_addr_int;
+  reg [AWIDTH-1:0]  rb_addr_int;
+
+  always @(posedge clk) begin
+    if (reset) begin
+      reg_rd_req_delay <= 1'b0;
+      reg_rd_req_delay2 <= 1'b0;
+      rb_addr_int     <= 'd0;
+    end
+    else if (reg_rd_req) begin
+      rb_addr_int <= reg_rd_addr - BASE;
+      reg_rd_req_delay <= 1'b1;
+    end
+    else if (reg_rd_req_delay) begin
+      reg_rd_req_delay2 <= 1'b1;
+      reg_rd_req_delay <= 1'b0;
+    end
+    // Deassert after two clock cycles
+    else if (reg_rd_req_delay2) begin
+      reg_rd_req_delay <= 1'b0;
+      reg_rd_req_delay2 <= 1'b0;
+      rb_addr_int     <= 'd0;
+    end
+    else begin
+      reg_rd_req_delay <= 1'b0;
+      reg_rd_req_delay2 <= 1'b0;
+      rb_addr_int     <= 'd0;
+    end
+  end
+
+  // Write mode of settings bus
+  regport_to_settingsbus #(
+    .BASE(BASE),
+    .END_ADDR(END_ADDR),
+    .DWIDTH(DWIDTH),
+    .AWIDTH(AWIDTH),
+    .SR_AWIDTH(SR_AWIDTH),
+    .ADDRESSING(ADDRESSING)
+   ) xbar_write_settings_bus (
+    .clk(clk),
+    .reset(reset),
+    .reg_wr_req(reg_wr_req),
+    .reg_wr_addr(reg_wr_addr),
+    .reg_wr_data(reg_wr_data),
+
+    .set_stb(set_stb),
+    .set_addr(set_addr),
+    .set_data(set_data)
+  );
+
+  assign rb_addr = (ADDRESSING == "WORD") ? {{SHIFT{1'b0}}, rb_addr_int[SR_AWIDTH-1:SHIFT]}
+                                          : rb_addr_int[SR_AWIDTH-1:0];
+  // Strobe asserted two cycle after read request only when address is between BASE and END ADDR
+  // This is specific to the xbar as the xbar delays read data by an extra clock
+  // cycle to relax timing.
+  assign rb_stb  = reg_rd_req_delay2 && (reg_rd_addr >= BASE) && (reg_rd_addr <= END_ADDR);
+  assign reg_rd_resp = rb_stb;
+  assign reg_rd_data = rb_data;
+
+endmodule