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author | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
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committer | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
commit | 0df4b801a34697f2058b4a7b95e08d2a0576c9db (patch) | |
tree | be10e78d1a97c037a9e7492360a178d1873b9c09 /fpga/usrp3/lib/control/por_gen.v | |
parent | 6e7bc850b66e8188718248b76b729c7cf9c89700 (diff) | |
download | uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.gz uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.bz2 uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.zip |
Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Diffstat (limited to 'fpga/usrp3/lib/control/por_gen.v')
-rw-r--r-- | fpga/usrp3/lib/control/por_gen.v | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/control/por_gen.v b/fpga/usrp3/lib/control/por_gen.v new file mode 100644 index 000000000..0e4fcd88a --- /dev/null +++ b/fpga/usrp3/lib/control/por_gen.v @@ -0,0 +1,25 @@ +// +// Copyright 2013 Ettus Research LLC +// + + + +module por_gen + (input clk, + output reset_out); + + reg por_rst; + reg [7:0] por_counter = 8'h0; + + always @(posedge clk) + if (por_counter != 8'h55) + begin + por_counter <= por_counter + 8'h1; + por_rst <= 1'b1; + end + else + por_rst <= 1'b0; + + assign reset_out = por_rst; + +endmodule // por_gen |