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authorMartin Braun <martin.braun@ettus.com>2014-10-07 11:25:20 +0200
committerMartin Braun <martin.braun@ettus.com>2014-10-07 11:25:20 +0200
commitfd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch)
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parent3b66804e41891e358c790b453a7a59ec7462dba4 (diff)
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Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp3/lib/control/binary_encoder.v')
-rw-r--r--fpga/usrp3/lib/control/binary_encoder.v42
1 files changed, 0 insertions, 42 deletions
diff --git a/fpga/usrp3/lib/control/binary_encoder.v b/fpga/usrp3/lib/control/binary_encoder.v
deleted file mode 100644
index e13a8174b..000000000
--- a/fpga/usrp3/lib/control/binary_encoder.v
+++ /dev/null
@@ -1,42 +0,0 @@
-
-`define LOG2(N) (\
- N < 2 ? 0 : \
- N < 4 ? 1 : \
- N < 8 ? 2 : \
- N < 16 ? 3 : \
- N < 32 ? 4 : \
- N < 64 ? 5 : \
- N < 128 ? 6 : \
- N < 256 ? 7 : \
- N < 512 ? 8 : \
- N < 1024 ? 9 : \
- 10)
-
- module binary_encoder
- #(
- parameter SIZE = 16
- )
- (
- input [SIZE-1:0] in,
- output [`LOG2(SIZE)-1:0] out
- );
-
- genvar m,n;
-
- generate
- // Loop enough times to represent the total number of input bits as an encoded value
- for (m = 0; m <= `log2(SIZE-1); m = m + 1) begin: expand_or_tree
- wire [SIZE-1:0] encoding;
- // Build enable mask by iterating through every input bit.
- for (n = 0; n < SIZE ; n = n + 1) begin: encode_this_bit
- assign encoding[n] = n[m];
- end
- // OR tree for this output bit with appropraite bits enabled.
- assign out[m] = |(encoding & in);
- end
- endgenerate
-endmodule // binary_encoder
-
-
-
- \ No newline at end of file