Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 232 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/control/axi_forwarding_cam.v b/fpga/usrp3/lib/control/axi_forwarding_cam.v
new file mode 100644
index 000000000..64076bd0a
--- /dev/null
+++ b/fpga/usrp3/lib/control/axi_forwarding_cam.v
@@ -0,0 +1,232 @@
+//
+// Copyright 2013 Ettus Research LLC
+// Copyright 2018 Ettus Research, a National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This module implements a highly customized content-addressable memory (CAM)
+// that enables forwarding decisions to be made on a 16 bit field from a stream ID (SID) field.
+// The forwarding is generic in the sense that a SID's host destination can map to any endpoint / crossbar port.
+//
+// The 16 bits are allocated by convention as 8 bits of Network address (addresses USRP's / AXI crossbars) and
+// 8 bits of Host address (addresses endpoints / crossbar ports in a USRP).
+//
+// By definition if the destination field in the SID addresses a different
+// USRP / crossbar than this one then we don't care about the Host field, only the Network field.
+// We only look at the Host field when the Network field addresses us.
+// Thus we need a CAM of 256+256 entries with Log2(N) bits, where N is the number of
+// slave(output) ports on the crossbar switch.
+//
+// SID format:
+//
+// |---------|---------|---------|---------|
+// |   SRC   |   SRC   |   DST   |   DST   |
+// | NETWORK |   HOST  | NETWORK |   HOST  |
+// |---------|---------|---------|---------|
+//      8         8         8         8
+
+module axi_forwarding_cam
+  #(
+    parameter BASE = 0,      // BASE address for setting registers in this block. (512 addrs used)
+    parameter WIDTH=64,      // Bit width of FIFO word.
+    parameter NUM_OUTPUTS=2  // Number of outputs (destinations) in crossbar.
+    )
+    (
+     input 			  clk,
+     input 			  reset,
+     input 			  clear,
+     // Monitored FIFO signals
+     input [WIDTH-1:0] 		  o_tdata,
+     input 			  o_tvalid,
+     input 			  o_tready,
+     input 			  o_tlast,
+     input 			  pkt_present,
+     // Configuration
+     input [7:0] 		  local_addr,
+     // Setting Bus
+     input 			  set_stb,
+     input [15:0] 		  set_addr,
+     input [31:0] 		  set_data,
+
+     output reg [NUM_OUTPUTS-1:0] forward_valid,
+     input [NUM_OUTPUTS-1:0] 	  forward_ack,
+
+     input                        rb_rd_stb,
+     input [$clog2(NUM_OUTPUTS)-1:0] rb_addr,
+     output [31:0]                rb_data
+     );
+
+
+   localparam WAIT_SOF = 0;
+   localparam WAIT_EOF = 1;
+   reg 				  state;
+
+   localparam IDLE = 0;
+   localparam FORWARD = 1;
+   localparam WAIT = 2;
+
+   reg 	[1:0]			  demux_state;
+
+   reg [15:0] 			  dst;
+   reg 				  dst_valid, dst_valid_reg;
+   wire 			  local_dst;
+   wire [8:0] 			  read_addr;
+
+   //
+   // Monitor packets leaving FIFO
+   //
+   always @(posedge clk)
+     if (reset | clear) begin
+        state <= WAIT_SOF;
+     end else
+       case(state)
+	 //
+	 // After RESET or the EOF of previous packet, the first cycle with
+	 // output valid asserted is the SOF and presents the Header word.
+	 // The cycle following the concurrent presentation of asserted output
+	 // valid and output ready presents the word following the header.
+	 //
+         WAIT_SOF:
+           if (o_tvalid && o_tready) begin
+              state <= WAIT_EOF;
+           end else begin
+              state <= WAIT_SOF;
+           end
+	 //
+	 // EOF is signalled by o_tlast asserted whilst output valid and ready asserted.
+	 //
+         WAIT_EOF:
+           if (o_tlast && o_tvalid && o_tready) begin
+              state <= WAIT_SOF;
+           end else begin
+              state <= WAIT_EOF;
+           end
+       endcase // case(in_state)
+
+   //
+   // Extract Destination fields(s) from SID
+   //
+   always @(posedge clk)
+     if (reset | clear) begin
+	dst <= 0;
+	dst_valid <= 0;
+	dst_valid_reg <= 0;
+     end else if (o_tvalid && (state == WAIT_SOF) && pkt_present) begin
+	// SID will remain valid until o_tready is asserted as this will cause a state transition.
+	dst <= o_tdata[15:0];
+	dst_valid <= 1;
+	dst_valid_reg <= dst_valid;
+     end else begin
+	dst_valid <= 0;
+	dst_valid_reg <= dst_valid;
+     end
+
+   //
+   // Is Network field in DST our local address?
+   //
+   assign local_dst = (dst[15:8] == local_addr) && dst_valid;
+
+
+   //
+   // Mux address to RAM so that it searches CAM for Network field or Host field.
+   // Network addresses are stored in the lower 256 locations, host addresses the upper 256.
+   //
+   assign read_addr = {local_dst,(local_dst ? dst[7:0] : dst[15:8])};
+
+   //
+   // Implement CAM as block RAM here, 512xCeil(Log2(NUM_OUTPUTS))
+   //
+   //synthesis attribute ram_style of mem is block
+   reg [$clog2(NUM_OUTPUTS)-1 : 0] mem [0:511];
+
+   // Initialize the CAM's local address forwarding decisions with sensible defaults by
+   // assuming dst[7:4] = crossbar port, dst[3:0] = block port. Setup a one-to-one mapping
+   // for crossbar ports and always map same crossbar port regardless of block port.
+   // i.e.
+   //   dst 8'h00 => forward to crossbar port 0
+   //   dst 8'h01 => forward to crossbar port 0
+   //   dst 8'h10 => forward to crossbar port 1
+   // etc.
+   integer xbar_port;
+   integer block_port;
+   initial begin
+     for (xbar_port = 0; xbar_port < NUM_OUTPUTS; xbar_port = xbar_port + 1) begin
+       for (block_port = 0; block_port < 16; block_port = block_port + 1) begin
+         mem[256+(xbar_port << 4)+block_port] = xbar_port;
+       end
+     end
+   end
+
+   reg [8:0] 			   read_addr_reg;
+   wire 			   write;
+   wire [$clog2(NUM_OUTPUTS)-1:0] 	   read_data;
+
+   assign write = (set_addr[15:9] == (BASE >>9)) && set_stb; // Addr decode.
+
+   always @(posedge clk)
+     begin
+	read_addr_reg <= read_addr;
+
+	if (write) begin
+	   mem[set_addr[8:0]] <= set_data[$clog2(NUM_OUTPUTS)-1:0];
+	end
+
+     end
+
+   assign read_data = mem[read_addr_reg];
+
+
+   //
+   // State machine to manage forwarding flags.
+   //
+    always @(posedge clk)
+     if (reset | clear) begin
+        forward_valid <= {NUM_OUTPUTS{1'b0}};
+        demux_state <= IDLE;
+     end else
+       case(demux_state)
+
+	 // Wait for Valid DST which indicates a new packet lookup in the CAM.
+	 IDLE: begin
+	    if (dst_valid_reg == 1) begin
+	       forward_valid <= 1'b1 << read_data;
+	       demux_state <= FORWARD;
+	    end
+	 end
+	 // When Slave/Output thats forwarding ACK's the forward flag, clear request and wait for packet to be transfered
+	 FORWARD: begin
+	    if ((forward_ack & forward_valid) != 0) begin
+	       forward_valid <= {NUM_OUTPUTS{1'b0}};
+	       demux_state <= WAIT;
+	    end
+	 end
+	 // When packet transfered go back to idle.
+	 WAIT: begin
+	    if (forward_ack == 0)
+	      demux_state <= IDLE;
+	 end
+
+       endcase // case (demux_state)
+
+  //
+  // Compile forwarding statistics
+  // (This uses a lot of registers!)
+  //
+  genvar m;
+  reg [31:0] statistics [0:NUM_OUTPUTS-1];
+
+  generate
+    for (m = 0; m < NUM_OUTPUTS; m = m + 1) begin: generate_stats
+      always @(posedge clk) begin
+        if (reset | clear) begin
+          statistics[m] <= 0;
+        end else if (forward_ack[m] & forward_valid[m]) begin
+            statistics[m] <= statistics[m] + 1;
+        end
+      end
+    end
+  endgenerate
+
+  assign rb_data = statistics[rb_addr];
+
+endmodule