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| author | Andrew Moch <Andrew.Moch@ni.com> | 2021-02-05 10:48:24 -0600 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-06-03 11:26:54 -0500 |
| commit | d099fc3b032250bcc70e4c24f78d5eb6508850e1 (patch) | |
| tree | 13ca2469b1aa6b52e85beb53f00d610d6d65bdfc /fpga/usrp3/lib/axi4s_sv | |
| parent | 30b522b268aed6e7b4bc1a556e88d2a4b2fe6f77 (diff) | |
| download | uhd-d099fc3b032250bcc70e4c24f78d5eb6508850e1.tar.gz uhd-d099fc3b032250bcc70e4c24f78d5eb6508850e1.tar.bz2 uhd-d099fc3b032250bcc70e4c24f78d5eb6508850e1.zip | |
fpga: lib: add pause support to ethernet xport
Diffstat (limited to 'fpga/usrp3/lib/axi4s_sv')
| -rw-r--r-- | fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv index 0aa1daca0..d312b6f32 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv @@ -22,7 +22,7 @@ module axi4s_fifo #( ); `include "axi4s.vh" - + // Parameter Checks initial begin assert (i.DATA_WIDTH == o.DATA_WIDTH) else |