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| author | Wade Fife <wade.fife@ettus.com> | 2022-05-26 15:15:16 -0500 |
|---|---|---|
| committer | skooNI <60897865+skooNI@users.noreply.github.com> | 2022-07-20 15:57:20 -0500 |
| commit | f41f050ef89fc977ba5accbaa26b2175f2de4a5e (patch) | |
| tree | acc9004719eb397ddbeeb28eb31d696872f59941 /fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv | |
| parent | 6b8df1055498181eb6fb82dd1ebb1cc573ac48d5 (diff) | |
| download | uhd-f41f050ef89fc977ba5accbaa26b2175f2de4a5e.tar.gz uhd-f41f050ef89fc977ba5accbaa26b2175f2de4a5e.tar.bz2 uhd-f41f050ef89fc977ba5accbaa26b2175f2de4a5e.zip | |
fpga: Fix first arg in calls to $fatal()
This fixes warnings regarding the first argument to $fatal(), which is
supposed to be a number indicating what diagnostics to display. 1
corresponds to "Prints simulation time and location".
Diffstat (limited to 'fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv')
| -rw-r--r-- | fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv index 382cdb13b..9522a356a 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv @@ -69,11 +69,11 @@ module axi4s_remove_bytes #( localparam MIDDLE = END_BYTE >= START_BYTE; `include "axi4s.vh" - + // Parameter Checks initial begin assert (i.DATA_WIDTH == o.DATA_WIDTH) else - $fatal("DATA_WIDTH mismatch"); + $fatal(1, "DATA_WIDTH mismatch"); end AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH), @@ -162,7 +162,7 @@ module axi4s_remove_bytes #( //----------------------------------------------------------------------- function automatic logic [START_BYTE*8-1:0] start_part([s0.DATA_WIDTH-1:0] data); begin - // workaround :: modelsim optimizer can fail if there is aposibility of a 0+:0 + // workaround :: modelsim optimizer can fail if there is a possibility of a 0+:0 localparam MY_START_BYTE = START_BYTE ? START_BYTE : 1; return data[0+:MY_START_BYTE*8]; end @@ -468,7 +468,6 @@ module axi4s_remove_bytes #( // the WRAP case leans forward one word since it bridges to // the next word so it needs to reach end_plus early - // REMOVE statemachine always_comb begin : reached_end_comb if (MCASE==MS_WRAP) begin reached_end = s0.reached_packet_byte(REM_END); @@ -487,7 +486,7 @@ module axi4s_remove_bytes #( logic s0_tready; always_comb s0.tready = s0_tready; - // Remove Statemachine + // Remove State Machine always_comb begin : remove_next_state // default assignment of next_state next_remove_state = remove_state; |