fpga: lib: Add synthesizable AXI4-Stream SV components

Components are connected together with AxiStreamIfc. Some features
include:
  (1) Add bytes to the start of a packet
  (2) Remove bytes from a packet
  (3) Wrappers for some older components
      a.  fifo - buffer but imediately pass a packet
      b.  packet_gate - buffer and hold till end of packet
      c.  width_conv - cross clock domains and change width of axi bus

The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can
be used to connect to ports with continuous assignment.
AxiStreamPacketIf must be used procedurally but allows the following
new methods:
  - reached_packet_byte - notify when tdata contains a paritcular byte
  - get_packet_byte/get_packet_field - extract a byte or field from axi
  - put_packet_byte/put_packet_field - overwrite a byte or field onto axi

1 files changed, 51 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s.vh b/fpga/usrp3/lib/axi4s_sv/axi4s.vh
new file mode 100644
index 000000000..1a0b80256
--- /dev/null
+++ b/fpga/usrp3/lib/axi4s_sv/axi4s.vh
@@ -0,0 +1,51 @@
+//
+// Copyright 2020 Ettus Research, A National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Header File: axi4s
+// Description: Macros for use with AXI4S
+//
+
+//-----------------------------------------------------------------------------
+// Unidirectional AXI4-Stream interface
+//-----------------------------------------------------------------------------
+
+// Macro that drives o from i for all fields. Of course ready runs in the
+// counter direction.
+
+`define AXI4S_ASSIGN(O,I) \
+  if (``I.TDATA) ``O.tdata = ``I.tdata;\
+  if (``I.TUSER) ``O.tuser = ``I.tuser;\
+  else           ``O.tuser = 0;\
+  if (``I.TKEEP) ``O.tkeep = ``I.tkeep;\
+  else           ``O.tkeep = '1;\
+  if (``I.TLAST) ``O.tlast = ``I.tlast;\
+  ``O.tvalid = ``I.tvalid;\
+  ``I.tready = ``O.tready;
+
+`define AXI4S_DEBUG_ASSIGN(O,I) \
+  (* mark_debug = "true" *) logic [``I.DATA_WIDTH-1:0]   ``I``_debug_tdata;\
+  (* mark_debug = "true" *) logic [``I.USER_WIDTH-1:0]   ``I``_debug_tuser;\
+  (* mark_debug = "true" *) logic [``I.DATA_WIDTH/8-1:0] ``I``_debug_tkeep;\
+  (* mark_debug = "true" *) logic                        ``I``_debug_tlast;\
+  (* mark_debug = "true" *) logic                        ``I``_debug_tvalid;\
+  (* mark_debug = "true" *) logic                        ``I``_debug_tready;\
+  always_comb begin\
+    if (``I.TDATA) ``I``_debug_tdata = ``I.tdata;\
+    if (``I.TUSER) ``I``_debug_tuser = ``I.tuser;\
+    if (``I.TKEEP) ``I``_debug_tkeep = ``I.tkeep;\
+    if (``I.TLAST) ``I``_debug_tlast = ``I.tlast;\
+    ``I``_debug_tvalid = ``I.tvalid;\
+    ``I``_debug_tready = ``O.tready;\
+  end\
+  always_comb begin\
+    if (``I.TDATA) ``O.tdata = ``I``_debug_tdata;\
+    if (``I.TUSER) ``O.tuser = ``I``_debug_tuser;\
+    else           ``O.tuser = 0;\
+    if (``I.TKEEP) ``O.tkeep = ``I``_debug_tkeep;\
+    else           ``O.tkeep = '1;\
+    if (``I.TLAST) ``O.tlast = ``I``_debug_tlast;\
+    ``O.tvalid = ``I``_debug_tvalid;\
+    ``I.tready = ``I``_debug_tready;\
+  end