Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 104 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/axi/axis_upsizer.v b/fpga/usrp3/lib/axi/axis_upsizer.v
new file mode 100644
index 000000000..07e313e2d
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axis_upsizer.v
@@ -0,0 +1,104 @@
+//
+// Copyright 2018 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_upsizer
+// Description: 
+//   An AXI-Stream width conversion module that widens the input
+//   sample with by a factor of RATIO.
+//   NOTE: This module has end-to-end combanitorial paths. For a
+//         pipelined version, please use axis_width_conv
+//
+// Parameters:
+//   - IN_DATA_W: The bitwidth of the input data bus. The width of the
+//                output data bus is IN_DATA_W*RATIO
+//   - IN_USER_W: The bitwidth of the input user bus. The width of the
+//                output user bus is IN_USER_W*RATIO
+//   - RATIO: The upsizing ratio
+//
+// Signals:
+//   - s_axis_* : Input sample stream (AXI-Stream)
+//   - m_axis_* : Output sample stream (AXI-Stream)
+
+module axis_upsizer #(
+  parameter IN_DATA_W = 32,
+  parameter IN_USER_W = 1,
+  parameter RATIO     = 4
+)(
+  // Clock, reset and settings
+  input  wire                         clk,              // Clock
+  input  wire                         reset,            // Reset
+  // Data In (AXI-Stream)              
+  input  wire [IN_DATA_W-1:0]         s_axis_tdata,     // Input stream tdata
+  input  wire [IN_USER_W-1:0]         s_axis_tuser,     // Input stream tuser
+  input  wire                         s_axis_tlast,     // Input stream tlast
+  input  wire                         s_axis_tvalid,    // Input stream tvalid
+  output wire                         s_axis_tready,    // Input stream tready
+  // Data Out (AXI-Stream)             
+  output wire [(IN_DATA_W*RATIO)-1:0] m_axis_tdata,     // Output stream tdata
+  output wire [(IN_USER_W*RATIO)-1:0] m_axis_tuser,     // Output stream tuser
+  output wire [RATIO-1:0]             m_axis_tkeep,     // Output stream tkeep
+  output wire                         m_axis_tlast,     // Output stream tlast
+  output wire                         m_axis_tvalid,    // Output stream tvalid
+  input  wire                         m_axis_tready     // Output stream tready
+);
+
+  genvar i;
+  generate if (RATIO != 1) begin
+    // Constants
+    localparam [$clog2(RATIO)-1:0] SEL_FIRST  = 'd0;
+    localparam [$clog2(RATIO)-1:0] SEL_LAST   = RATIO-1;
+    localparam [RATIO-1:0]         KEEP_FIRST = {{(RATIO-1){1'b0}}, 1'b1};
+    localparam [RATIO-1:0]         KEEP_ALL   = {(RATIO){1'b1}};
+  
+    // Keep a binary-coded and one-hot version of the current
+    // section of the output that is being processed.
+    reg [$clog2(RATIO)-1:0] select = SEL_FIRST;
+    reg [RATIO-1:0]         keep   = KEEP_FIRST;
+    // Cached data. Incomplete output word.
+    reg [IN_DATA_W-1:0] cached_data[0:RATIO-2];
+    reg [IN_USER_W-1:0] cached_user[0:RATIO-2];
+
+    // State machine to drive the select bits for the
+    // output DEMUX.
+    always @(posedge clk) begin
+      if (reset) begin
+        select <= SEL_FIRST;
+        keep   <= KEEP_FIRST;
+      end else if (s_axis_tvalid & s_axis_tready) begin
+        select <= (select == SEL_LAST || s_axis_tlast) ? SEL_FIRST  : (select + 'd1);
+        keep   <= (keep   == KEEP_ALL || s_axis_tlast) ? KEEP_FIRST : {keep[RATIO-2:0], 1'b1};
+        cached_data[select] <= s_axis_tdata;
+        cached_user[select] <= s_axis_tuser;
+      end
+    end
+
+    // The output DEMUX
+    for (i = 0; i < RATIO; i=i+1) begin
+      if (i == SEL_LAST) begin
+        assign m_axis_tdata[(i*IN_DATA_W)+:IN_DATA_W] = s_axis_tdata;
+        assign m_axis_tuser[(i*IN_USER_W)+:IN_USER_W] = s_axis_tuser;
+      end else begin
+        assign m_axis_tdata[(i*IN_DATA_W)+:IN_DATA_W] = keep[i+1] ? cached_data[i] : s_axis_tdata;
+        assign m_axis_tuser[(i*IN_USER_W)+:IN_USER_W] = keep[i+1] ? cached_user[i] : s_axis_tuser;
+      end
+    end
+    assign m_axis_tkeep   = keep;
+    assign m_axis_tlast   = s_axis_tlast;
+    assign m_axis_tvalid  = s_axis_tvalid & ((keep == KEEP_ALL) | s_axis_tlast);
+    assign s_axis_tready  = m_axis_tvalid ? m_axis_tready : s_axis_tvalid;
+
+  end else begin  // if (RATIO != 1)
+
+    // Passthrough
+    assign m_axis_tdata   = s_axis_tdata;
+    assign m_axis_tuser   = s_axis_tuser;
+    assign m_axis_tkeep   = 1'b1;
+    assign m_axis_tlast   = s_axis_tlast;
+    assign m_axis_tvalid  = s_axis_tvalid;
+    assign s_axis_tready  = m_axis_tready;
+
+  end endgenerate
+
+endmodule // axis_upsizer