Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 125 insertions, 0 deletions

diff --git a/fpga/usrp3/lib/axi/axis_data_swap.v b/fpga/usrp3/lib/axi/axis_data_swap.v
new file mode 100644
index 000000000..2408ab6c6
--- /dev/null
+++ b/fpga/usrp3/lib/axi/axis_data_swap.v
@@ -0,0 +1,125 @@
+//
+// Copyright 2019 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axis_data_swap
+// Description:
+//  A generic data swapper module for AXI-Stream. The contents of
+//  tdata are swapped based on the tswap signal. For each bit 'i'
+//  in tswap, adjacent words of width 2^i are swapped if tswap[i]
+//  is high. For example, if tswap[3] = 1, then each byte in tdata
+//  will be swapped with its adjacent neighbor. It is permissible
+//  for tswap to change for each transfer in an AXIS packet.
+//  Swapping can also be configured to be static (zero logic) by
+//  setting DYNAMIC = 0. To reduce area, certain swap stages can
+//  even be disabled. For example, if STAGES_EN[2:0] is set to 0
+//  then the lowest granularity for swaps will be a byte.
+//
+// Parameters:
+//   - DATA_W: Width of the tdata bus in bits
+//   - USER_W: Width of the tuser bus in bits
+//   - STAGES_EN: Which swap stages are enabled.
+//   - DYNAMIC: Dynamic swapping enabled (use tswap)
+//
+// Signals:
+//   - s_axis_*: The input AXI stream
+//   - m_axis_*: The output AXI stream
+//
+
+module axis_data_swap #(
+  parameter integer              DATA_W    = 256,
+  parameter integer              USER_W    = 1,
+  parameter [$clog2(DATA_W)-1:0] STAGES_EN = 'hFFFFFFFF, //@HACK: Vivado does not allow $clog2 in value of this expr
+  parameter [0:0]                DYNAMIC   = 1
+)(
+  // Clock and Reset
+  input  wire                      clk,
+  input  wire                      rst,
+  // Input AXIS
+  input  wire [DATA_W-1:0]         s_axis_tdata,
+  input  wire [$clog2(DATA_W)-2:0] s_axis_tswap,
+  input  wire [USER_W-1:0]         s_axis_tuser,
+  input  wire                      s_axis_tlast,
+  input  wire                      s_axis_tvalid,
+  output wire                      s_axis_tready,
+  // Output AXIS                   
+  output wire [DATA_W-1:0]         m_axis_tdata,
+  output wire [USER_W-1:0]         m_axis_tuser,
+  output wire                      m_axis_tlast,
+  output wire                      m_axis_tvalid,
+  input  wire                      m_axis_tready
+);
+
+  parameter SWAP_STAGES = $clog2(DATA_W);
+  parameter SWAP_W      = $clog2(DATA_W)-1;
+  genvar s, w;
+
+  wire [DATA_W-1:0] stg_tdata [0:SWAP_STAGES], stg_tdata_swp[0:SWAP_STAGES], stg_tdata_res[0:SWAP_STAGES];
+  wire [SWAP_W-1:0] stg_tswap [0:SWAP_STAGES];
+  wire [USER_W-1:0] stg_tuser [0:SWAP_STAGES];
+  wire              stg_tlast [0:SWAP_STAGES];
+  wire              stg_tvalid[0:SWAP_STAGES];
+  wire              stg_tready[0:SWAP_STAGES];
+
+  // Connect input and output to stage wires
+  generate
+    assign stg_tdata [0] = s_axis_tdata;
+    assign stg_tswap [0] = s_axis_tswap;
+    assign stg_tuser [0] = s_axis_tuser;
+    assign stg_tlast [0] = s_axis_tlast;
+    assign stg_tvalid[0] = s_axis_tvalid;
+    assign s_axis_tready = stg_tready[0];
+
+    assign m_axis_tdata            = stg_tdata [SWAP_STAGES];
+    assign m_axis_tuser            = stg_tuser [SWAP_STAGES];
+    assign m_axis_tlast            = stg_tlast [SWAP_STAGES];
+    assign m_axis_tvalid           = stg_tvalid[SWAP_STAGES];
+    assign stg_tready[SWAP_STAGES] = m_axis_tready;
+  endgenerate
+
+  // Instantiate AXIS flip-flops for each stage
+  generate
+    for (s = 0; s < SWAP_STAGES; s=s+1) begin
+      if (STAGES_EN[SWAP_STAGES-s-1]) begin
+        // Swap Logic
+        for (w = 0; w < (1<<s); w=w+1) begin
+          assign stg_tdata_swp[s][(w*(DATA_W/(1<<s)))+:(DATA_W/(1<<s))] =
+            stg_tdata[s][(((1<<s)-w-1)*(DATA_W/(1<<s)))+:(DATA_W/(1<<s))];
+        end
+        if (DYNAMIC) begin
+          // Honor tswap in DYNAMIC mode.
+          // Also add a flip_flop to break the long start-to-end critical path
+          assign stg_tdata_res[s] = (s > 0 && stg_tswap[s][SWAP_W-s]) ?
+            stg_tdata_swp[s] : stg_tdata[s];
+          // Flip-flop
+          axi_fifo_flop #(.WIDTH(DATA_W+SWAP_W+USER_W+1)) reg_i (
+            .clk(clk), .reset(rst), .clear(1'b0),
+            .i_tdata({stg_tlast[s], stg_tuser[s], stg_tswap[s], stg_tdata_res[s]}),
+            .i_tvalid(stg_tvalid[s]), .i_tready(stg_tready[s]),
+            .o_tdata({stg_tlast[s+1], stg_tuser[s+1], stg_tswap[s+1], stg_tdata[s+1]}),
+            .o_tvalid(stg_tvalid[s+1]), .o_tready(stg_tready[s+1]),
+            .occupied(), .space()
+          );
+        end else begin
+          // Static swapping logic
+          assign stg_tdata [s+1] = stg_tdata_swp[s];
+          assign stg_tswap [s+1] = stg_tswap    [s];
+          assign stg_tuser [s+1] = stg_tuser    [s];
+          assign stg_tlast [s+1] = stg_tlast    [s];
+          assign stg_tvalid[s+1] = stg_tvalid   [s];
+          assign stg_tready[s]   = stg_tready   [s+1];
+        end
+      end else begin
+        // Skip this stage
+        assign stg_tdata [s+1] = stg_tdata [s];
+        assign stg_tswap [s+1] = stg_tswap [s];
+        assign stg_tuser [s+1] = stg_tuser [s];
+        assign stg_tlast [s+1] = stg_tlast [s];
+        assign stg_tvalid[s+1] = stg_tvalid[s];
+        assign stg_tready[s]   = stg_tready[s+1];
+      end
+    end
+  endgenerate
+
+endmodule // axis_data_swap