diff options
| author | Josh Blum <josh@joshknows.com> | 2010-11-23 13:36:42 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-23 13:36:42 -0800 |
| commit | bb0572a960edf54486a4be746c681adaac0fa398 (patch) | |
| tree | 7afb46e99eaf799a478fcde841eb78d7698e9c39 /fpga/usrp2 | |
| parent | 8ce75a3ca7a51f4bdee87d78a610a0f2519473ae (diff) | |
| download | uhd-bb0572a960edf54486a4be746c681adaac0fa398.tar.gz uhd-bb0572a960edf54486a4be746c681adaac0fa398.tar.bz2 uhd-bb0572a960edf54486a4be746c681adaac0fa398.zip | |
fpga: performed a forceful checkout of fpga to overwrite with current fpga code
Diffstat (limited to 'fpga/usrp2')
121 files changed, 11263 insertions, 1085 deletions
diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs index bc8e4d5bc..d3bb7e2c8 100644 --- a/fpga/usrp2/control_lib/Makefile.srcs +++ b/fpga/usrp2/control_lib/Makefile.srcs @@ -21,6 +21,7 @@ nsgpio.v \ ram_2port.v \ ram_harv_cache.v \ ram_harvard.v \ +ram_harvard2.v \ ram_loader.v \ setting_reg.v \ settings_bus.v \ @@ -29,6 +30,7 @@ srl.v \ system_control.v \ wb_1master.v \ wb_readback_mux.v \ +quad_uart.v \ simple_uart.v \ simple_uart_tx.v \ simple_uart_rx.v \ @@ -42,4 +44,9 @@ pic.v \ longfifo.v \ shortfifo.v \ medfifo.v \ +s3a_icap_wb.v \ +bootram.v \ +nsgpio16LE.v \ +settings_bus_16LE.v \ +atr_controller16.v \ )) diff --git a/fpga/usrp2/control_lib/atr_controller16.v b/fpga/usrp2/control_lib/atr_controller16.v new file mode 100644 index 000000000..3d8b5b1e9 --- /dev/null +++ b/fpga/usrp2/control_lib/atr_controller16.v @@ -0,0 +1,60 @@ + +// Automatic transmit/receive switching of control pins to daughterboards +// Store everything in registers for now, but could use a RAM for more +// complex state machines in the future + +module atr_controller16 + (input clk_i, input rst_i, + input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o, + input we_i, input stb_i, input cyc_i, output reg ack_o, + input run_rx, input run_tx, input [31:0] master_time, + output [31:0] ctrl_lines); + + reg [3:0] state; + reg [31:0] atr_ram [0:15]; // DP distributed RAM + + wire [3:0] sel_int = { (sel_i[1] & adr_i[1]), (sel_i[0] & adr_i[1]), + (sel_i[1] & ~adr_i[1]), (sel_i[0] & ~adr_i[1]) }; + + // WB Interface + always @(posedge clk_i) + if(we_i & stb_i & cyc_i) + begin + if(sel_int[3]) + atr_ram[adr_i[5:2]][31:24] <= dat_i[15:8]; + if(sel_int[2]) + atr_ram[adr_i[5:2]][23:16] <= dat_i[7:0]; + if(sel_int[1]) + atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8]; + if(sel_int[0]) + atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; + end // if (we_i & stb_i & cyc_i) + + always @(posedge clk_i) + dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0]; + + always @(posedge clk_i) + ack_o <= stb_i & cyc_i & ~ack_o; + + // Control side of DP RAM + assign ctrl_lines = atr_ram[state]; + + // Put a more complex state machine with time delays and multiple states here + // if daughterboard requires more complex sequencing + localparam ATR_IDLE = 4'd0; + localparam ATR_TX = 4'd1; + localparam ATR_RX = 4'd2; + localparam ATR_FULL_DUPLEX = 4'd3; + + always @(posedge clk_i) + if(rst_i) + state <= ATR_IDLE; + else + case ({run_rx,run_tx}) + 2'b00 : state <= ATR_IDLE; + 2'b01 : state <= ATR_TX; + 2'b10 : state <= ATR_RX; + 2'b11 : state <= ATR_FULL_DUPLEX; + endcase // case({run_rx,run_tx}) + +endmodule // atr_controller16 diff --git a/fpga/usrp2/control_lib/bootram.v b/fpga/usrp2/control_lib/bootram.v new file mode 100644 index 000000000..668012504 --- /dev/null +++ b/fpga/usrp2/control_lib/bootram.v @@ -0,0 +1,250 @@ + +// Boot RAM for S3A, 8KB, dual port + +// RAMB16BWE_S36_S36: 512 x 32 + 4 Parity bits byte-wide write Dual-Port RAM +// Spartan-3A Xilinx HDL Libraries Guide, version 10.1.1 + +module bootram + (input clk, input reset, + input [12:0] if_adr, + output [31:0] if_data, + + input [12:0] dwb_adr_i, + input [31:0] dwb_dat_i, + output [31:0] dwb_dat_o, + input dwb_we_i, + output reg dwb_ack_o, + input dwb_stb_i, + input [3:0] dwb_sel_i); + + wire [31:0] DOA0, DOA1, DOA2, DOA3; + wire [31:0] DOB0, DOB1, DOB2, DOB3; + wire ENB0, ENB1, ENB2, ENB3; + wire [3:0] WEB; + + reg [1:0] delayed_if_bank; + always @(posedge clk) + delayed_if_bank <= if_adr[12:11]; + + assign if_data = delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA3 : DOA2) : (delayed_if_bank[0] ? DOA1 : DOA0); + assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0); + + always @(posedge clk) + if(reset) + dwb_ack_o <= 0; + else + dwb_ack_o <= dwb_stb_i & ~dwb_ack_o; + + assign ENB0 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b00); + assign ENB1 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b01); + assign ENB2 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b10); + assign ENB3 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b11); + + assign WEB = {4{dwb_we_i}} & dwb_sel_i; + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM0 + (.DOA(DOA0), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input + + .DOB(DOB0), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB0), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM1 + (.DOA(DOA1), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input + + .DOB(DOB1), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB1), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM2 + (.DOA(DOA2), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input + + .DOB(DOB2), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB2), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM3 + (.DOA(DOA3), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input + + .DOB(DOB3), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB3), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + +endmodule // bootram + +/* + // The following INIT_xx declarations specify the initial contents of the RAM + // Address 0 to 127 + .INIT_00(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_01(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_02(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_03(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_04(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_05(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_06(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_07(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_08(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_09(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_0A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_0B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_0C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_0D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_0E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_0F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + // Address 128 to 255 + .INIT_10(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_11(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_12(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_13(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_14(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_15(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_16(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_17(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_18(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_19(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_1A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_1B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_1C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_1D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_1E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_1F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + // Address 256 to 383 + .INIT_20(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_21(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_22(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_23(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_24(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_25(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_26(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_27(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_28(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_29(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_2A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_2B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_2C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_2D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_2E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_2F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + // Address 384 to 511 + .INIT_30(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_31(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_32(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_33(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_34(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_35(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_36(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_37(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_38(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_39(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_3A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_3B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_3C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_3D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_3E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + .INIT_3F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), + // The next set of INITP_xx are for the parity bits + // Address 0 to 127 + .INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000), + // Address 128 to 255 + .INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000), + // Address 256 to 383 + .INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000), + // Address 384 to 511 + .INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000), + .INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000) +*/ diff --git a/fpga/usrp2/control_lib/newfifo/fifo_pacer.v b/fpga/usrp2/control_lib/newfifo/fifo_pacer.v new file mode 100644 index 000000000..1bf03ab6e --- /dev/null +++ b/fpga/usrp2/control_lib/newfifo/fifo_pacer.v @@ -0,0 +1,24 @@ + + +module fifo_pacer + (input clk, + input reset, + input [7:0] rate, + input enable, + input src1_rdy_i, output dst1_rdy_o, + output src2_rdy_o, input dst2_rdy_i, + output underrun, overrun); + + wire strobe; + + cic_strober strober (.clock(clk), .reset(reset), .enable(enable), + .rate(rate), .strobe_fast(1), .strobe_slow(strobe)); + + wire all_ready = src1_rdy_i & dst2_rdy_i; + assign dst1_rdy_o = all_ready & strobe; + assign src2_rdy_o = dst1_rdy_o; + + assign underrun = strobe & ~src1_rdy_i; + assign overrun = strobe & ~dst2_rdy_i; + +endmodule // fifo_pacer diff --git a/fpga/usrp2/control_lib/newfifo/packet32_tb.v b/fpga/usrp2/control_lib/newfifo/packet32_tb.v new file mode 100644 index 000000000..82bb09c29 --- /dev/null +++ b/fpga/usrp2/control_lib/newfifo/packet32_tb.v @@ -0,0 +1,27 @@ + + +module packet32_tb(); + + wire [35:0] data; + wire src_rdy, dst_rdy; + + wire clear = 0; + reg clk = 0; + reg reset = 1; + + always #10 clk <= ~clk; + initial #1000 reset <= 0; + + initial $dumpfile("packet32_tb.vcd"); + initial $dumpvars(0,packet32_tb); + + wire [31:0] total, crc_err, seq_err, len_err; + + packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear), + .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear), + .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet32_tb diff --git a/fpga/usrp2/control_lib/newfifo/packet_generator.v b/fpga/usrp2/control_lib/newfifo/packet_generator.v new file mode 100644 index 000000000..6e8b45ccd --- /dev/null +++ b/fpga/usrp2/control_lib/newfifo/packet_generator.v @@ -0,0 +1,59 @@ + + +module packet_generator + (input clk, input reset, input clear, + output reg [7:0] data_o, output sof_o, output eof_o, + output src_rdy_o, input dst_rdy_i); + + localparam len = 32'd2000; + + reg [31:0] state; + reg [31:0] seq; + wire [31:0] crc_out; + wire calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF); + + + always @(posedge clk) + if(reset | clear) + seq <= 0; + else + if(eof_o & src_rdy_o & dst_rdy_i) + seq <= seq + 1; + + always @(posedge clk) + if(reset | clear) + state <= 0; + else + if(src_rdy_o & dst_rdy_i) + if(state == (len - 1)) + state <= 32'hFFFF_FFFC; + else + state <= state + 1; + + always @* + case(state) + 0 : data_o <= len[7:0]; + 1 : data_o <= len[15:8]; + 2 : data_o <= len[23:16]; + 3 : data_o <= len[31:24]; + 4 : data_o <= seq[7:0]; + 5 : data_o <= seq[15:8]; + 6 : data_o <= seq[23:16]; + 7 : data_o <= seq[31:24]; + 32'hFFFF_FFFC : data_o <= crc_out[31:24]; + 32'hFFFF_FFFD : data_o <= crc_out[23:16]; + 32'hFFFF_FFFE : data_o <= crc_out[15:8]; + 32'hFFFF_FFFF : data_o <= crc_out[7:0]; + default : data_o <= state[7:0]; + endcase // case (state) + + assign src_rdy_o = 1; + assign sof_o = (state == 0); + assign eof_o = (state == 32'hFFFF_FFFF); + + wire clear_crc = eof_o & src_rdy_o & dst_rdy_i; + + crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), + .calc(calc_crc), .crc_out(crc_out), .match()); + +endmodule // packet_generator diff --git a/fpga/usrp2/control_lib/newfifo/packet_generator32.v b/fpga/usrp2/control_lib/newfifo/packet_generator32.v new file mode 100644 index 000000000..6f8004964 --- /dev/null +++ b/fpga/usrp2/control_lib/newfifo/packet_generator32.v @@ -0,0 +1,21 @@ + + +module packet_generator32 + (input clk, input reset, input clear, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + wire [7:0] ll_data; + wire ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy_n; + + packet_generator pkt_gen + (.clk(clk), .reset(reset), .clear(clear), + .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof), + .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n)); + + ll8_to_fifo36 ll8_to_f36 + (.clk(clk), .reset(reset), .clear(clear), + .ll_data(ll_data), .ll_sof_n(~ll_sof), .ll_eof_n(~ll_eof), + .ll_src_rdy_n(~ll_src_rdy), .ll_dst_rdy_n(ll_dst_rdy_n), + .f36_data(data_o), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i)); + +endmodule // packet_generator32 diff --git a/fpga/usrp2/control_lib/newfifo/packet_tb.v b/fpga/usrp2/control_lib/newfifo/packet_tb.v new file mode 100644 index 000000000..3c423d2ba --- /dev/null +++ b/fpga/usrp2/control_lib/newfifo/packet_tb.v @@ -0,0 +1,29 @@ + + +module packet_tb(); + + wire [7:0] data; + wire sof, eof, src_rdy, dst_rdy; + + wire clear = 0; + reg clk = 0; + reg reset = 1; + + always #10 clk <= ~clk; + initial #1000 reset <= 0; + + initial $dumpfile("packet_tb.vcd"); + initial $dumpvars(0,packet_tb); + + wire [31:0] total, crc_err, seq_err, len_err; + + packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear), + .data_o(data), .sof_o(sof), .eof_o(eof), + .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear), + .data_i(data), .sof_i(sof), .eof_i(eof), + .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet_tb diff --git a/fpga/usrp2/control_lib/newfifo/packet_verifier.v b/fpga/usrp2/control_lib/newfifo/packet_verifier.v new file mode 100644 index 000000000..b49ad1bbb --- /dev/null +++ b/fpga/usrp2/control_lib/newfifo/packet_verifier.v @@ -0,0 +1,61 @@ + + +// Packet format -- +// Line 1 -- Length, 32 bits +// Line 2 -- Sequence number, 32 bits +// Last line -- CRC, 32 bits + +module packet_verifier + (input clk, input reset, input clear, + input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o, + + output reg [31:0] total, + output reg [31:0] crc_err, + output reg [31:0] seq_err, + output reg [31:0] len_err); + + reg [31:0] seq_num; + reg [31:0] length; + wire first_byte, last_byte; + reg second_byte, last_byte_d1; + + wire calc_crc = src_rdy_i & dst_rdy_o; + + crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), + .calc(calc_crc), .crc_out(), .match(match_crc)); + + assign first_byte = src_rdy_i & dst_rdy_o & sof_i; + assign last_byte = src_rdy_i & dst_rdy_o & eof_i; + assign dst_rdy_o = ~last_byte_d1; + + // stubs for now + wire match_seq = 1; + wire match_len = 1; + + always @(posedge clk) + if(reset | clear) + last_byte_d1 <= 0; + else + last_byte_d1 <= last_byte; + + always @(posedge clk) + if(reset | clear) + begin + total <= 0; + crc_err <= 0; + seq_err <= 0; + len_err <= 0; + end + else + if(last_byte_d1) + begin + total <= total + 1; + if(~match_crc) + crc_err <= crc_err + 1; + else if(~match_seq) + seq_err <= seq_err + 1; + else if(~match_len) + seq_err <= len_err + 1; + end + +endmodule // packet_verifier diff --git a/fpga/usrp2/control_lib/newfifo/packet_verifier32.v b/fpga/usrp2/control_lib/newfifo/packet_verifier32.v new file mode 100644 index 000000000..06a13d242 --- /dev/null +++ b/fpga/usrp2/control_lib/newfifo/packet_verifier32.v @@ -0,0 +1,30 @@ + + +module packet_verifier32 + (input clk, input reset, input clear, + input [35:0] data_i, input src_rdy_i, output dst_rdy_o, + output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err); + + wire [7:0] ll_data; + wire ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy; + wire [35:0] data_int; + wire src_rdy_int, dst_rdy_int; + + fifo_short #(.WIDTH(36)) fifo_short + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); + + fifo36_to_ll8 f36_to_ll8 + (.clk(clk), .reset(reset), .clear(clear), + .f36_data(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), + .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n), + .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy)); + + packet_verifier pkt_ver + (.clk(clk), .reset(reset), .clear(clear), + .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n), + .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet_verifier32 diff --git a/fpga/usrp2/control_lib/nsgpio16LE.v b/fpga/usrp2/control_lib/nsgpio16LE.v new file mode 100644 index 000000000..8aef0c7ae --- /dev/null +++ b/fpga/usrp2/control_lib/nsgpio16LE.v @@ -0,0 +1,123 @@ +// Modified from code originally by Richard Herveille, his copyright is below + +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores Simple General Purpose IO core //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +module nsgpio16LE + (input clk_i, input rst_i, + input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [15:0] dat_i, + output reg [15:0] dat_o, output reg ack_o, + input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, + inout [31:0] gpio + ); + + reg [31:0] ctrl, line, ddr, dbg, lgpio; + + wire wb_acc = cyc_i & stb_i; // WISHBONE access + wire wb_wr = wb_acc & we_i; // WISHBONE write access + + always @(posedge clk_i or posedge rst_i) + if (rst_i) + begin + ctrl <= 32'h0; + line <= 32'h0; + ddr <= 32'h0; + dbg <= 32'h0; + end + else if (wb_wr) + case( adr_i[3:1] ) + 3'b000 : + line[15:0] <= dat_i; + 3'b001 : + line[31:16] <= dat_i; + 3'b010 : + ddr[15:0] <= dat_i; + 3'b011 : + ddr[31:16] <= dat_i; + 3'b100 : + ctrl[15:0] <= dat_i; + 3'b101 : + ctrl[31:16] <= dat_i; + 3'b110 : + dbg[15:0] <= dat_i; + 3'b111 : + dbg[31:16] <= dat_i; + endcase // case ( adr_i[3:1] ) + + always @(posedge clk_i) + case (adr_i[3:1]) + 3'b000 : + dat_o <= lgpio[15:0]; + 3'b001 : + dat_o <= lgpio[31:16]; + 3'b010 : + dat_o <= ddr[15:0]; + 3'b011 : + dat_o <= ddr[31:16]; + 3'b100 : + dat_o <= ctrl[15:0]; + 3'b101 : + dat_o <= ctrl[31:16]; + 3'b110 : + dat_o <= dbg[15:0]; + 3'b111 : + dat_o <= dbg[31:16]; + endcase // case (adr_i[3:1]) + + + always @(posedge clk_i or posedge rst_i) + if (rst_i) + ack_o <= 1'b0; + else + ack_o <= wb_acc & !ack_o; + + // latch GPIO input pins + always @(posedge clk_i) + lgpio <= gpio; + + // assign GPIO outputs + integer n; + reg [31:0] igpio; // temporary internal signal + + always @(ctrl or line or debug_1 or debug_0 or atr or ddr or dbg) + for(n=0;n<32;n=n+1) + igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : + (ctrl[n] ? atr[n] : line[n]) ) + : 1'bz; + + assign gpio = igpio; + +endmodule + diff --git a/fpga/usrp2/control_lib/quad_uart.v b/fpga/usrp2/control_lib/quad_uart.v new file mode 100644 index 000000000..afa6fae1d --- /dev/null +++ b/fpga/usrp2/control_lib/quad_uart.v @@ -0,0 +1,71 @@ + +module quad_uart + #(parameter TXDEPTH = 1, + parameter RXDEPTH = 1) + (input clk_i, input rst_i, + input we_i, input stb_i, input cyc_i, output reg ack_o, + input [4:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o, + output [3:0] rx_int_o, output [3:0] tx_int_o, + output [3:0] tx_o, input [3:0] rx_i, output [3:0] baud_o + ); + + // Register Map + localparam SUART_CLKDIV = 0; + localparam SUART_TXLEVEL = 1; + localparam SUART_RXLEVEL = 2; + localparam SUART_TXCHAR = 3; + localparam SUART_RXCHAR = 4; + + wire wb_acc = cyc_i & stb_i; // WISHBONE access + wire wb_wr = wb_acc & we_i; // WISHBONE write access + + reg [15:0] clkdiv[0:3]; + wire [7:0] rx_char[0:3]; + wire [3:0] tx_fifo_full, rx_fifo_empty; + wire [7:0] tx_fifo_level[0:3], rx_fifo_level[0:3]; + + always @(posedge clk_i) + if (rst_i) + ack_o <= 1'b0; + else + ack_o <= wb_acc & ~ack_o; + + integer i; + always @(posedge clk_i) + if (rst_i) + for(i=0;i<4;i=i+1) + clkdiv[i] <= 0; + else if (wb_wr) + case(adr_i[2:0]) + SUART_CLKDIV : clkdiv[adr_i[4:3]] <= dat_i[15:0]; + endcase // case(adr_i) + + always @(posedge clk_i) + case (adr_i[2:0]) + SUART_TXLEVEL : dat_o <= tx_fifo_level[adr_i[4:3]]; + SUART_RXLEVEL : dat_o <= rx_fifo_level[adr_i[4:3]]; + SUART_RXCHAR : dat_o <= rx_char[adr_i[4:3]]; + endcase // case(adr_i) + + genvar j; + generate + for(j=0;j<4;j=j+1) + begin : gen_uarts + simple_uart_tx #(.DEPTH(TXDEPTH)) simple_uart_tx + (.clk(clk_i),.rst(rst_i), + .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i[2:0] == SUART_TXCHAR) && (adr_i[4:3]==j)), + .fifo_level(tx_fifo_level[j]),.fifo_full(tx_fifo_full[j]), + .clkdiv(clkdiv[j]),.baudclk(baud_o[j]),.tx(tx_o[j])); + + simple_uart_rx #(.DEPTH(RXDEPTH)) simple_uart_rx + (.clk(clk_i),.rst(rst_i), + .fifo_out(rx_char[j]),.fifo_read(ack_o && ~wb_wr && (adr_i[2:0] == SUART_RXCHAR) && (adr_i[4:3]==j)), + .fifo_level(rx_fifo_level[j]),.fifo_empty(rx_fifo_empty[j]), + .clkdiv(clkdiv[j]),.rx(rx_i[j])); + end // block: gen_uarts + endgenerate + + assign tx_int_o = ~tx_fifo_full; // Interrupt for those that have space + assign rx_int_o = ~rx_fifo_empty; // Interrupt for those that have data + +endmodule // quad_uart diff --git a/fpga/usrp2/control_lib/ram_2port_mixed_width.v b/fpga/usrp2/control_lib/ram_2port_mixed_width.v new file mode 100644 index 000000000..fae7d8de3 --- /dev/null +++ b/fpga/usrp2/control_lib/ram_2port_mixed_width.v @@ -0,0 +1,120 @@ + +module ram_2port_mixed_width + (input clk16, + input en16, + input we16, + input [10:0] addr16, + input [15:0] di16, + output [15:0] do16, + input clk32, + input en32, + input we32, + input [9:0] addr32, + input [31:0] di32, + output [31:0] do32); + + wire en32a = en32 & ~addr32[9]; + wire en32b = en32 & addr32[9]; + wire en16a = en16 & ~addr16[10]; + wire en16b = en16 & addr16[10]; + + wire [31:0] do32a, do32b; + wire [15:0] do16a, do16b; + + assign do32 = addr32[9] ? do32b : do32a; + assign do16 = addr16[10] ? do16b : do16a; + + RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000), + .INIT_B(18'h00000), + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(18'h00000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE + ) + RAMB16BWE_S36_S18_0 (.DOA(do32a), // Port A 32-bit Data Output + .DOB(do16a), // Port B 16-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .DOPB(), // Port B 2-bit Parity Output + .ADDRA(addr32[8:0]), // Port A 9-bit Address Input + .ADDRB(addr16[9:0]), // Port B 10-bit Address Input + .CLKA(clk32), // Port A 1-bit Clock + .CLKB(clk16), // Port B 1-bit Clock + .DIA(di32), // Port A 32-bit Data Input + .DIB(di16), // Port B 16-bit Data Input + .DIPA(0), // Port A 4-bit parity Input + .DIPB(0), // Port-B 2-bit parity Input + .ENA(en32a), // Port A 1-bit RAM Enable Input + .ENB(en16a), // Port B 1-bit RAM Enable Input + .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input + .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input + .WEA({4{we32}}), // Port A 4-bit Write Enable Input + .WEB({2{we16}}) // Port B 2-bit Write Enable Input + ); + + RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000), + .INIT_B(18'h00000), + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(18'h00000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE + ) + RAMB16BWE_S36_S18_1 (.DOA(do32b), // Port A 32-bit Data Output + .DOB(do16b), // Port B 16-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .DOPB(), // Port B 2-bit Parity Output + .ADDRA(addr32[8:0]), // Port A 9-bit Address Input + .ADDRB(addr16[9:0]), // Port B 10-bit Address Input + .CLKA(clk32), // Port A 1-bit Clock + .CLKB(clk16), // Port B 1-bit Clock + .DIA(di32), // Port A 32-bit Data Input + .DIB(di16), // Port B 16-bit Data Input + .DIPA(0), // Port A 4-bit parity Input + .DIPB(0), // Port-B 2-bit parity Input + .ENA(en32b), // Port A 1-bit RAM Enable Input + .ENB(en16b), // Port B 1-bit RAM Enable Input + .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input + .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input + .WEA({4{we32}}), // Port A 4-bit Write Enable Input + .WEB({2{we16}}) // Port B 2-bit Write Enable Input + ); + +endmodule // ram_2port_mixed_width + + + + +// ISE 10.1.03 chokes on the following + +/* + + reg [31:0] ram [(1<<AWIDTH)-1:0]; + integer i; + initial + for(i=0;i<512;i=i+1) + ram[i] <= 32'b0; + + always @(posedge clk16) + if (en16) + begin + if (we16) + if(addr16[0]) + ram[addr16[10:1]][15:0] <= di16; + else + ram[addr16[10:1]][31:16] <= di16; + do16 <= addr16[0] ? ram[addr16[10:1]][15:0] : ram[addr16[10:1]][31:16]; + end + + always @(posedge clk32) + if (en32) + begin + if (we32) + ram[addr32] <= di32; + do32 <= ram[addr32]; + end + +endmodule // ram_2port_mixed_width + + + */ diff --git a/fpga/usrp2/control_lib/ram_harvard2.v b/fpga/usrp2/control_lib/ram_harvard2.v new file mode 100644 index 000000000..67777af2a --- /dev/null +++ b/fpga/usrp2/control_lib/ram_harvard2.v @@ -0,0 +1,77 @@ + + +// Dual ported, Harvard architecture + +module ram_harvard2 + #(parameter AWIDTH=15, + parameter RAM_SIZE=32768) + (input wb_clk_i, + input wb_rst_i, + // Instruction fetch port. + input [AWIDTH-1:0] if_adr, + output reg [31:0] if_data, + // Data access port. + input [AWIDTH-1:0] dwb_adr_i, + input [31:0] dwb_dat_i, + output reg [31:0] dwb_dat_o, + input dwb_we_i, + output dwb_ack_o, + input dwb_stb_i, + input [3:0] dwb_sel_i); + + reg ack_d1; + reg stb_d1; + + assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1)); + + always @(posedge wb_clk_i) + if(wb_rst_i) + ack_d1 <= 1'b0; + else + ack_d1 <= dwb_ack_o; + + always @(posedge wb_clk_i) + if(wb_rst_i) + stb_d1 <= 0; + else + stb_d1 <= dwb_stb_i; + + reg [7:0] ram0 [0:(RAM_SIZE/4)-1]; + reg [7:0] ram1 [0:(RAM_SIZE/4)-1]; + reg [7:0] ram2 [0:(RAM_SIZE/4)-1]; + reg [7:0] ram3 [0:(RAM_SIZE/4)-1]; + + // Port 1, Read only + always @(posedge wb_clk_i) + if_data[31:24] <= ram3[if_adr[AWIDTH-1:2]]; + always @(posedge wb_clk_i) + if_data[23:16] <= ram2[if_adr[AWIDTH-1:2]]; + always @(posedge wb_clk_i) + if_data[15:8] <= ram1[if_adr[AWIDTH-1:2]]; + always @(posedge wb_clk_i) + if_data[7:0] <= ram0[if_adr[AWIDTH-1:2]]; + + // Port 2, R/W + always @(posedge wb_clk_i) + if(dwb_stb_i) dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]]; + always @(posedge wb_clk_i) + if(dwb_stb_i) dwb_dat_o[23:16] <= ram2[dwb_adr_i[AWIDTH-1:2]]; + always @(posedge wb_clk_i) + if(dwb_stb_i) dwb_dat_o[15:8] <= ram1[dwb_adr_i[AWIDTH-1:2]]; + always @(posedge wb_clk_i) + if(dwb_stb_i) dwb_dat_o[7:0] <= ram0[dwb_adr_i[AWIDTH-1:2]]; + + always @(posedge wb_clk_i) + if(dwb_we_i & dwb_stb_i & dwb_sel_i[3]) + ram3[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[31:24]; + always @(posedge wb_clk_i) + if(dwb_we_i & dwb_stb_i & dwb_sel_i[2]) + ram2[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[23:16]; + always @(posedge wb_clk_i) + if(dwb_we_i & dwb_stb_i & dwb_sel_i[1]) + ram1[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[15:8]; + always @(posedge wb_clk_i) + if(dwb_we_i & dwb_stb_i & dwb_sel_i[0]) + ram0[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[7:0]; + +endmodule // ram_harvard diff --git a/fpga/usrp2/control_lib/s3a_icap_wb.v b/fpga/usrp2/control_lib/s3a_icap_wb.v new file mode 100644 index 000000000..83d9f775e --- /dev/null +++ b/fpga/usrp2/control_lib/s3a_icap_wb.v @@ -0,0 +1,59 @@ + + +module s3a_icap_wb + (input clk, input reset, + input cyc_i, input stb_i, input we_i, output ack_o, + input [31:0] dat_i, output [31:0] dat_o);//, output [31:0] debug_out); + + assign dat_o[31:8] = 24'd0; + + wire BUSY, CE, WRITE, ICAPCLK; + + //changed this to gray-ish code to prevent glitching + reg [2:0] icap_state; + localparam ICAP_IDLE = 0; + localparam ICAP_WR0 = 1; + localparam ICAP_WR1 = 5; + localparam ICAP_RD0 = 2; + localparam ICAP_RD1 = 3; + + always @(posedge clk) + if(reset) + icap_state <= ICAP_IDLE; + else + case(icap_state) + ICAP_IDLE : + begin + if(stb_i & cyc_i) + if(we_i) + icap_state <= ICAP_WR0; + else + icap_state <= ICAP_RD0; + end + ICAP_WR0 : + icap_state <= ICAP_WR1; + ICAP_WR1 : + icap_state <= ICAP_IDLE; + ICAP_RD0 : + icap_state <= ICAP_RD1; + ICAP_RD1 : + icap_state <= ICAP_IDLE; + endcase // case (icap_state) + + assign WRITE = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1); + assign CE = (icap_state == ICAP_WR0) | (icap_state == ICAP_RD0); + assign ICAPCLK = CE & (~clk); + + assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1); + //assign debug_out = {17'd0, BUSY, dat_i[7:0], ~CE, ICAPCLK, ~WRITE, icap_state}; + + ICAP_SPARTAN3A ICAP_SPARTAN3A_inst + (.BUSY(BUSY), // Busy output + .O(dat_o[7:0]), // 32-bit data output + .CE(~CE), // Clock enable input + .CLK(ICAPCLK), // Clock input + .I(dat_i[7:0]), // 32-bit data input + .WRITE(~WRITE) // Write input + ); + +endmodule // s3a_icap_wb diff --git a/fpga/usrp2/control_lib/settings_bus.v b/fpga/usrp2/control_lib/settings_bus.v index fc960e456..aec179516 100644 --- a/fpga/usrp2/control_lib/settings_bus.v +++ b/fpga/usrp2/control_lib/settings_bus.v @@ -10,7 +10,7 @@ module settings_bus input wb_stb_i, input wb_we_i, output reg wb_ack_o, - output strobe, + output reg strobe, output reg [7:0] addr, output reg [31:0] data); @@ -19,18 +19,18 @@ module settings_bus always @(posedge wb_clk) if(wb_rst) begin - stb_int <= 1'b0; + strobe <= 1'b0; addr <= 8'd0; data <= 32'd0; end - else if(wb_we_i & wb_stb_i) + else if(wb_we_i & wb_stb_i & ~wb_ack_o) begin - stb_int <= 1'b1; + strobe <= 1'b1; addr <= wb_adr_i[9:2]; data <= wb_dat_i; end else - stb_int <= 1'b0; + strobe <= 1'b0; always @(posedge wb_clk) if(wb_rst) @@ -38,11 +38,4 @@ module settings_bus else wb_ack_o <= wb_stb_i & ~wb_ack_o; - always @(posedge wb_clk) - stb_int_d1 <= stb_int; - - //assign strobe = stb_int & ~stb_int_d1; - assign strobe = stb_int & wb_ack_o; - endmodule // settings_bus - diff --git a/fpga/usrp2/control_lib/settings_bus_16LE.v b/fpga/usrp2/control_lib/settings_bus_16LE.v new file mode 100644 index 000000000..76061e9e0 --- /dev/null +++ b/fpga/usrp2/control_lib/settings_bus_16LE.v @@ -0,0 +1,54 @@ + +// Grab settings off the wishbone bus, send them out to settings bus +// 16 bits little endian, but all registers need to be written 32 bits at a time. +// This means that you write the low 16 bits first and then the high 16 bits. +// The setting regs are strobed when the high 16 bits are written + +module settings_bus_16LE + #(parameter AWIDTH=16, RWIDTH=8) + (input wb_clk, + input wb_rst, + input [AWIDTH-1:0] wb_adr_i, + input [15:0] wb_dat_i, + input wb_stb_i, + input wb_we_i, + output reg wb_ack_o, + output strobe, + output reg [7:0] addr, + output reg [31:0] data); + + reg stb_int; + + always @(posedge wb_clk) + if(wb_rst) + begin + stb_int <= 1'b0; + addr <= 8'd0; + data <= 32'd0; + end + else if(wb_we_i & wb_stb_i) + begin + addr <= wb_adr_i[RWIDTH+1:2]; // Zero pad high bits + if(wb_adr_i[1]) + begin + stb_int <= 1'b1; // We now have both halves + data[31:16] <= wb_dat_i; + end + else + begin + stb_int <= 1'b0; // Don't strobe, we need other half + data[15:0] <= wb_dat_i; + end + end + else + stb_int <= 1'b0; + + always @(posedge wb_clk) + if(wb_rst) + wb_ack_o <= 0; + else + wb_ack_o <= wb_stb_i & ~wb_ack_o; + + assign strobe = stb_int & wb_ack_o; + +endmodule // settings_bus_16LE diff --git a/fpga/usrp2/control_lib/simple_uart.v b/fpga/usrp2/control_lib/simple_uart.v index 22f0e70a2..0dd58b5f5 100644 --- a/fpga/usrp2/control_lib/simple_uart.v +++ b/fpga/usrp2/control_lib/simple_uart.v @@ -1,11 +1,12 @@ module simple_uart #(parameter TXDEPTH = 1, - parameter RXDEPTH = 1) - (input clk_i, input rst_i, - input we_i, input stb_i, input cyc_i, output reg ack_o, - input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o, - output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o); + parameter RXDEPTH = 1, + parameter CLKDIV_DEFAULT = 16'd0) + (input clk_i, input rst_i, + input we_i, input stb_i, input cyc_i, output reg ack_o, + input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o, + output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o); // Register Map localparam SUART_CLKDIV = 0; @@ -30,7 +31,7 @@ module simple_uart always @(posedge clk_i) if (rst_i) - clkdiv <= 0; + clkdiv <= CLKDIV_DEFAULT; else if (wb_wr) case(adr_i) SUART_CLKDIV : clkdiv <= dat_i[15:0]; diff --git a/fpga/usrp2/control_lib/v5icap_wb.v b/fpga/usrp2/control_lib/v5icap_wb.v new file mode 100644 index 000000000..c8800285a --- /dev/null +++ b/fpga/usrp2/control_lib/v5icap_wb.v @@ -0,0 +1,54 @@ + + +module v5icap_wb + (input clk, input reset, + input cyc_i, input stb_i, input we_i, output ack_o, + input [31:0] dat_i, output [31:0] dat_o); + + wire BUSY, CE, WRITE; + + reg [2:0] icap_state; + localparam ICAP_IDLE = 0; + localparam ICAP_WR0 = 1; + localparam ICAP_WR1 = 2; + localparam ICAP_RD0 = 3; + localparam ICAP_RD1 = 4; + + always @(posedge clk) + if(reset) + icap_state <= ICAP_IDLE; + else + case(icap_state) + ICAP_IDLE : + begin + if(stb_i & cyc_i) + if(we_i) + icap_state <= ICAP_WR0; + else + icap_state <= ICAP_RD0; + end + ICAP_WR0 : + icap_state <= ICAP_WR1; + ICAP_WR1 : + icap_state <= ICAP_IDLE; + ICAP_RD0 : + icap_state <= ICAP_RD1; + ICAP_RD1 : + icap_state <= ICAP_IDLE; + endcase // case (icap_state) + + assign WRITE = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1); + assign CE = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD0); + + assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1); + + ICAP_VIRTEX5 #(.ICAP_WIDTH("X32")) ICAP_VIRTEX5_inst + (.BUSY(BUSY), // Busy output + .O(dat_o), // 32-bit data output + .CE(~CE), // Clock enable input + .CLK(clk), // Clock input + .I(dat_i), // 32-bit data input + .WRITE(~WRITE) // Write input + ); + +endmodule // v5icap_wb diff --git a/fpga/usrp2/coregen/Makefile.srcs b/fpga/usrp2/coregen/Makefile.srcs index a59696d15..a3a5d826d 100644 --- a/fpga/usrp2/coregen/Makefile.srcs +++ b/fpga/usrp2/coregen/Makefile.srcs @@ -16,8 +16,12 @@ fifo_xlnx_16x19_2clk.v \ fifo_xlnx_16x19_2clk.xco \ fifo_xlnx_16x40_2clk.v \ fifo_xlnx_16x40_2clk.xco \ +fifo_xlnx_32x36_2clk.v \ +fifo_xlnx_32x36_2clk.xco \ fifo_xlnx_512x36_2clk_36to18.v \ fifo_xlnx_512x36_2clk_36to18.xco \ fifo_xlnx_512x36_2clk_18to36.v \ fifo_xlnx_512x36_2clk_18to36.xco \ +fifo_xlnx_512x36_2clk_prog_full.v \ +fifo_xlnx_512x36_2clk_prog_full.xco \ )) diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp index 4c9201aff..dd85a7f50 100644 --- a/fpga/usrp2/coregen/coregen.cgp +++ b/fpga/usrp2/coregen/coregen.cgp @@ -1,4 +1,4 @@ -# Date: Mon Jul 26 21:55:33 2010 +# Date: Fri Oct 15 07:50:19 2010 SET addpads = false SET asysymbol = false @@ -13,10 +13,10 @@ SET foundationsym = false SET implementationfiletype = Ngc SET package = fg456 SET removerpms = false -SET simulationfiles = Behavioral +SET simulationfiles = Structural SET speedgrade = -5 SET verilogsim = true SET vhdlsim = false SET workingdirectory = /tmp/ -# CRC: 394da717 +# CRC: 983b9b45 diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise new file mode 100644 index 000000000..70ee54054 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_32x36_2clk.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_32x36_2clk.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc new file mode 100644 index 000000000..d1ed419a7 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$56140<,[o}e~g`n;"2*726&;$9,)<>;.vnt*Ydo&lbjbQwloz\77~4>V8h`f agn3847=7081:?6?!039244=5<288?>?=;249MKVR\3nbb1=::1<20>512F__\XZ5dnww863=87n0?~<?01dd000*=81?86:?FG6811379l1>6D@_UU8svjaXmdzuRzgrdqk81<76;?097GAPTV9twi`Wlg{xtQ{hsgplZgt{lx094?>3781?OIX\^1|ah_dosp|Ys`{oxdR`jg`vf81<768n097GAPTV9twi`Wog`Rzgrdqk81<76;>097GAPTV9twi`Wog`Rzgrdqk[dutm{~787>12596>LHW]]0{~biPftno[qnumzbTbhintd>7>58602?1CXZ_UU8geqgXkfex1:50?3a?0<H]]Z^X7|k_ecweZeh}g~787>11c96>JSSX\^1{Qkauc\gjsi|5>1<3?46595=<053?K?7;ONA394B1=?:=;?75:=159;A=G630805=:491230>?780805;<4A108E44<I;80M><4A7;8EV_IKVXNK>5MU3:8FPUXAGLD=6M=;BG26>EOMJAT@DMJNRG\P\VB:2IB?6MCR89@KHKN\]OO=95LOSG\C@HBZH^BCCQFNGM4?FTBI]OO=6J=;EK0?AVH=2N[^L>:;ERQE43<LYXJ>85KPSC06>C3<2OHM=<4F308BA5<NMI?7KJLE29E@U2<NMZN=6I<;FLG5>O53@:97D?=;H01?L5>3@DBX^ZNTD18MKP53EC97AA9;MMB@@B03EELENOC4:NVP70<D\^9SA:4LTV02>JR\:UG86BZT548HPR3WE?0A^I@N49NQ]E^k2Gjfb|Yesqjkke<E`dd~[k}shmm6>H6<2D:<=:4N0220>H68;>0B<><4:L2412<F8:>86@>0768J460<2D:<5:4N02:7>H69=1E=<>;;O3251=I988?7C?>359M54233G;:995A1047?K76?=1E=<6;;O32=6=I9;>0B<<=3:L276=I9=>0B<:>3:L216=I9?90B<9<;O3;7>H61:1E>==4N330?K45;2D9?>5A2518J7343G8=?6@=729M6=5<F;387C=?3:L056=I;;90B>=<;O177>H4=:1E?;=4N250?K5?;2D85>5A4118J1743G>9?6@;329M015<F=?87C:93:L736=I<180B8<4N618J=443G28?6@7429M<05<F1<87C683:L;<6=I0080B4=4N820?K?6;2D2>>5A9218J<243G3>?6@6629M=25<F0287C76f:LA[GSTX@DT\_A_S69MAQQHZB;0C?5@K09S0>VFZ]k0\D@PBTQJ@]d<X@DTNX]AALG0?UTB92[37_OB17Z2@4=T>2YDY_MJ3:QSK1=SQYO8>6[?/fpe*w`(ojr%oaew/LzlvZtcWyd~Ril_ymq4567W[oxyaz>339V4*aun'xm#jmw.bnh|*Kg{UyhR~ats]dgZ~hz9:;=R\jstnw564<]9%l~k }f.e`|+ekcq%Ftb|Pre]sjqtXojUsc>?03]Qavsk|8997X> gsd-vc)`kq$h`fv Mymq[wbXxg~ySjmPxnp3455XZly~`y?<2:W3+bta&{l$knv!cmi{+H~hzV}yS}`{r^e`[}iu89:;S_k|umv277=R8&myj#|i/fa{*fjlp&GscQxr^rmpwY`kVrd~=>?1^Pfwpjs9:80Y=!hrg,qb*adp'iggu!Bxnp\swYwf}xTknQwos2347YUmzgx<==;T2,cw`)zo%lou lljz,I}iuW~xT|cz}_fa\|jt7899T^h}zlu315>S7'nxm"h gbz-gim'{nT|cz}_ckm858592_;#j|i.sd,cf~)keas#jPpovq[goi4849=6[?/fpe*w`(ojr%oaew/sf\tkruWkce0?0=1:W3+bta&{l$knv!cmi{+wbXxg~ySoga<2<15>S7'nxm"h gbz-gim'{nT|cz}_ckm818582_;#j|i.sd,cf~)keas#jPpovq[goiW98;7X> gsd-vc)`kq$h`fv re]sjqtXj`dT=?>4U1-dvc(un&mht#mcky-q`Zvi|{UiecQ=219V4*aun'xm#jmw.bnh|*tcWyd~Rlfn^114>S7'nxm"h gbz-gim'{nT|cz}_ckm[1413\:$kh!rg-dg}(ddbr$~iQnup\flhXpfx;<=>=7:W3+bta&{l$knv!cmi{+wbXxg~ySoga_ymq45679;<0Y=!hrg,qb*adp'iggu!}d^rmpwYeagUsc>?0004?P6(o{l%~k!hcy,`hn~(zmU{by|Pbhl\|jt789;:>;5Z0.eqb+ta'nis"nbdx.pg[uhszVhbbRv`r123671<]9%l~k }f.e`|+ekcq%yhR~ats]amkYg{:;<??=6:W3+bta&{l$knv!cmi{+wbXxg~ySoga_ymq4564:h1^<"i}f/pe+be&jf`t"|k_qlwvZdnfVrd~=>?3^QT476<]9%l~k }f.e`|+ekcq%yhR~ats]dg969:91^<"i}f/pe+be&jf`t"|k_qlwvZad4849<6[?/fpe*w`(ojr%oaew/sf\tkruWni7>3<?;T2,cw`)zo%lou lljz,vaYwf}xTkn2<>328Q5)`zo$yj"ilx/aoo})ulVzexQhc=6=5c=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[57a3\:$kh!rg-dg}(ddbr$~iQnup\cfY69o1^<"i}f/pe+be&jf`t"|k_qlwvZadW;;m7X> gsd-vc)`kq$h`fv re]sjqtXojU8=k5Z0.eqb+ta'nis"nbdx.pg[uhszVmhS9<9;T2,cw`)zo%lou lljz,vaYwf}xTknQnssgd8585>2_;#j|i.sd,cf~)keas#jPpovq[beXizxnk1?1279V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqab:56;<0Y=!hrg,qb*adp'iggu!}d^rmpwY`kVkx~hi33?05?P6(o{l%~k!hcy,`hn~(zmU{by|Pgb]bwwc`4=4996[?/fpe*w`(ojr%oaew/sf\tkruWniTm~|jg^211>S7'nxm"h gbz-gim'{nT|cz}_fa\evtboV;996[?/fpe*w`(ojr%oaew/sf\tkruWniTm~|jg^011>S7'nxm"h gbz-gim'{nT|cz}_fa\evtboV9996[?/fpe*w`(ojr%oaew/sf\tkruWniTm~|jg^61=>S7'nxm"h gbz-gim'{nT|cz}_fa\evtboVn:0=0=9:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfcZb6484956[?/fpe*w`(ojr%oaew/sf\tkruWniTm~|jg^f2878512_;#j|i.sd,cf~)keas#jPpovq[beXizxnkRj><2<1=>S7'nxm"h gbz-gim'{nT|cz}_fa\evtboVn:090=8:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfcZb6W9837X> gsd-vc)`kq$h`fv re]sjqtXojUjkh_e3\57><]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmTh<Q=299V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabYc9V9946[?/fpe*w`(ojr%oaew/sf\tkruWniTm~|jg^f2[1423\:$kh!rg-dg}(ddbr$~iQnup\cfYg{:;<=<:;T2,cw`)zo%lou lljz,vaYwf}xTknQwos2344423\:$kh!rg-dg}(ddbr$~iQnup\cfYg{:;<?<:;T2,cw`)zo%lou lljz,vaYwf}xTknQwos2346463\:$kh!rg-dg}(ddbr${Qnup\flh;878:7X> gsd-vc)`kq$h`fv ws]sjqtXj`d7=3<>;T2,cw`)zo%lou lljz,swYwf}xTnd`32?02?P6(o{l%~k!hcy,`hn~({U{by|Pbhl?7;463\:$kh!rg-dg}(ddbr${Qnup\flh;<78;7X> gsd-vc)`kq$h`fv ws]sjqtXj`dT<?>4U1-dvc(un&mht#mcky-tvZvi|{UiecQ>219V4*aun'xm#jmw.bnh|*quWyd~Rlfn^014>S7'nxm"h gbz-gim'~xT|cz}_ckm[6473\:$kh!rg-dg}(ddbr${Qnup\flhX<;<0Y=!hrg,qb*adp'iggu!xr^rmpwYeagUsc>?0104?P6(o{l%~k!hcy,`hn~({U{by|Pbhl\|jt789::>;5Z0.eqb+ta'nis"nbdx.uq[uhszVhbbRv`r123571<]9%l~k }f.e`|+ekcq%|~R~ats]amkYg{:;<<?=6:W3+bta&{l$knv!cmi{+rtXxg~ySoga_ymq4565:>1^<"i}f/pe+be&jf`t"y}_qlwvZdnfVrd~=>?2005?P6(o{l%~k!hcy,`hn~({U{by|Pbhl\|jt78999m6[?/fpe*w`(ojr%oaew/vp\tkruWkceSua}0120[VQ7:91^<"i}f/pe+be&jf`t"y}_qlwvZad4949<6[?/fpe*w`(ojr%oaew/vp\tkruWni7=3<?;T2,cw`)zo%lou lljz,swYwf}xTkn2=>328Q5)`zo$yj"ilx/aoo})pzVzexQhc=1=65=R8&myj#|i/fa{*fjlp&}yS}`{r^e`8186n2_;#j|i.sd,cf~)keas#z|Ppovq[beX88l0Y=!hrg,qb*adp'iggu!xr^rmpwY`kV;:j6[?/fpe*w`(ojr%oaew/vp\tkruWniT><h4U1-dvc(un&mht#mcky-tvZvi|{UloR=>f:W3+bta&{l$knv!cmi{+rtXxg~ySjmP4348Q5)`zo$yj"ilx/aoo})pzVzexQhc^cpv`a;878=7X> gsd-vc)`kq$h`fv ws]sjqtXojUjkh<0<12>S7'nxm"h gbz-gim'~xT|cz}_fa\evtbo585>;5Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef>0:70<]9%l~k }f.e`|+ekcq%|~R~ats]dgZgtzlm783<:;T2,cw`)zo%lou lljz,swYwf}xTknQnssgd[5423\:$kh!rg-dg}(ddbr${Qnup\cfYf{{olS<<:;T2,cw`)zo%lou lljz,swYwf}xTknQnssgd[7423\:$kh!rg-dg}(ddbr${Qnup\cfYf{{olS><:;T2,cw`)zo%lou lljz,swYwf}xTknQnssgd[14>3\:$kh!rg-dg}(ddbr${Qnup\cfYf{{olSi?30?0:?P6(o{l%~k!hcy,`hn~({U{by|Pgb]bwwc`Wm;7=3<6;T2,cw`)zo%lou lljz,swYwf}xTknQnssgd[a7;:7827X> gsd-vc)`kq$h`fv ws]sjqtXojUjkh_e3?7;4>3\:$kh!rg-dg}(ddbr${Qnup\cfYf{{olSi?34?0;?P6(o{l%~k!hcy,`hn~({U{by|Pgb]bwwc`Wm;T<?64U1-dvc(un&mht#mcky-tvZvi|{UloRo|rde\`4Y6:11^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQk1^01<>S7'nxm"h gbz-gim'~xT|cz}_fa\evtboVn:S><7;T2,cw`)zo%lou lljz,swYwf}xTknQnssgd[a7X<;?0Y=!hrg,qb*adp'iggu!xr^rmpwY`kVrd~=>?0378Q5)`zo$yj"ilx/aoo})pzVzexQhc^zlv5679;?0Y=!hrg,qb*adp'iggu!xr^rmpwY`kVrd~=>?2378Q5)`zo$yj"ilx/aoo})pzVzexQhc^zlv567;::0Y=!hrg,qb*ak8'xo#j|>.sdtbq)Je|rT^LCPRE]FJZ@PN]8:??5Z0.eqb+ta'nf;"j gs3-vcqa|&GfyuQ]AL]Q@ZCIWO]MX??P13d8Q5)`zo$yj"ic0/pg+bt6&{l|jy!Bmtz\VDKXZLMDYYQJN031`>S7'nxm"h gm2-va)`z8$yjzh{/bwqvZ`pn}Uxxlzj<1<1`>S7'nxm"h gm2-va)`z8$yjzh{/bwqvZ`pn}Uxxlzj<0<1g>S7'nxm"h gm2-va)`z8$yjzh{/bwqvZ`pn}Uxxlzj_10`?P6(o{l%~k!hl1,q`*au9'xm{kz ctpq[cqa|VymykP1278Q5)`zo$yj"ic0/pg+bt6&{l|jy!lusp\br`sWz~jxhQbuy2344:76:<0Y=!hrg,qb*ak8'xo#j|>.sdtbq)d}{xTjzh{_rvbp`Yj}q:;<<2?>016?P6(o{l%~k!hl1,q`*au9'xm{kz ctpq[cqa|VymykPmtz3457;979=7X> gsd-vc)`d9$yh"i}1/pescr(k|xySkyit^qweqcXe|r;<=?31?31<>S7'nxm"h gm2-va)`z8$yjzh{/dosp|Yao~Tjo<8;T2,cw`)zo%l`= }d.eq5+tao~$i`~{y^dtbqYn:o1^<"i}f/pe+bj7&{n$k?!rguep*cjx}sTjzh{_h]nq}67899;7X> gsd-vc)`d9$yh"i}1/pescr(mdzuRhxfu]j[hs89:;=?74U1-dvc(un&mg<#|k/fpbw+tt|z%ym`Qjmqvz[cdXa::0Y=!hrg,qb*ak8'xo#j|ns/pppv)uidUna}zv_g`\mZiu89:;?>5Z0.eqb+ta'nf;"j gscp*wus{&xjaRkbpu{\bgYnWfx;<=>>1410?P6(o{l%~k!hl1,q`*auiz$yy} r`o\ahvsqVliSdQ`r1234431;:1^<"i}f/pe+bj7&{n$ko|.sqww*tfeVof|ywPfc]j[jt789::95=<;T2,cw`)zo%l`= }d.eqev(u{}y$~lcPelrw}Z`eW`Ud~=>?00:077=R8&myj#|i/fn3*wb(o{kx"}{s.pbiZcjx}sTjoQf_np34565>:80Y=!hrg,qb*ak8'xo#j|ns/pppv)uidUna}zv_g`\mZiu89:;:?==;T2,cw`)zo%l`= }d.eqev(u{}y$~lcPelrw}Z`eW`Ud~=>?07117>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|;>0Y=!hrg,qb*ak8'xo#~ats-Ngjsi|Vidycz>259V4*aun'xm#jb?.sf,vuhsz&Ghcx`{_bmvjq45<2_;#j|i.sd,ci6)zm%y|cz}/LalqkrXkfex><;;T2,cw`)zo%l`= }d.psjqt(Eje~byQlotlw064<]9%l~k }f.eo4+tc'{zex!BcnwmpZeh}g~Ttb|30?32[LHQW98h7X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{_ymq84869;i0Y=!hrg,qb*ak8'xo#~ats-Ngjsi|VidyczPxnp?6;76:m1^<"i}f/pe+bj7&{n$~}`{r.O`kphsWje~byQwos>0:476:j1^<"i}f/pe+bj7&{n$~}`{r.O`kphsWje~byQwos>0:445k2_;#j|i.sd,ci6)zm%y|cz}/LalqkrXkfexRv`r=6=547f3\:$kh!rg-dh5(ul&x{by| N032b>S7'nxm"h gm2-va)uxg~y#naznu>3:4`<]9%l~k }f.eo4+tc'{zex!lotlw8486n2_;#j|i.sd,ci6)zm%y|cz}/bmvjq:568l0Y=!hrg,qb*ak8'xo#~ats-`kphs4:4:j6[?/fpe*w`(oe:%~i!}povq+firf}6?2<k4U1-dvc(un&mg<#|k/srmpw)dg|dS=?j;T2,cw`)zo%l`= }d.psjqt(kfexR?>e:W3+bta&{l$ka>!re-qtkru'je~byQ=1d9V4*aun'xm#jb?.sf,vuhsz&idyczP30g8Q5)`zo$yj"ic0/pg+wvi|{%hcx`{_501?P6(o{l%~k!hl1,q`*twf}x$ob{at^f28585:2_;#j|i.sd,ci6)zm%y|cz}/bmvjqYc95;5>?5Z0.eqb+ta'nf;"j rqlwv*eh}g~Th<2=>308Q5)`zo$yj"ic0/pg+wvi|{%hcx`{_e3?7;453\:$kh!rg-dh5(ul&x{by| cnwmpZb64=49=6[?/fpe*w`(oe:%~i!}povq+firf}Uo=R>=1:W3+bta&{l$ka>!re-qtkru'je~byQk1^315>S7'nxm"h gm2-va)uxg~y#naznu]g5Z4592_;#j|i.sd,ci6)zm%y|cz}/bmvjqYc9V99=6[?/fpe*w`(oe:%~i!}povq+firf}Uo=R:=4:W3+bta&{l$ka>!re-qtkru'je~byQaou23445a3\:$kh!rg-dh5(pz&m|m~ hpg,tvu`(EhnoSigif^rmpwYwimUjhi>?01]`}969;o1^<"i}f/pe+bj7&~x$kzo|.fre*rtwn&GjhiQkigd\tkruWykoSljk0123[f;979m7X> gsd-vc)`d9$|~"ixar,dtc(pzyl$Aljk_ekebZvi|{U{miQnde2345Ydq585?k5Z0.eqb+ta'nf;"z| gvcp*bva&~x{j"Cnde]gmc`Xxg~yS}ok_`fg4567Wjs7?3=i;T2,cw`)zo%l`= xr.etev(`xo$|~}h M`fg[aoanVzexQae]b`a6789Uhu1:1419V4*aun'xm#jb?.vp,crgt&nzm"z|f.Ob`aYcaolT|cz}_qcg[dbc89:;Sa{{<0<74>S7'nxm"h gm2-sw)`hy%k}h!wsre+HgclVnbjkQnup\tdbXimn;<=>Pltv?6;273\:$kh!rg-dh5(pz&m|m~ hpg,tvu`(EhnoSigif^rmpwYwimUjhi>?01]oqq:46=:0Y=!hrg,qb*ak8'}y#jyns/esb+quxo%FmijPdhde[uhszVzjhRokd1234Zjr|5>58=5Z0.eqb+ta'nf;"z| gvcp*bva&~x{j"Cnde]gmc`Xxg~yS}ok_`fg4567We080;0:W3+bta&{l$ka>!ws-dsdu)oyl%{~i/Lcg`ZbnnoU{by|Pp`f\eab789:Ttb|34?63?P6(o{l%~k!hl1,tv*apiz$l|k xrqd,IdbcWmcmjR~ats]seaYflm:;<=Qwos>6:7`<]9%l~k }f.eo4+qu'n}j#if/uqtc)caolT|cz}_qcg8185n2_;#j|i.sd,ci6){%l{l}!gqd-swva'mcmjR~ats]sea:26;o0Y=!hrg,qb*ak8'}y#jyns/esb+quxo%oekhPpovq[ugcW=8n7X> gsd-vc)`d9$|~"ixar,dtc(pzyl$hdhi_qlwvZvflV?8;6[?/fpe*w`(oe:%{!hw`q-cu`){zm#igif^rmpwYwimUjhi>?01>7:61<]9%l~k }f.eo4+qu'n}j#if/uqtc)caolT|cz}_qcg[dbc89:;080=a:W3+bta&{l$ka>!ws-dsdu)oyl%{~i/qplcZ`rdeUb??5Z0.eqb+ta'nf;"z| gvcp*bva&~x{j"~}of]eqijXaVg~t=>?3218Q5)`zo$yj"ic0/uq+bqf{'m{j#y}pg-svjaXn|fgSdQbuy234674:2_;#j|i.sd,ci6){%l{l}!gqd-swva'yxdkRhzlm]j[kis89::>;5Z0.eqb+ta'nf;"z| gvcp*rus{&i9#iazt^k1270<]9%l~k }f.eo4+qu'n}j#y|tr-`6*bh}}Ub:?<9;T2,cw`)zo%l`= xr.etev(p{}y$o?!kotv\m2>582_;#j|i.sd,ci6){%l{l}!wrvp+fijx;8h7X> gsd-vc)`d9$|~"ixar,twqu(zhgTmac`su]eqijXa:>0Y=!hrg,qb*ak8'}y#jyns/uppv)uidUj``a|t^dvhiYnWds<=>?369V4*aun'xm#jb?.vp,crgt&~y"|nm^coijusWog`RgPmtz345668>9=7X> gsd-vc)`d9$|~"ixar,twqu(zhgTmac`su]eqijXaVg~t=>?03402>S7'nxm"h gm2-sw)`hy%{~z|/scn[djjgz~Tjxbc_h]nq}6789<<?;5Z0.eqb+ta'nf;"z| gvcp*rus{&xjaRocmnqw[cskdVcTaxv?0125=63<]9%l~k }f.eo4+qu'n}j#y|tr-qehYfddexxRhzlm]j[kis89::=?64U1-dvc(un&mg<#y}/fubw+qt|z%ym`Qiumn\bgYn:<1^<"i}f/pe+bj7&~x$kzo|.vqww*tfeVl~`aQf2e9V4*aun'xm#jb?.vp,crgt&~y"|nm^dvhiYnWds<=>?319V4*aun'xm#jb?.vp,crgt&~y"|nm^dvhiYnWds<=>?1171b>S7'nxm"h gm2-sw)`hy%{~z|/scn[cskdVcTaxv?012137`<]9%l~k }f.eo4+qu'n}j#y|tr-qehYa}efTeRczx1234355n2_;#j|i.sd,ci6){%l{l}!wrvp+wgjWog`RgPmtz3456018n0Y=!hrg,qb*ak8'}y#ob_vp\akYn98l0Y=!hrg,qb*ak8'}y#ob_vp\akYn9V;9?6[?/fpe*w`(oe:%{!xpovq+Heh}g~Tob{at368Q5)`zo$yj"ic0/uq+rvi|{%Fob{at^alqkr6:=1^<"i}f/pe+bj7&~x${}`{r.O`kphsWje~by<=4:W3+bta&{l$ka>!ws-ttkru'DidyczPcnwmp6433\:$kh!rg-dh5(pz&}{by| MbmvjqYdg|d8><4U1-dvc(un&mg<#y}/vrmpw)JkfexRm`uov\|jt;87;:SD@Y_10`?P6(o{l%~k!hl1,tv*qwf}x$Anaznu]`kphsWqey0<0>13a8Q5)`zo$yj"ic0/uq+rvi|{%Fob{at^alqkrXpfx7>3?>2e9V4*aun'xm#jb?.vp,suhsz&Ghcx`{_bmvjqYg{682<?>2b9V4*aun'xm#jb?.vp,suhsz&Ghcx`{_bmvjqYg{682<<=c:W3+bta&{l$ka>!ws-ttkru'DidyczPcnwmpZ~hz5>5=<?n;T2,cw`)zo%l`= xr.usjqt(F8;:j6[?/fpe*w`(oe:%{!xpovq+firf}6;2<h4U1-dvc(un&mg<#y}/vrmpw)dg|d0<0>f:W3+bta&{l$ka>!ws-ttkru'je~by2=>0d8Q5)`zo$yj"ic0/uq+rvi|{%hcx`{<2<2b>S7'nxm"h gm2-sw)pxg~y#naznu>7:4c<]9%l~k }f.eo4+qu'~zex!lotlw[57b3\:$kh!rg-dh5(pz&}{by| cnwmpZ76m2_;#j|i.sd,ci6){%||cz}/bmvjqY59l1^<"i}f/pe+bj7&~x${}`{r.alqkrX;8o0Y=!hrg,qb*ak8'}y#z~ats-`kphsW=897X> gsd-vc)`d9$|~"ynup,gjsi|Vn:0=0=2:W3+bta&{l$ka>!ws-ttkru'je~byQk1=3=67=R8&myj#|i/fn3*rt(yd~"m`uov\`4:56;80Y=!hrg,qb*ak8'}y#z~ats-`kphsWm;7?3<=;T2,cw`)zo%l`= xr.usjqt(kfexRj><5<15>S7'nxm"h gm2-sw)pxg~y#naznu]g5Z6592_;#j|i.sd,ci6){%||cz}/bmvjqYc9V;9=6[?/fpe*w`(oe:%{!xpovq+firf}Uo=R<=1:W3+bta&{l$ka>!ws-ttkru'je~byQk1^115>S7'nxm"h gm2-sw)pxg~y#naznu]g5Z25:2_;#j|i.sd,ci6){%||cz}/bmvjqYc:5:5>?5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th?2>>308Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_e0?6;453\:$kh!rg-dh5(pz&}{by| cnwmpZb54:49>6[?/fpe*w`(oe:%{!xpovq+firf}Uo>1:1209V4*aun'xm#jb?.vp,suhsz&idyczPd3]364=R8&myj#|i/fn3*rt(yd~"m`uov\`7Y6:81^<"i}f/pe+bj7&~x${}`{r.alqkrXl;U9><5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th?Q<209V4*aun'xm#jb?.vp,suhsz&idyczPd3]767=R8&myj#|i/fn3*rt(yd~"m`uov\`6:76;80Y=!hrg,qb*ak8'}y#z~ats-`kphsWm97=3<=;T2,cw`)zo%l`= xr.usjqt(kfexRj<<3<16>S7'nxm"h gm2-sw)pxg~y#naznu]g7959:;1^<"i}f/pe+bj7&~x${}`{r.alqkrXl:6?2??4U1-dvc(un&mg<#y}/vrmpw)dg|dSi=P0338Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_e1\577<]9%l~k }f.eo4+qu'~zex!lotlw[a5X:;;0Y=!hrg,qb*ak8'}y#z~ats-`kphsWm9T???4U1-dvc(un&mg<#y}/vrmpw)dg|dSi=P4368Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_omw45669>1^<"i}f/pe+hcj'me~xRg30?3;?P6(o{l%~k!bel-gkprXa5;;2<64U1-dvc(un&gna"j`uu]j8479911^<"i}f/pe+hcj'me~xRg313<2<>S7'nxm"h mdo,`jssW`6:?3?7;T2,cw`)zo%fi`!kotv\m9736820Y=!hrg,qb*kbe&ndyyQf<07=5==R8&myj#|i/lgn+air|Vc7=;0>8:W3+bta&{l$ahc dnww[l:6?7;37X> gsd-vc)jmd%ocxzPi=3;:4><]9%l~k }f.ofi*bh}}Ub0<71169V4*aun'xm#`kb/emvpZo;97;37X> gsd-vc)jmd%ocxzPi=03:4><]9%l~k }f.ofi*bh}}Ub0??1199V4*aun'xm#`kb/emvpZo;:;4:46[?/fpe*w`(elg$hb{{_h>17;7?3\:$kh!rg-nah)cg|~Te1<;>0:8Q5)`zo$yj"cjm.flqqYn4;?5=55Z0.eqb+ta'dof#iazt^k?638602_;#j|i.sd,i`k(lfSd2=7?3;?P6(o{l%~k!bel-gkprXa5832<64U1-dvc(un&gna"j`uu]j87?99>1^<"i}f/pe+hcj'me~xRg32?3;?P6(o{l%~k!bel-gkprXa59;2<64U1-dvc(un&gna"j`uu]j8679911^<"i}f/pe+hcj'me~xRg333<2<>S7'nxm"h mdo,`jssW`68?3?7;T2,cw`)zo%fi`!kotv\m9536820Y=!hrg,qb*kbe&ndyyQf<27=52=R8&myj#|i/lgn+air|Vc7?3?8;T2,cw`)zo%fi`!kotv\m9299>1^<"i}f/pe+hcj'me~xRg35?34?P6(o{l%~k!bel-gkprXa5<5=:5Z0.eqb+ta'dof#iazt^k?3;703\:$kh!rg-nah)cg|~Te161169V4*aun'xm#`kb/emvpZo;17;=7X> gsd-vc)jmd%ocxzPi^222>S7'nxm"h mdo,`jssW`U:=:5Z0.eqb+ta'dof#iazt^k\55703\:$kh!rg-nah)cg|~TeR?>169V4*aun'xm#`kb/emvpZoX9;;<7X> gsd-vc)jmd%ocxzPi^3052=R8&myj#|i/lgn+air|VcT=9?8;T2,cw`)zo%fi`!kotv\mZ729>1^<"i}f/pe+hcj'me~xRgP1734?P6(o{l%~k!bel-gkprXaV;<=:5Z0.eqb+ta'dof#iazt^k\5=703\:$kh!rg-nah)cg|~TeR?6179V4*aun'xm#`kb/emvpZoX:8=0Y=!hrg,qb*kbe&ndyyQf_3223>S7'nxm"h mdo,`jssW`U9=<94U1-dvc(un&gna"j`uu]j[746?2_;#j|i.sd,i`k(lfSdQ=3058Q5)`zo$yj"cjm.flqqYnW;>:;6[?/fpe*w`(elg$hb{{_h]1141<]9%l~k }f.ofi*bh}}UbS?8>7:W3+bta&{l$ahc dnww[lY5?8=0Y=!hrg,qb*kbe&ndyyQf_3:23>S7'nxm"h mdo,`jssW`U95<84U1-dvc(un&gna"j`uu]j[6703\:$kh!rg-nah)cg|~TeR=?169V4*aun'xm#`kb/emvpZoX;8;<7X> gsd-vc)jmd%ocxzPi^1152=R8&myj#|i/lgn+air|VcT?>?8;T2,cw`)zo%fi`!kotv\mZ539>1^<"i}f/pe+hcj'me~xRgP3435?P6(o{l%~k!bel-gkprXaV>::6[?/fpe*w`(elg$hb{{_h]653=R8&myj#|i/lgn+air|VcT:<84U1-dvc(un&gna"j`uu]j[2713\:$kh!rg-nah)cg|~TeR6>6:W3+bta&{l$ahc dnww[lY>9j1^<"i}f/pe+hcj'me~xRgPnnv34576m2_;#j|i.sd,i`k(omg%h`!Br`o\VDK69o1^<"i}f/pe+hcj'nnf"ic Mscn[WGJ99;m7X> gsd-vc)jmd%lh` km.OqehYUID;:=k5Z0.eqb+ta'dof#jjb.eo,IwgjW[KF=??i;T2,cw`)zo%fi`!hdl,gi*KuidUYM@?<1g9V4*aun'xm#`kb/ffn*ak(E{kfS_OB153e?P6(o{l%~k!bel-d`h(ce&Gym`Q]AL365c=R8&myj#|i/lgn+bbj&mg$Aob_SCN537a3\:$kh!rg-nah)`ld$oa"C}al]QEH709o1^<"i}f/pe+hcj'nnf"ic Mscn[WGJ91;m7X> gsd-vc)jmd%lh` km.OqehYUID;2=h5Z0.eqb+ta'dof#jjb.eo,IwgjW[KF><h4U1-dvc(un&gna"ikm/fn+HtfeVXJA?>>f:W3+bta&{l$ahc geo-`h)JzhgT^LC=10d8Q5)`zo$yj"cjm.egi+bj'DxjaR\NM302b>S7'nxm"h mdo,cak)ld%F~lcPR@O174`<]9%l~k }f.ofi*ace'nf#@|nm^PBI726n2_;#j|i.sd,i`k(omg%h`!Br`o\VDK5=8l0Y=!hrg,qb*kbe&moa#jb/LpbiZTFE;<:j6[?/fpe*w`(elg$kic!dl-NvdkXZHG9;<h4U1-dvc(un&gna"ikm/fn+HtfeVXJA?6>f:W3+bta&{l$ahc geo-`h)JzhgT^LC=90g8Q5)`zo$yj"cjm.egi+bj'DxjaR\NM23e?P6(o{l%~k!bel-d`h(ce&Gym`Q]AL135c=R8&myj#|i/lgn+bbj&mg$Aob_SCN747a3\:$kh!rg-nah)`ld$oa"C}al]QEH559o1^<"i}f/pe+hcj'nnf"ic Mscn[WGJ;:;m7X> gsd-vc)jmd%lh` km.OqehYUID9?=k5Z0.eqb+ta'dof#jjb.eo,IwgjW[KF?8?i;T2,cw`)zo%fi`!hdl,gi*KuidUYM@=91g9V4*aun'xm#`kb/ffn*ak(E{kfS_OB363e?P6(o{l%~k!bel-d`h(ce&Gym`Q]AL1;5c=R8&myj#|i/lgn+bbj&mg$Aob_SCN7<7b3\:$kh!rg-nah)`ld$oa"C}al]QEH26n2_;#j|i.sd,i`k(omg%h`!Br`o\VDK388l0Y=!hrg,qb*kbe&moa#jb/LpbiZTFE=;:j6[?/fpe*w`(elg$kic!dl-NvdkXZHG?><h4U1-dvc(un&gna"ikm/fn+HtfeVXJA9=>f:W3+bta&{l$ahc geo-`h)JzhgT^LC;40d8Q5)`zo$yj"cjm.egi+bj'DxjaR\NM572b>S7'nxm"h mdo,cak)ld%F~lcPR@O724`<]9%l~k }f.ofi*ace'nf#@|nm^PBI116n2_;#j|i.sd,i`k(omg%h`!Br`o\VDK308l0Y=!hrg,qb*kbe&moa#jb/LpbiZTFE=3:i6[?/fpe*w`(elg$kic!dl-NvdkXZHG>=k5Z0.eqb+ta'dof#jjb.eo,IwgjW[KF9=?i;T2,cw`)zo%fi`!hdl,gi*KuidUYM@;>1g9V4*aun'xm#`kb/ffn*ak(E{kfS_OB533e?P6(o{l%~k!bel-d`h(ce&Gym`Q]AL705c=R8&myj#|i/lgn+bbj&mg$Aob_SCN117a3\:$kh!rg-nah)`ld$oa"C}al]QEH329o1^<"i}f/pe+hcj'nnf"ic Mscn[WGJ=?;m7X> gsd-vc)jmd%lh` km.OqehYUID?<=k5Z0.eqb+ta'dof#jjb.eo,IwgjW[KF95?i;T2,cw`)zo%fi`!hdl,gi*KuidUYM@;61d9V4*aun'xm#`kb/ffn*ak(E{kfS_OB60d8Q5)`zo$yj"cjm.egi+bj'DxjaR\NM722b>S7'nxm"h mdo,cak)ld%F~lcPR@O554`<]9%l~k }f.ofi*ace'nf#@|nm^PBI346n2_;#j|i.sd,i`k(omg%h`!Br`o\VDK1;8l0Y=!hrg,qb*kbe&moa#jb/LpbiZTFE?>:j6[?/fpe*w`(elg$kic!dl-NvdkXZHG=9<h4U1-dvc(un&gna"ikm/fn+HtfeVXJA;8>f:W3+bta&{l$ahc geo-`h)JzhgT^LC970d8Q5)`zo$yj"cjm.egi+bj'DxjaR\NM7:2b>S7'nxm"h mdo,cak)ld%F~lcPR@O5=4c<]9%l~k }f.ofi*ace'nf#@|nm^PBI27a3\:$kh!rg-nah)`ld$oa"C}al]QEH179o1^<"i}f/pe+hcj'nnf"ic Mscn[WGJ?8;m7X> gsd-vc)jmd%lh` km.OqehYUID=9=h5Z0.eqb+ta'dof#jjb.eo,IwgjW[KF4<k4U1-dvc(un&gna"ikm/fn+HtfeVXJA4?6;T2,cw`)zo%fi`!hdl,gi*H688;27X> gsd-vc)jmd%lh` km.L2467>3\:$kh!rg-nah)`ld$oa"@>043:?P6(o{l%~k!bel-d`h(ce&D:<:?6;T2,cw`)zo%fi`!hdl,gi*H680;37X> gsd-vc)jmd%lh` km.L254?<]9%l~k }f.ofi*ace'nf#C?>10;8Q5)`zo$yj"cjm.egi+bj'G;:?<74U1-dvc(un&gna"ikm/fn+K76=830Y=!hrg,qb*kbe&moa#jb/O3234?<]9%l~k }f.ofi*ace'nf#C?>90;8Q5)`zo$yj"cjm.egi+bj'G;9=<74U1-dvc(un&gna"ikm/fn+K75;830Y=!hrg,qb*kbe&moa#jb/O3114?<]9%l~k }f.ofi*ace'nf#C?=70;8Q5)`zo$yj"cjm.egi+bj'G;95<64U1-dvc(un&gna"ikm/fn+K74901^<"i}f/pe+hcj'nnf"ic N0125<=R8&myj#|i/lgn+bbj&mg$B<=<189V4*aun'xm#`kb/ffn*ak(F89>=45Z0.eqb+ta'dof#jjb.eo,J450901^<"i}f/pe+hcj'nnf"ic N01:5<=R8&myj#|i/lgn+bbj&mg$B<:>189V4*aun'xm#`kb/ffn*ak(F8>8=45Z0.eqb+ta'dof#jjb.eo,J422901^<"i}f/pe+hcj'nnf"ic N0645==R8&myj#|i/lgn+bbj&mg$B<;>8:W3+bta&{l$ahc geo-`h)I9>;37X> gsd-vc)jmd%lh` km.L2=4><]9%l~k }f.ofi*ace'nf#C<>199V4*aun'xm#`kb/ffn*ak(F;9:46[?/fpe*w`(elg$kic!dl-M607?3\:$kh!rg-nah)`ld$oa"@=70:8Q5)`zo$yj"cjm.egi+bj'G82=55Z0.eqb+ta'dof#jjb.eo,J67602_;#j|i.sd,i`k(omg%h`!A323;?P6(o{l%~k!bel-d`h(ce&D89<64U1-dvc(un&gna"ikm/fn+K50911^<"i}f/pe+hcj'nnf"ic N2;2<>S7'nxm"h mdo,cak)ld%E8<?7;T2,cw`)zo%fi`!hdl,gi*H3;820Y=!hrg,qb*kbe&moa#jb/O665==R8&myj#|i/lgn+bbj&mg$B99>8:W3+bta&{l$ahc geo-`h)I<0;<7X> gsd-vc)jmd%lh` km.L65==R8&myj#|i/lgn+bbj&mg$B8?>8:W3+bta&{l$ahc geo-`h)I=:;37X> gsd-vc)jmd%lh` km.L614><]9%l~k }f.ofi*ace'nf#C;8199V4*aun'xm#`kb/ffn*ak(F<3:46[?/fpe*w`(elg$kic!dl-M247?3\:$kh!rg-nah)`ld$oa"@930:8Q5)`zo$yj"cjm.egi+bj'G<>=55Z0.eqb+ta'dof#jjb.eo,J31602_;#j|i.sd,i`k(omg%h`!A6834?P6(o{l%~k!bel-d`h(ce&D<=55Z0.eqb+ta'dof#jjb.eo,J27602_;#j|i.sd,i`k(omg%h`!A723;?P6(o{l%~k!bel-d`h(ce&D<9<64U1-dvc(un&gna"ikm/fn+K10911^<"i}f/pe+hcj'nnf"ic N6;2<>S7'nxm"h mdo,cak)ld%E4<?7;T2,cw`)zo%fi`!hdl,gi*H?;820Y=!hrg,qb*kbe&moa#jb/O:65==R8&myj#|i/lgn+bbj&mg$B59>8:W3+bta&{l$ahc geo-`h)I00;<7X> gsd-vc)jmd%lh` km.L:5==R8&myj#|i/lgn+bbj&mg$B4?>8:W3+bta&{l$ahc geo-`h)I1:;37X> gsd-vc)jmd%lh` km.L:14><]9%l~k }f.ofi*ace'nf#C78199V4*aun'xm#`kb/ffn*ak(F03996[?/fpe*w`(elg$kic!dl-\rdtnfmos<=>?<1<12>S7'nxm"h mdo,cak)ld%Tzl|fneg{456748:5>;5Z0.eqb+ta'dof#jjb.eo,[sguagnnt=>?0=32:70<]9%l~k }f.ofi*ace'nf#Rxnrhlga}67896:>3<9;T2,cw`)zo%fi`!hdl,gi*Yqi{cehhv?012?5685>2_;#j|i.sd,i`k(omg%h`!Pv`pjjac89:;0<:1279V4*aun'xm#`kb/ffn*ak(Wkyecjjx12349726;<0Y=!hrg,qb*kbe&moa#jb/^tbvlhcmq:;<=2>6?05?P6(o{l%~k!bel-d`h(ce&U}mgaddz3456;9>49:6[?/fpe*w`(elg$kic!dl-\rdtnfmos<=>?<0:=63=R8&myj#|i/lgn+bbj&mg$S{o}ioff|56785;22?;4U1-dvc(un&gna"ikm/fn+Zpfz`doiu>?01>2:70<]9%l~k }f.ofi*ace'nf#Rxnrhlga}678969<3<9;T2,cw`)zo%fi`!hdl,gi*Yqi{cehhv?012?6485>2_;#j|i.sd,i`k(omg%h`!Pv`pjjac89:;0?<1279V4*aun'xm#`kb/ffn*ak(Wkyecjjx12349446;<0Y=!hrg,qb*kbe&moa#jb/^tbvlhcmq:;<=2=4?05?P6(o{l%~k!bel-d`h(ce&U}mgaddz3456;:<49:6[?/fpe*w`(elg$kic!dl-\rdtnfmos<=>?<34=63=R8&myj#|i/lgn+bbj&mg$S{o}ioff|567858<2?84U1-dvc(un&gna"ikm/fn+Zpfz`doiu>?01>1<;413\:$kh!rg-nah)`ld$oa"Qyaskm``~789:7>40=5:W3+bta&{l$ahc geo-`h)X~hxbbikw01238785>2_;#j|i.sd,i`k(omg%h`!Pv`pjjac89:;0>>1279V4*aun'xm#`kb/ffn*ak(Wkyecjjx12349566;<0Y=!hrg,qb*kbe&moa#jb/^tbvlhcmq:;<=2<2?05?P6(o{l%~k!bel-d`h(ce&U}mgaddz3456;;:49:6[?/fpe*w`(elg$kic!dl-\rdtnfmos<=>?<26=63=R8&myj#|i/lgn+bbj&mg$S{o}ioff|567859>2?;4U1-dvc(un&gna"ikm/fn+Zpfz`doiu>?01>0:73<]9%l~k }f.ofi*ace'nf#Rxnrhlga}67896?2?;4U1-dvc(un&gna"ikm/fn+Zpfz`doiu>?01>6:73<]9%l~k }f.ofi*ace'nf#Rxnrhlga}67896=2?;4U1-dvc(un&gna"ikm/fn+Zpfz`doiu>?01>4:73<]9%l~k }f.ofi*ace'nf#Rxnrhlga}6789632?;4U1-dvc(un&gna"ikm/fn+Zpfz`doiu>?01>::4c<]9%l~k }f.ofi*ace'nf#iazt^k?4;7a3\:$kh!rg-nah)`ld$oa"j`uu]j84699o1^<"i}f/pe+hcj'nnf"ic dnww[l:697;m7X> gsd-vc)jmd%lh` km.flqqYn4885=k5Z0.eqb+ta'dof#jjb.eo,`jssW`6:?3?i;T2,cw`)zo%fi`!hdl,gi*bh}}Ub0<:11g9V4*aun'xm#`kb/ffn*ak(lfSd2>5?3e?P6(o{l%~k!bel-d`h(ce&ndyyQf<04=5c=R8&myj#|i/lgn+bbj&mg$hb{{_h>23;7a3\:$kh!rg-nah)`ld$oa"j`uu]j84>99o1^<"i}f/pe+hcj'nnf"ic dnww[l:617;n7X> gsd-vc)jmd%lh` km.flqqYn484:j6[?/fpe*w`(elg$kic!dl-gkprXa58;2<h4U1-dvc(un&gna"ikm/fn+air|Vc7><0>f:W3+bta&{l$ahc geo-`h)cg|~Te1<=>0d8Q5)`zo$yj"cjm.egi+bj'me~xRg322<2b>S7'nxm"h mdo,cak)ld%ocxzPi=07:4`<]9%l~k }f.ofi*ace'nf#iazt^k?6086n2_;#j|i.sd,i`k(omg%h`!kotv\m94168l0Y=!hrg,qb*kbe&moa#jb/emvpZo;:>4:j6[?/fpe*w`(elg$kic!dl-gkprXa5832<h4U1-dvc(un&gna"ikm/fn+air|Vc7>40>e:W3+bta&{l$ahc geo-`h)cg|~Te1<11g9V4*aun'xm#`kb/ffn*ak(lfSd2<0?3e?P6(o{l%~k!bel-d`h(ce&ndyyQf<23=5c=R8&myj#|i/lgn+bbj&mg$hb{{_h>06;7a3\:$kh!rg-nah)`ld$oa"j`uu]j86599o1^<"i}f/pe+hcj'nnf"ic dnww[l:4<7;m7X> gsd-vc)jmd%lh` km.flqqYn4:?5=h5Z0.eqb+ta'dof#jjb.eo,`jssW`682<k4U1-dvc(un&gna"ikm/fn+air|Vc783?j;T2,cw`)zo%fi`!hdl,gi*bh}}Ub080>e:W3+bta&{l$ahc geo-`h)cg|~Te1811d9V4*aun'xm#`kb/ffn*ak(lfSd28>0g8Q5)`zo$yj"cjm.egi+bj'me~xRg38?3f?P6(o{l%~k!bel-d`h(ce&ndyyQf<8<2`>S7'nxm"h mdo,cak)ld%ocxzPi^22`>S7'nxm"h mdo,cak)ld%ocxzPi^32a>S7'nxm"h mdo,cak)ld%ocxzPi^335`=R8&myj#|i/lgn+bbj&mg$hb{{_h]254c<]9%l~k }f.ofi*ace'nf#iazt^k\577b3\:$kh!rg-nah)`ld$oa"j`uu]j[456m2_;#j|i.sd,i`k(omg%h`!kotv\mZ739l1^<"i}f/pe+hcj'nnf"ic dnww[lY6=8o0Y=!hrg,qb*kbe&moa#jb/emvpZoX9?;n7X> gsd-vc)jmd%lh` km.flqqYnW8=:i6[?/fpe*w`(elg$kic!dl-gkprXaV;3=h5Z0.eqb+ta'dof#jjb.eo,`jssW`U:5<j4U1-dvc(un&gna"ikm/fn+air|VcT><k4U1-dvc(un&gna"ikm/fn+air|VcT>=?j;T2,cw`)zo%fi`!hdl,gi*bh}}UbS??>e:W3+bta&{l$ahc geo-`h)cg|~TeR<=1d9V4*aun'xm#`kb/ffn*ak(lfSdQ=30g8Q5)`zo$yj"cjm.egi+bj'me~xRgP253f?P6(o{l%~k!bel-d`h(ce&ndyyQf_372a>S7'nxm"h mdo,cak)ld%ocxzPi^055`=R8&myj#|i/lgn+bbj&mg$hb{{_h]134c<]9%l~k }f.ofi*ace'nf#iazt^k\6=7b3\:$kh!rg-nah)`ld$oa"j`uu]j[7?6l2_;#j|i.sd,i`k(omg%h`!kotv\mZ56m2_;#j|i.sd,i`k(omg%h`!kotv\mZ579l1^<"i}f/pe+hcj'nnf"ic dnww[lY498o0Y=!hrg,qb*kbe&moa#jb/emvpZoX;;;n7X> gsd-vc)jmd%lh` km.flqqYnW:9:i6[?/fpe*w`(elg$kic!dl-gkprXaV9?=h5Z0.eqb+ta'dof#jjb.eo,`jssW`U89<j4U1-dvc(un&gna"ikm/fn+air|VcT8<j4U1-dvc(un&gna"ikm/fn+air|VcT9<j4U1-dvc(un&gna"ikm/fn+air|VcT:<j4U1-dvc(un&gna"ikm/fn+air|VcT;<j4U1-dvc(un&gna"ikm/fn+air|VcT4<j4U1-dvc(un&gna"ikm/fn+air|VcT5?;4U1-dvc(un&gna"ikm/fn+lht|VF[ARCZX022575<]9%l~k }f.ofi*ace'nf#d`|t^NSIZKRP8;996[?/fpe*w`(elg$kic!dl-jjvrXDYGTAXV>10312>S7'nxm"h mdo,cak)ld%bb~zPLQO\IP^698;:>85Z0.eqb+ta'dof#jjb.eo,mkusWEZFS@[W133260=R8&myj#|i/lgn+bbj&mg$ec}{_MRN[HS_9:;:>85Z0.eqb+ta'dof#jjb.eo,mkusWEZFS@[W153260=R8&myj#|i/lgn+bbj&mg$ec}{_MRN[HS_9<;:>85Z0.eqb+ta'dof#jjb.eo,mkusWEZFS@[W173260=R8&myj#|i/lgn+bbj&mg$ec}{_MRN[HS_9>;:>85Z0.eqb+ta'dof#jjb.eo,mkusWEZFS@[W193260=R8&myj#|i/lgn+bbj&mg$ec}{_MRN[HS_90;:>85Z0.eqb+ta'dof#jjb.eo,mkusWEZFS@[W213260=R8&myj#|i/lgn+bbj&mg$ec}{_MRN[HS_:8;:>;5Z0.eqb+ta'dof#jjb.eo,mkusWEZFS@[W2032573<]9%l~k }f.ofi*ace'nf#d`|t^NSIZKRP;8:=?;4U1-dvc(un&gna"ikm/fn+lht|VF[ARCZX312573<]9%l~k }f.ofi*ace'nf#d`|t^NSIZKRP;>:=?;4U1-dvc(un&gna"ikm/fn+lht|VF[ARCZX372573<]9%l~k }f.ofi*ace'nf#d`|t^NSIZKRP;<:=?;4U1-dvc(un&gna"ikm/fn+lht|VF[ARCZX352573<]9%l~k }f.ofi*ace'nf#d`|t^NSIZKRP;2:=?;4U1-dvc(un&gna"ikm/fn+lht|VF[ARCZX3;2573<]9%l~k }f.ofi*ace'nf#d`|t^NSIZKRP:::=?;4U1-dvc(un&gna"ikm/fn+lht|VF[ARCZX232570<]9%l~k }f.ofi*ace'nf#d`|t^NSIZKRP:;:=<<:;T2,cw`)zo%fi`!hdl,gi*oi{}UG\@QBUY1154423\:$kh!rg-nah)`ld$oa"gasu]OTHYJ]Q98=<<:;T2,cw`)zo%fi`!hdl,gi*oi{}UG\@QBUY1754423\:$kh!rg-nah)`ld$oa"gasu]OTHYJ]Q9>=<<;;T2,cw`)zo%fi`!hdl,gi*oi{}UG\@QBUY62572<]9%l~k }f.ofi*ace'nf#d`|t^NSIZKRP<;:>95Z0.eqb+ta'dof#jjb.eo,mkusWEZFS@[W60310>S7'nxm"h mdo,cak)ld%bb~zPLQO\IP^0988?7X> gsd-vc)jmd%lh` km.kmwqYKXDUFYU6>1368Q5)`zo$yj"cjm.egi+bj'`dxxRB_M^OV\<769o1^<"i}f/pe+hcj'nnf"ic wskwaZesze8;7X> gsd-vc)jmd%lh` km.uqmqcXk}xg=<j4U1-dvc(un&xxxobd/SQW[CSKDVMNB<j4U1-dvc(un&xxxobd/sf\vvrXizxnk?>4U1-dvc(un&xxxobd/sf\vvrXizxnkRj>219V4*aun'xm#}{bmi,vaYu{}Ujkh_e02g>S7'nxm"h rrvahn)ulVxxxRm`mc3g?P6(o{l%~k!}su`oo*tcW{ySnabb03f?P6(o{l%~k!}su`oo*tcW{ySkh<1<2a>S7'nxm"h rrvahn)ulVxxxR|jg=3=5`=R8&myj#|i/sqwfim(zmUyyQ}ef>1:4b<]9%l~k }f.pppgjl'{nT~~zPrde\44b<]9%l~k }f.pppgjl'{nT~~zPrde\54b<]9%l~k }f.pppgjl'{nT~~zPrde\641<]9%l~k }f.pppgjl'{ySi?>7:W3+bta&{l$~~zmlj-qwqYc:8=0Y=!hrg,qb*tt|kf`#}{_e12`>S7'nxm"h rrvahn)pzVxxxRo|rde14>S7'nxm"h rrvahn)pzVxxxRo|rde\`4473\:$kh!rg-qwqdkc&}yS}{_`qqabYc:8i0Y=!hrg,qb*tt|kf`#z|Prrv\gjke9m1^<"i}f/pe+wusjea${Q}su]`khd69l1^<"i}f/pe+wusjea${Q}su]qab:768o0Y=!hrg,qb*tt|kf`#z|Prrv\v`a;97;o7X> gsd-vc)u{}hgg"y}_sqw[wc`W9;o7X> gsd-vc)u{}hgg"y}_sqw[wc`W8k0Y^K]_@NJEVe<]ZOYS[G\ICNF7>PDK01]EHYPTXRF0>QDDB80[H?k;YKOMK^*PMH+<#?/SUWA$5(6(HYHED;4XNP@]3=_[]FBN:5WSU]DJA1<PZ^TZNMm;Y]@KWCXAGLD:6Vkb^Kgb>^c`VZye`Xjrrklj46<PmgTAld`rWgqwlii991Sh`QBiomqR`ttafdh7lbborv\ahvsqk1j``a|t^dvhi0<jhi`y}j4b`ahquYji{an~>5lljf8`drfWje~by&?)e9geqgXkfex%?&d:fbpdYdg|d$?'k;ecweZeh}g~#?$j4d`vb[firf}"?%k5kauc\gjsi|5>1<394dckwawt13mce$='9;ekm,4/03mce$<>&7:fjj-76!>1oec&>2(58`lh/9:#<7iga(06*3>bnf!;>%:5kio*22,1<l`d#=:'8;ekm,4>.?2nbb%?6)79gmk.5!>1oec&=0(58`lh/:8#<7iga(30*3>bnf!88%:5kio*10,1<l`d#>8'8;ekm,70.?2nbb%<8)69gmk.50 =0hd`'28+5?aoi :#<7iga(22*3>bnf!9:%:5kio*06,1<l`d#?>'8;ekm,62.?2nbb%=:)79gmk.3!?1oec&:)79gmk.1!?1oec&8)79gmk.?!?1oec&6)79gmk:76>1oec2>0?58`lh;984<7iga<00=3>bnf5;82:5kio>20;1<l`d7=808;ekm8409?2nbb1?8>69gmk:607=0hd`318<5?aoi484<7iga<32=3>bnf58:2:5kio>16;1<l`d7>>08;ekm8729?2nbb1<:>69gmk:5>7=0hd`326<4?aoi4;25;6jfn=0::3=cag692:5kio>04;1<l`d7?<08;ekm8649?2nbb1=<>69gmk:4<730hd`33483:2=cag689384dhl?7;0<l`d78384dhl?1;0<l`d7:384dhl?3;0<l`d74384dhl?=;1<lf$='8;emvp-7.02ndyy&>0(:8`jss 8;"46j`uu*26,><lf$<=&8:flqq.6< 20hb{{(07*<>bh}}"::$64dnww,41.02ndyy&>8(:8`jss 83";6j`uu*1-==cg|~#>='7;emvp-46!11ocxz'23+;?air|!88%55kotv+61/?3me~x%<:)99gkpr/:?#37iazt)04-==cg|~#>5'7;emvp-4>!>1ocxz'3(:8`jss ::"46j`uu*05,><lf$><&8:flqq.4; 20hb{{(26*<>bh}}"89$94dnww,1/03me~x%;&7:flqq.1!>1ocxz'7(58`jss 1#<7iazt);*3>bh}}6;255kotv?558?3me~x1?>>99gkpr;9;437iazt=30:==cg|~7=907;emvp972611ocxz317<;?air|5;<255kotv?5=8?3me~x1?6>69gkpr;9720hb{{<32=<>bh}}69=364dnww874902ndyy2=3?:8`jss4;>546j`uu>11;><lf0?818:flqq:5?720hb{{<3:=<>bh}}695394dnww878?3me~x1=?>99gkpr;;8437iazt=11:==cg|~7?>07;emvp9536h1ocxz33483:==cg|~7?808;emvp959?2ndyy2;>69gkpr;=7=0hb{{<7<4?air|5=5;6j`uu>;:2=cg|~75364eeke6kac=2of|yw=f:djbjY`mgoymya}_w4\5)&_aecet-M@RD"Dakcui}ey,<<!2068bl`hWqfetR==x24\6fjl;;1mekaPxml{[64;?U9oae#fhdl[bcim{kcQy6^3/JJHB$GEEI>kn;gkekZ~kfqU8>u=9_3aoo)`nnfUlick}aumq[s0X9%qhSeo|_hlw[fjl59&hSeo|_rppp86+kVxoSk|jq<3/gZciikfnS}{_r{mg87+kVbjR|k_ecweZeh}g~6<!mPdhl\slbs`49= nQgar]tvZbf|hUhcx`{=1.`[cskdVlgmj}Prrv\rdj:9%iTe`~celgmpdrnggUu}k22-a\qvcXmdhnhikk_sgd95*dW~xTjk~=0.`[pubWme~xR||t<3/gZsillxm`byPlnu>4)eX`hyTc{k}fmmt95*dWyxn`bok_mcwake~59&hSiazt^uj`qn:;?&hS`}hoo]uei;6$jUyhRjjpuj>77*dWlxycQfnkg`pliiW}s{i0>#c^jbwZsillxm`by20-a\lduXiegdyQiumn>5)eX`hyT~~z21-a\`drfWje~byQxievk90*dWakxSz|Pabi>4)eX}zoTinm20-a\gjkjggUh`bmd=1.`[rtXijaT`by20-a\vaYwf}xT{dj{h<7/gZstmVl|jyQkauc\gjsi|4:'oRfns^coijusWlg{xt3?,b]q`Zbf|hUhcx`{_vkgpm;2$jUdzh|ilnu\hjq:8%iT{Qnup\slbs`4?'oR~}of]fiur~W}s{i0>#c^uq[agsiVidyczPwhfwl83+kVzyiaand^pfcv;6$jUocxzPrrv\rdj:8%iTdl}Pd`vb[firf}7; nQrne\bpjkW}byi~fPndebp`Yqie79?!mPws]gauro5:8'oR~}of]fiur~W}byi~fPndebp`Yqie7> nQrne\ahvsqV~c~h}g_`qpawrX~hf68!mPh`q\rdjnl4:'oR~}of]eqijX|axneQnsrgqpZpfd48? nabpnlfjqYiido6jdh`_ynm|Z55p:<T>nbd,b]ueiocWee|1="l_qpjiZ`nnfUu}k2500{73*dWyxdkRhzlm]w}uc:9%iTahc`rx]w}uc::%w9i6hffn]{hk~X;;r8:R<llj]emciXoldn~lz`r^t5[4Y{}U:86hzlmf8mklbk}nieyk}re9jjocd|zhbxh|}7:kmpZekc11eknlzimf;?jpbzofd{l5rne\ahvsq8>0|ah_dosp|Ys`{oxd%>&159svjaXmdzuRzgrdqk,4/6<2zycjQjmqvz[qnumzb#>$?;;qplcZcjx}sTxe|jsi*0-42<x{elShctx]wlwct`!>"=;5rne\ahvsqV~c~h}g<583:4d<x{elShctx]wlwct`Vkxh|{(1+2f>vugnUna}zv_ujqavnXizyn~y&>)0`8twi`Wlg{xtQ{hsgplZgt{lx$?'>b:rqkbYbey~rSyf}erj\evubz}"8%<l4psmd[`kw|pUdk|h^cpw`ts =#:h6~}of]fiur~W}byi~fParqfvq:3294:n6~}of]fiur~W}byi~fPndebp`.7!8h0|ah_dosp|Ys`{oxdR`jg`vf,4/6j2zycjQjmqvz[qnumzbTbhintd*1-4d<x{elShctx]wlwct`Vdnklzj(2+2f>vugnUna}zv_ujqavnXflmjxh&;)0f8twi`Wlg{xtQ{hsgplZhboh~n094?>89svjaXn|fg=>5rne\bpjkW}byi~f'0(30?uthoVl~`aQ{hsgpl-7.9:1{~biPftno[qnumzb#>$?<;qplcZ`rdeUdk|h)1*56=wzfmTjxbc_ujqavn/< ;>7}|`g^dvhiYs`{oxd1:50?3b?uthoVl~`aQ{hsgplZgt{lx$='>a:rqkbYa}efTxe|jsi]bwvcu|!;"=l5rne\bpjkW}byi~fParqfvq.5!8k0|ah_gwohZrozlycSl}|esv+7,7f3yxdkRhzlm]wlwct`Vkxh|{(5+2g>vugnUmyabPtipfwmYf{zoyx1:50?3b?uthoVl~`aQ{hsgplZhboh~n$='>a:rqkbYa}efTxe|jsi]mabgsm!;"=l5rne\bpjkW}byi~fPndebp`.5!8k0|ah_gwohZrozlycSckhaug+7,7f3yxdkRhzlm]wlwct`Vdnklzj(5+2g>vugnUmyabPtipfwmYimnki1:50?48vaYddb;;7jPd`vb[firf}";%<>4re]geqgXkfex%?&119q`Zbf|hUhcx`{(3+24>tcWmkmRm`uov+7,773{nThlzn_bmvjq.3!8:0~iQkauc\gjsi|5:5=?5}d^fbpdYdg|d094?>49q`Zci>2xoS}{3:ppp2=tj`~n~:4ssqw0>ru}l30ycjjrgnls0=qieco:6y}_`ah2>quWjf`==5xr^fbpdYdg|d$='>0:uq[agsiVidycz'1(33?rtXlh~jSnaznu*1-46<{UomyoPcnwmp-5.991|~Rjnt`]`kphs =#:>6y}_ecweZeh}g~787>15:uq[`h13~xT~~zr@Arf5==GHq;1J7:51zQ00?5a=3?1=><m7859572alrd8984>;o162?0<,:?86>:k;|Q06?5a=3?1=><m7859572al2Y?j7:?0;29564e?0=1=?:ie:Q06?2783:1=><m7859572an2n8j54?:082V532:l>684>33`4=2<6:=lo7{Zm9;295?7=913p_>:53g791?74:k=2;7?=4gf8 62f2<:0Z>;;:3yv1<<63|?j6=5r$c09f>d4n10;68?53;72M5302P9o7<ta;;9y!de2:l37)=:2;1e3>o3;90;66a<5983>>i39<0;66g;4183>>i4nj0;66a<f783>>o3;00;66g;3383>>i4k00;6)l;:2g`?kd42910c>m7:18'f1<4mj1en>4>;:m0g2<72-h?6>kl;o`0>7=<g:i=6=4+b580af=ij:0876a<c483>!d32:oh7cl<:598k6e3290/n94<eb9mf6<232e8o?4?:%`7>6cd3gh86;54o2a2>5<#j=08in5ab284?>i4k90;6)l;:2g`?kd42110c>li:18'f1<4mj1en>46;:m0f`<72-h?6>kl;o`0>d=<g:ho6=4+b580af=ij:0i76a<bb83>!d32:oh7cl<:b98k6de290/n94<eb9mf6<c32e8nl4?:%`7>6cd3gh86h54o2`:>5<#j=08in5ab28e?>i4j>0;6)l;:2g`?kd428:07b=m6;29 g2=;li0bo=51098k6d2290/n94<eb9mf6<6:21d?o:50;&a0?5bk2di?7?<;:m0f6<72-h?6>kl;o`0>42<3f9i>7>5$c697`e<fk91=854o2`2>5<#j=08in5ab2822>=h;k:1<7*m4;1fg>he;3;<76a<ag83>!d32:oh7cl<:0:8?j5fm3:1(o:53da8jg5=9010c>mi:18'f1<4mj1en>4>a:9l7fc=83.i87=jc:la7?7e32e8oi4?:%`7>6cd3gh86<m4;n1`g?6=,k>1?hm4nc195a=<g:ii6=4+b580af=ij:0:i65`3bc94?"e<39no6`m3;3e?>i4k:0;6)l;:2g`?kd42;:07b=m8;29 g2=;li0bo=52098k6gc290/n94<eb9mf6<5:21d?lm50;&a0?5bk2di?7<<;:k0<5<72-h?6>o<;o`0>5=<a:=m6=4+b580e6=ij:0:76g<7d83>!d32:k87cl<:398m61c290/n94<a29mf6<432c8;n4?:%`7>6g43gh86954i25a>5<#j=08m>5ab286?>o4?00;6)l;:2c0?kd42?10e>97:18'f1<4i:1en>48;:k032<72-h?6>o<;o`0>==<a:==6=4+b580e6=ij:0276g<7483>!d32:k87cl<:`98m613290/n94<a29mf6<e32c8;>4?:%`7>6g43gh86n54i251>5<#j=08m>5ab28g?>o4?80;6)l;:2c0?kd42l10e>9?:18'f1<4i:1en>4i;:k02`<72-h?6>o<;o`0>46<3`9=h7>5$c697d5<fk91=<54i24`>5<#j=08m>5ab2826>=n;?h1<7*m4;1b7>he;3;876g<6`83>!d32:k87cl<:068?l5113:1(o:53`18jg5=9<10e>87:18'f1<4i:1en>4>6:9j731=83.i87=n3:la7?7032c8:;4?:%`7>6g43gh86<64;h151?6=,k>1?l=4nc195<=<a:2=6=4+b580e6=ij:0:m65f39794?"e<39j?6`m3;3a?>o40=0;6)l;:2c0?kd428i07d=73;29 g2=;h90bo=51e98m6>5290/n94<a29mf6<6m21b?5?50;&a0?5f;2di?7?i;:k03d<72-h?6>o<;o`0>76<3`9=j7>5$c697d5<fk91><54i247>5<#j=08m>5ab2816>=n;?91<7*m4;1b7>he;38876g;2983>>d4<00;6<4?:1yK71><,kh1?974oc394?=zj=?1<7?50;2xL62?3-hi69;4o5694?=zj;h1<76i:043>4>>sA9?46T=c;3546=n3;:6<;513827?732h026<8516821?702h0::7??:8820?742881=<4i:|&af?5aj2.9j7=i9:&07?5ai2.jh7l?;h63`?6=,k>18=k4nc194>=n<9i1<7*m4;63a>he;3;07d:?b;29 g2=<9o0bo=52:9j05g=83.i87:?e:la7?5<3`>;57>5$c6905c<fk91865f3gg94?=n<:;1<75f42694?=h<:=1<75f41594?"e<3>;46`m3;28?l27>3:1(o:541:8jg5=921b8=;50;&a0?2702di?7<4;h630?6=,k>18=64nc197>=n<991<7*m4;63<>he;3>07d:<0;29?j2793:17d:>3;29 g2=<8>0bo=50:9j044=83.i87:>4:la7?7<3`>:=7>5$c69042<fk91>65f40294?"e<3>:86`m3;18?l27n3:1(o:54068jg5=<21d?8650;9l736=83.i87=91:la7?6<3f9>j7>5$c69737<fk91=65`34g94?"e<39==6`m3;08?j52l3:1(o:53738jg5=;21d?8m50;&a0?5192di?7:4;n621?6=3`>?<7>5;h62e?6=,k>18<l4nc194>=n<831<7*m4;62f>he;3;07d:>8;29 g2=<8h0bo=52:9j041=83.i87:>b:la7?5<3`>::7>5$c6904d<fk91865`3ga94?=h;o<1<75f42;94?=n;<k1<75f43294?"e<3>9=6`m3;28?l26n3:1(o:54338jg5=921b8<k50;&a0?2592di?7<4;h62`?6=,k>18??4nc197>=n<8i1<7*m4;615>he;3>07d:=6;29 g2=<;=0bo=50:9j073=83.i87:=7:la7?7<3`>987>5$c69071<fk91>65f43194?"e<3>9;6`m3;18?l25:3:1(o:54358jg5=<21d?8950;9j7c`=831b?8l50;9j017=831d8>=50;9l06>=831b8><50;9l7f?=83.i87=jc:la7?6<3f9h47>5$c697`e<fk91=65`3b594?"e<39no6`m3;08?j5d>3:1(o:53da8jg5=;21d?n;50;&a0?5bk2di?7:4;n1`0?6=,k>1?hm4nc191>=h;j81<7*m4;1fg>he;3<07b=l1;29 g2=;li0bo=57:9l7f6=83.i87=jc:la7?><3f9ij7>5$c697`e<fk91565`3cg94?"e<39no6`m3;c8?j5el3:1(o:53da8jg5=j21d?om50;&a0?5bk2di?7m4;n1af?6=,k>1?hm4nc19`>=h;kk1<7*m4;1fg>he;3o07b=m9;29 g2=;li0bo=5f:9l7g1=83.i87=jc:la7?7732e8n;4?:%`7>6cd3gh86<?4;n1a1?6=,k>1?hm4nc1957=<g:h?6=4+b580af=ij:0:?65`3c194?"e<39no6`m3;37?>i4j;0;6)l;:2g`?kd428?07b=m1;29 g2=;li0bo=51798k6d7290/n94<eb9mf6<6?21d?lh50;&a0?5bk2di?7?7;:m0e`<72-h?6>kl;o`0>4?<3f9hj7>5$c697`e<fk91=l54o2af>5<#j=08in5ab282f>=h;jn1<7*m4;1fg>he;3;h76a<cb83>!d32:oh7cl<:0f8?j5dj3:1(o:53da8jg5=9l10c>mn:18'f1<4mj1en>4>f:9l7f5=83.i87=jc:la7?4732e8n54?:%`7>6cd3gh86??4;n1b`?6=,k>1?hm4nc1967=<g:kh6=4+b580af=ij:09?65f39294?"e<39j?6`m3;28?l50n3:1(o:53`18jg5=921b?:k50;&a0?5f;2di?7<4;h14`?6=,k>1?l=4nc197>=n;>i1<7*m4;1b7>he;3>07d=8b;29 g2=;h90bo=55:9j72?=83.i87=n3:la7?0<3`9<47>5$c697d5<fk91;65f36594?"e<39j?6`m3;:8?l50>3:1(o:53`18jg5=121b?:;50;&a0?5f;2di?7o4;h140?6=,k>1?l=4nc19f>=n;>91<7*m4;1b7>he;3i07d=82;29 g2=;h90bo=5d:9j727=83.i87=n3:la7?c<3`9<<7>5$c697d5<fk91j65f37g94?"e<39j?6`m3;33?>o4>m0;6)l;:2c0?kd428;07d=9c;29 g2=;h90bo=51398m60e290/n94<a29mf6<6;21b?;o50;&a0?5f;2di?7?;;:k02<<72-h?6>o<;o`0>43<3`9=47>5$c697d5<fk91=;54i244>5<#j=08m>5ab2823>=n;?<1<7*m4;1b7>he;3;376g<6483>!d32:k87cl<:0;8?l5?>3:1(o:53`18jg5=9h10e>6::18'f1<4i:1en>4>b:9j7=2=83.i87=n3:la7?7d32c84>4?:%`7>6g43gh86<j4;h1;6?6=,k>1?l=4nc195`=<a:2:6=4+b580e6=ij:0:j65f36c94?"e<39j?6`m3;03?>o4>o0;6)l;:2c0?kd42;;07d=94;29 g2=;h90bo=52398m604290/n94<a29mf6<5;21b?8750;9l07b=83.i87:=f:la7?6<3f>9o7>5$c6907`<fk91=65`43`94?"e<3>9j6`m3;08?j25i3:1(o:543d8jg5=;21d8?750;&a0?25n2di?7:4;n60a?6=,k>18>h4nc194>=h<:n1<7*m4;60b>he;3;07b:<c;29 g2=<:l0bo=52:9l06d=83.i87:<f:la7?5<3f>8m7>5$c6906`<fk91865`41094?=n;on1<75`37094?=n<;21<75`42494?=e;<:1<7?50;2x gd=<<1C?9h4H26;?j232900qo=:1;295?6=8r.in7=;9:J00c=O;=20co?50;9~f45e290?6=4?{%`a>14<@:>m7E=;8:&7f?2<a;n1<75f3483>>oe=3:17bl9:188yg55n3:187>50z&af?273A9?j6F<499'0g<53`8o6=44i2394?=n;<0;66am6;29?xd4;m0;694?:1y'fg<3:2B88k5G35:8L7g<,<=18>;4$5`90>o5l3:17d=::188mg3=831dn;4?::a764=8391<7>t$c`97c=O;=l0D>:7;I0b?!302=9>7):m:39j6a<722c897>5;n`5>5<<uk9?<7>53;294~"ej39m7E=;f:J00==O:h1/9:4;349'0g<53`8o6=44i2794?=hj?0;66sm32a94?2=83:p(ol5439K71`<@:>37E<n;%74>1523->i695f2e83>>o4=3:17dl::188kg0=831vn>=>:180>5<7s-hi6>h4H26e?M5302B9m6*:7;601>"3j380e?j50;9j70<722ei:7>5;|`07`<72<0;6=u+bc877>N4<o1C?964H3c8 01=<:?0e?j50;9j6`<722c897>5;h`6>5<<gk<1<75rb21e>5<4290;w)lm:2d8L62a3A9?46F=a:&63?24=2.?n7<4i3f94?=n;<0;66am6;29?xd4;90;684?:1y'fg<3;2B88k5G35:8L7g<,<=18>;4i3f94?=n:l0;66g<5;29?ld22900co850;9~f65e290?6=4?{%`a>14<@:>m7E=;8:J1e>"2?3>896*;b;68m7b=831b?84?::ka1?6=3fh=6=44}c10e?6=<3:1<v*mb;61?M53n2B8855+4c87?l4c2900e>;50;9jf0<722ei:7>5;|`07<<72=0;6=u+bc876>N4<o1C?964$5`90>o5l3:17d=::188mg3=831dn;4?::a76>=83>1<7>t$c`907=O;=l0D>:7;%6a>1=n:m0;66g<5;29?ld22900co850;9~f621290?6=4?{%`a>14<@:>m7E=;8:&7f?2<a;n1<75f3483>>oe=3:17bl9:188yg53=3:187>50z&af?253A9?j6F<499'0g<33`8o6=44i2794?=nj<0;66am6;29?xddl3:187>50z&af?273A9?j6F<499'0g<53`8o6=44i2394?=n;<0;66am6;29?xddk3:187>50z&af?273A9?j6F<499'0g<53`8o6=44i2394?=n;<0;66am6;29?xddj3:187>50z&af?273A9?j6F<499'0g<53`8o6=44i2394?=n;<0;66am6;29?xddi3:187>50z&af?273A9?j6F<499'0g<53`8o6=44i2394?=n;<0;66am6;29?xdd13:187>50z&af?273A9?j6F<499'0g<53`8o6=44i2394?=n;<0;66am6;29?xd6880;694?:1y'fg<382B88k5G35:8 1d=:2c9h7>5;h12>5<<a:?1<75`b783>>{e99:1<7:50;2x gd=<91C?9h4H26;?!2e2;1b>i4?::k05?6=3`9>6=44oc494?=zjol1<7:50;2x gd=<91C?9h4H26;?!2e2;1b>i4?::k05?6=3`9>6=44oc494?=zjoo1<7:50;2x gd=<91C?9h4H26;?!2e2;1b>i4?::k05?6=3`9>6=44oc494?=zjon1<7:50;2x gd=<91C?9h4H26;?!2e2;1b>i4?::k05?6=3`9>6=44oc494?=zj88<6=4;:183!de2=:0D>:i;I17<>"3j380e?j50;9j74<722c897>5;n`5>5<<uk;9:7>54;294~"ej3>;7E=;f:J00==#<k097d<k:188m67=831b?84?::ma2?6=3th:>84?:583>5}#jk0?<6F<4g9K71><,=h1>6g=d;29?l562900e>;50;9lf3<722wi=?:50;694?6|,kh18=5G35d8L62?3->i6?5f2e83>>o493:17d=::188kg0=831vn<<<:187>5<7s-hi69>4H26e?M5302.?n7<4i3f94?=n;80;66g<5;29?jd12900qoh<:187>5<7s-hi69>4H26e?M5302.?n7<4i3f94?=n;80;66g<5;29?jd12900qoh=:187>5<7s-hi69>4H26e?M5302.?n7<4i3f94?=n;80;66g<5;29?jd12900qoh>:187>5<7s-hi69>4H26e?M5302.?n7<4i3f94?=n;80;66g<5;29?jd12900qoh?:187>5<7s-hi69>4H26e?M5302.?n7<4i3f94?=n;80;66g<5;29?jd12900qoki:187>5<7s-hi69>4H26e?M5302.?n7<4i3f94?=n;80;66g<5;29?jd12900qo?>d;290?6=8r.in7:?;I17b>N4<11C>l5+568770=#<k097d<k:188m67=831b?84?::ma2?6=3th:=n4?:583>5}#jk0?<6F<4g9K71><@;k0(8954278 1d=:2c9h7>5;h12>5<<a:?1<75`b783>>{e98h1<7:50;2x gd=<91C?9h4H26;?M4f3-?<69=:;%6a>7=n:m0;66g<1;29?l522900co850;9~f47f290?6=4?{%`a>16<@:>m7E=;8:J1e>"2?3>896*;b;08m7b=831b?<4?::k01?6=3fh=6=44}c32=?6=<3:1<v*mb;63?M53n2B8855G2`9'12<3;<1/8o4=;h0g>5<<a:;1<75f3483>>ie>3:17plj9;290?6=8r.in7:?;I17b>N4<11C>l5+568770=#<k097d<k:188m67=831b?84?::ma2?6=3thn47>54;294~"ej3>;7E=;f:J00==O:h1/9:4;349'0g<53`8o6=44i2394?=n;<0;66am6;29?xdb?3:187>50z&af?273A9?j6F<499K6d=#=>0??85+4c81?l4c2900e>?50;9j70<722ei:7>5;|`f2?6=<3:1<v*mb;63?M53n2B8855G2`9'12<3;<1/8o4=;h0g>5<<a:;1<75f3483>>ie>3:17plj5;290?6=8r.in7:?;I17b>N4<11C>l5+568770=#<k097d<k:188m67=831b?84?::ma2?6=3thoj7>54;294~"ej3>;7E=;f:J00==#<k097d<k:188m67=831b?84?::ma2?6=3thoi7>54;294~"ej3>;7E=;f:J00==#<k097d<k:188m67=831b?84?::ma2?6=3thoh7>54;294~"ej3>;7E=;f:J00==#<k097d<k:188m67=831b?84?::ma2?6=3thoo7>54;294~"ej3>;7E=;f:J00==#<k097d<k:188m67=831b?84?::ma2?6=3thon7>54;294~"ej3>;7E=;f:J00==#<k097d<k:188m67=831b?84?::ma2?6=3th:=>4?:583>5}#jk0?<6F<4g9K71><,=h1>6g=d;29?l562900e>;50;9lf3<722wi=<<50;694?6|,kh18=5G35d8L62?3->i6?5f2e83>>o493:17d=::188kg0=831vn<?>:187>5<7s-hi69>4H26e?M5302.?n7<4i3f94?=n;80;66g<5;29?jd12900qo?>0;290?6=8r.in7:?;I17b>N4<11/8o4=;h0g>5<<a:;1<75f3483>>ie>3:17pl>0g83>1<729q/no4;0:J00c=O;=20(9l52:k1`?6=3`9:6=44i2794?=hj?0;66sm14;94?3=83:p(ol5409K71`<@:>37):m:39j6a<722c9i7>5;h12>5<<a:?1<75`b783>>{e9<21<7;50;2x gd=<81C?9h4H26;?!2e2;1b>i4?::k1a?6=3`9:6=44i2794?=hj?0;66sm14494?3=83:p(ol5409K71`<@:>37):m:39j6a<722c9i7>5;h12>5<<a:?1<75`b783>>{e9<?1<7;50;2x gd=<:1C?9h4H26;?!2e2=1b>i4?::k1a?6=3`9>6=44ic794?=hj?0;66sm14594?3=83:p(ol5409K71`<@:>37):m:39j6a<722c9i7>5;h12>5<<a:?1<75`b783>>{e9?91<7;50;2x gd=<81C?9h4H26;?!2e2;1b>i4?::k1a?6=3`9:6=44i2794?=hj?0;66sm17094?3=83:p(ol5409K71`<@:>37):m:39j6a<722c9i7>5;h12>5<<a:?1<75`b783>>{e9?;1<7;50;2x gd=<81C?9h4H26;?!2e2;1b>i4?::k1a?6=3`9:6=44i2794?=hj?0;66sm17294?3=83:p(ol5409K71`<@:>37):m:39j6a<722c9i7>5;h12>5<<a:?1<75`b783>>{e9<l1<7;50;2x gd=<81C?9h4H26;?!2e2;1b>i4?::k1a?6=3`9:6=44i2794?=hj?0;66sm12594?2=83:p(ol5439K71`<@:>37):m:59j6a<722c897>5;h`6>5<<gk<1<75rb01;>5<3290;w)lm:508L62a3A9?46*;b;68m7b=831b?84?::ka1?6=3fh=6=44}c306?6=<3:1<v*mb;63?M53n2B8855+4c81?l4c2900e>?50;9j70<722ei:7>5;|`274<72=0;6=u+bc874>N4<o1C?964$5`96>o5l3:17d=>:188m63=831dn;4?::a526=8391<7>t$c`971c<@:>m7E=;8:k04?6=3`>o6=44o`d94?=zj8<m6=4<:183!de2:>n7E=;f:J00==n;90;66g;d;29?jga2900qo?99;290?6=8r.in7;7;I17b>N4<11b?=4?::k02?6=3`h36=44o`d94?=zj8<36=4;:183!de2<20D>:i;I17<>o483:17d=9:188mg>=831dmk4?::a531=83>1<7>t$c`91==O;=l0D>:7;h13>5<<a:<1<75fb983>>ifn3:17pl>6783>1<729q/no4:8:J00c=O;=20e>>50;9j73<722ci47>5;nce>5<<uk;=97>54;294~"ej3?37E=;f:J00==n;90;66g<6;29?ld?2900clh50;9~f413290?6=4?{%`a>16<@:>m7E=;8:&7f?4<a;n1<75f3083>>o4=3:17bl9:188yg70;3:187>50z&af?273A9?j6F<499'0g<53`8o6=44i2394?=n;<0;66am6;29?xd6?>0;684?:1y'fg<3;2B88k5G35:8 1d=<2c9h7>5;h0f>5<<a:?1<75fb483>>ie>3:17pl>a583>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6i:0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>a083>0<729q/no4;3:J00c=O;=20(9l54:k1`?6=3`8n6=44i2794?=nj<0;66am6;29?xd6i90;684?:1y'fg<3;2B88k5G35:8 1d=<2c9h7>5;h0f>5<<a:?1<75fb483>>ie>3:17pl>a383>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6ij0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>a`83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6ik0;684?:1y'fg<3;2B88k5G35:8 1d=<2c9h7>5;h0f>5<<a:?1<75fb483>>ie>3:17pl>ae83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6il0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>b783>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6j=0;684?:1y'fg<3;2B88k5G35:8 1d=<2c9h7>5;h0f>5<<a:?1<75fb483>>ie>3:17pl>b483>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6j>0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>b983>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6k;0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>c083>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6k90;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>bg83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6jl0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=e483>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5m?0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=f083>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5nj0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl<0283>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd48=0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl<0483>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd48?0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl<0683>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd4810;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=e683>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5m10;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=e883>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5mh0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=ec83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5mj0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=ee83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5ml0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=eg83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5n90;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=f383>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5n:0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=f583>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5n<0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=f783>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5n>0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=f983>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5n00;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=f`83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5nk0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=fe83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5nl0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=fg83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd4890;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl<0083>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd48;0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=0e83>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th9=54?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd5::0;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`101<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=2d83>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th9?44?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd5<o0;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`116<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=5583>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th9<h4?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd5980;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`14c<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=1183>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th9=?4?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd59:0;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`151<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=1483>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th9=44?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd59?0;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`152<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=1`83>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th9=o4?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd59j0;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`15a<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=2183>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th9=h4?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd59o0;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`164<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=2383>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th9>94?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd5:<0;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`16=<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=2783>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th9>:4?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd5:00;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`16d<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=2c83>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th9>n4?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd5;90;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`16a<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=2g83>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th9?<4?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd5;;0;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`176<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=3583>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th9?:4?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd5;<0;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`173<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=3c83>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th9?54?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd5;h0;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`17`<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=3b83>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th9?i4?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd5;o0;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`105<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=4083>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th98?4?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd5<?0;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`106<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=4483>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th98:4?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd5<10;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`10<<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=4`83>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th98i4?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd5<k0;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`10f<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=4d83>a<729q/no4m7:J00c=O;=20e?;50;9j63<722c9;7>5;h0;>5<<a:?1<75f3983>>o413:17d=n:188m6d=831b?9l50;9j71e=831dnl4?::m03?6=3th99=4?:e83>5}#jk0i;6F<4g9K71><a;?1<75f2783>>o5?3:17d<7:188m63=831b?54?::k0=?6=3`9j6=44i2`94?=n;=h1<75f35a94?=hjh0;66a<7;29?xd5=80;6i4?:1y'fg<e?2B88k5G35:8m73=831b>;4?::k13?6=3`836=44i2794?=n;10;66g<9;29?l5f2900e>l50;9j71d=831b?9m50;9lfd<722e8;7>5;|`117<72m0;6=u+bc8a3>N4<o1C?964i3794?=n:?0;66g=7;29?l4?2900e>;50;9j7=<722c857>5;h1b>5<<a:h1<75f35`94?=n;=i1<75`b`83>>i4?3:17pl=0483>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd58=0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=0283>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd58;0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=0083>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5890;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>fd83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6nm0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>fb83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6nk0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>f`83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6n00;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>f983>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6n>0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>f783>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6n<0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>f283>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6n;0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>f083>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6n90;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>eg83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6ml0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>ee83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6mj0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>ec83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6mh0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=0c83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd58h0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=0883>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd5810;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl=0683>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd58?0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>fg83>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6n=0;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>e883>0<729q/no4;1:J00c=O;=20(9l52:k1`?6=3`8n6=44i2394?=n;<0;66am6;29?xd6m10;684?:1y'fg<392B88k5G35:8 1d=:2c9h7>5;h0f>5<<a:;1<75f3483>>ie>3:17pl>8783>1<729q/no4;2:J00c=O;=20(9l54:k1`?6=3`9>6=44ic794?=hj?0;66sm19594?2=83:p(ol5439K71`<@:>37):m:59j6a<722c897>5;h`6>5<<gk<1<75rb05e>5<2290;w)lm:518L62a3A9?46*;b;68m7b=831b>h4?::k01?6=3`h>6=44oc494?=zj:>96=4<:183!de2<;0D>:i;I17<>"3j3i0e9950;9j0=<722ejj7>5;|`071<72:0;6=u+bc865>N4<o1C?964$5`9g>o3?3:17d:7:188kd`=831vn<><:180>5<7s-hi68?4H26e?M5302.?n7?7;h64>5<<a=21<75`ag83>>{eko0;6>4?:1y'fg<292B88k5G35:8 1d=911b8:4?::k7<?6=3fkm6=44}c3:1?6=;3:1<v*mb;72?M53n2B8855+4c82<>o3?3:17d:7:188kd`=831vn<:n:180>5<7s-hi68?4H26e?M5302.?n7?7;h64>5<<a=21<75`ag83>>{ek:0;6>4?:1y'fg<292B88k5G35:8 1d=911b8:4?::k7<?6=3fkm6=44}ca1>5<4290;w)lm:438L62a3A9?46*;b;3;?l202900e9650;9lec<722wio<4?:283>5}#jk0>=6F<4g9K71><,=h1=55f4683>>o303:17boi:188yge729086=4?{%`a>07<@:>m7E=;8:&7f?7?3`><6=44i5:94?=hio0;66smbg83>6<729q/no4:1:J00c=O;=20(9l5199j02<722c?47>5;nce>5<<ukhn6=4<:183!de2<;0D>:i;I17<>"3j3;37d:8:188m1>=831dmk4?::afa<72:0;6=u+bc865>N4<o1C?964$5`95==n<>0;66g;8;29?jga2900qoll:180>5<7s-hi68?4H26e?M5302.?n7?7;h64>5<<a=21<75`ag83>>{e9>31<7:50;2x gd==:1C?9h4H26;?!2e2:1b8:4?::k7<?6=3`>26=44o`d94?=zj89=6=4;:183!de2<90D>:i;I17<>"3j39n7d:8:188m1>=831b844?::mbb?6=3th:<84?:583>5}#jk0>?6F<4g9K71><,=h1>95f4683>>o303:17d:6:188kd`=831vni?50;694?6|,kh19>5G35d8L62?3->i6?:4i5594?=n<10;66g;9;29?jga2900qo?66;290?6=8r.in7;<;I17b>N4<11/8o4>a:k73?6=3`>36=44i5;94?=hio0;66sm15`94?2=83:p(ol5529K71`<@:>37):m:0c8m11=831b854?::k7=?6=3fkm6=44}c300?6==3:1<v*mb;76?M53n2B8855+4c8g?l202900e9650;9j0<<722c?m7>5;nce>5<<uk;;;7>55;294~"ej3?>7E=;f:J00==#<k0:56g;7;29?l2?2900e9750;9j0d<722ejj7>5;|`g7?6==3:1<v*mb;76?M53n2B8855+4c82=>o3?3:17d:7:188m1?=831b8l4?::mbb?6=3th:?l4?:483>5}#jk0>96F<4g9K71><,=h1=k5f4683>>o303:17d:6:188m1g=831dmk4?::a5=3=8391<7>t$c`914=O;=l0D>:7;%6a>63<a==1<75f4983>>ifn3:17pl>2d83>1<729q/no4:3:J00c=O;=20(9l5269j02<722c?47>5;h6:>5<<ghl1<75rb02;>5<2290;w)lm:478L62a3A9?46*;b;3:?l202900e9650;9j0<<722c?m7>5;nce>5<<ukn?6=4::183!de2<?0D>:i;I17<>"3j3;27d:8:188m1>=831b844?::k7e?6=3fkm6=44}c11g?6=<3:1<v*mb;70?M53n2B8855+4c80g>o3?3:17d:7:188m1?=831dmk4?::a77d=83>1<7>t$c`916=O;=l0D>:7;%6a>6e<a==1<75f4983>>o313:17boi:188yg55i3:187>50z&af?343A9?j6F<499'0g<4k2c?;7>5;h6;>5<<a=31<75`ag83>>{e;;31<7:50;2x gd==:1C?9h4H26;?!2e2:i0e9950;9j0=<722c?57>5;nce>5<<uk9947>54;294~"ej3?87E=;f:J00==#<k08o6g;7;29?l2?2900e9750;9lec<722wi??950;694?6|,kh19>5G35d8L62?3->i6>m4i5594?=n<10;66g;9;29?jga2900qo==6;290?6=8r.in7;<;I17b>N4<11/8o4<c:k73?6=3`>36=44i5;94?=hio0;66sm33794?2=83:p(ol5529K71`<@:>37):m:2a8m11=831b854?::k7=?6=3fkm6=44}c110?6=<3:1<v*mb;70?M53n2B8855+4c80g>o3?3:17d:7:188m1?=831dmk4?::a775=83>1<7>t$c`916=O;=l0D>:7;%6a>6e<a==1<75f4983>>o313:17boi:188yg55:3:187>50z&af?343A9?j6F<499'0g<4k2c?;7>5;h6;>5<<a=31<75`ag83>>{e;;;1<7:50;2x gd==:1C?9h4H26;?!2e2:i0e9950;9j0=<722c?57>5;nce>5<<uk99<7>54;294~"ej3?87E=;f:J00==#<k08o6g;7;29?l2?2900e9750;9lec<722wi?<h50;694?6|,kh19>5G35d8L62?3->i6>m4i5594?=n<10;66g;9;29?jga2900qo=>e;290?6=8r.in7;<;I17b>N4<11/8o4<c:k73?6=3`>36=44i5;94?=hio0;66sm30f94?2=83:p(ol5529K71`<@:>37):m:2a8m11=831b854?::k7=?6=3fkm6=44}c12g?6=<3:1<v*mb;70?M53n2B8855+4c80g>o3?3:17d:7:188m1?=831dmk4?::a74d=83>1<7>t$c`916=O;=l0D>:7;%6a>6e<a==1<75f4983>>o313:17boi:188yg56i3:187>50z&af?343A9?j6F<499'0g<4k2c?;7>5;h6;>5<<a=31<75`ag83>>{e;831<7:50;2x gd==:1C?9h4H26;?!2e2:i0e9950;9j0=<722c?57>5;nce>5<<uk9:47>54;294~"ej3?87E=;f:J00==#<k08o6g;7;29?l2?2900e9750;9lec<722wi?<950;694?6|,kh19>5G35d8L62?3->i6>m4i5594?=n<10;66g;9;29?jga2900qo=>6;290?6=8r.in7;<;I17b>N4<11/8o4<c:k73?6=3`>36=44i5;94?=hio0;66sm30794?2=83:p(ol5529K71`<@:>37):m:2a8m11=831b854?::k7=?6=3fkm6=44}c120?6=<3:1<v*mb;70?M53n2B8855+4c80g>o3?3:17d:7:188m1?=831dmk4?::a745=83>1<7>t$c`916=O;=l0D>:7;%6a>6e<a==1<75f4983>>o313:17boi:188yg56:3:187>50z&af?343A9?j6F<499'0g<4k2c?;7>5;h6;>5<<a=31<75`ag83>>{e;8;1<7:50;2x gd==:1C?9h4H26;?!2e2:i0e9950;9j0=<722c?57>5;nce>5<<uk9:<7>54;294~"ej3?87E=;f:J00==#<k08o6g;7;29?l2?2900e9750;9lec<722wi?=h50;694?6|,kh19>5G35d8L62?3->i6>m4i5594?=n<10;66g;9;29?jga2900qo=?e;290?6=8r.in7;<;I17b>N4<11/8o4<c:k73?6=3`>36=44i5;94?=hio0;66sm31f94?2=83:p(ol5529K71`<@:>37):m:2a8m11=831b854?::k7=?6=3fkm6=44}c13g?6=<3:1<v*mb;70?M53n2B8855+4c80g>o3?3:17d:7:188m1?=831dmk4?::a75d=83>1<7>t$c`916=O;=l0D>:7;%6a>6e<a==1<75f4983>>o313:17boi:188yg5713:187>50z&af?343A9?j6F<499'0g<4k2c?;7>5;h6;>5<<a=31<75`ag83>>{e;9k1<7:50;2x gd==:1C?9h4H26;?!2e2:i0e9950;9j0=<722c?57>5;nce>5<<uk;257>54;294~"ej3?87E=;f:J00==#<k0956g;7;29?l2?2900e9750;9lec<722wi=9k50;694?6|,kh19>5G35d8L62?3->i6?74i5594?=n<10;66g;9;29?jga2900qo?=c;291?6=8r.in7;:;I17b>N4<11/8o47;h64>5<<a=21<75f4883>>o3i3:17boi:188yg7393:197>50z&af?323A9?j6F<499'0g<6l2c?;7>5;h6;>5<<a=31<75f4`83>>ifn3:17pl>4383>0<729q/no4:5:J00c=O;=20(9l51d9j02<722c?47>5;h6:>5<<a=k1<75`ag83>>{e9:n1<7;50;2x gd==<1C?9h4H26;?!2e2;90e9950;9j0=<722c?57>5;h6b>5<<ghl1<75rb063>5<2290;w)lm:478L62a3A9?46*;b;1g?l202900e9650;9j0<<722c?m7>5;nce>5<<uk;3h7>53;294~"ej3?:7E=;f:J00==#<k0<7d:8:188m1>=831dmk4?::a5=4=83?1<7>t$c`910=O;=l0D>:7;%6a>75<a==1<75f4983>>o313:17d:n:188kd`=831vn<6<:186>5<7s-hi68;4H26e?M5302.?n7<<;h64>5<<a=21<75f4883>>o3i3:17boi:188yg7?93:197>50z&af?323A9?j6F<499'0g<b3`><6=44i5:94?=n<00;66g;a;29?jga2900qo?8b;291?6=8r.in7;:;I17b>N4<11/8o4>e:k73?6=3`>36=44i5;94?=n<h0;66anf;29?xd60h0;684?:1y'fg<2=2B88k5G35:8 1d=::1b8:4?::k7<?6=3`>26=44i5c94?=hio0;66sm19`94?3=83:p(ol5549K71`<@:>37):m:318m11=831b854?::k7=?6=3`>j6=44o`d94?=zj8226=4::183!de2<?0D>:i;I17<>"3j3o0e9950;9j0=<722c?57>5;h6b>5<<ghl1<75rb04b>5<4290;w)lm:438L62a3A9?46*;b;03?l202900e9650;9lec<722wi=;l50;194?6|,kh19<5G35d8L62?3->i6?>4i5594?=n<10;66anf;29?xd6>j0;6>4?:1y'fg<292B88k5G35:8 1d=:91b8:4?::k7<?6=3fkm6=44}c35`?6=;3:1<v*mb;72?M53n2B8855+4c814>o3?3:17d:7:188kd`=831vn<=i:186>5<7s-hi68;4H26e?M5302.?n7<=;h64>5<<a=21<75f4883>>o3i3:17boi:188yg70l3:197>50z&af?323A9?j6F<499'0g<5:2c?;7>5;h6;>5<<a=31<75f4`83>>ifn3:17pl>6d83>6<729q/no4:1:J00c=O;=20(9l5219j02<722c?47>5;nce>5<<uk99h7>54;294~"ej3?87E=;f:J00==#<k0=7d:8:188m1>=831b844?::mbb?6=3th8>h4?:583>5}#jk0>?6F<4g9K71><,=h1?6g;7;29?l2?2900e9750;9lec<722wi=4650;794?6|,kh1985G35d8L62?3->i6<l4i5594?=n<10;66g;9;29?l2f2900clh50;9~f42c290>6=4?{%`a>03<@:>m7E=;8:&7f?7e3`><6=44i5:94?=n<00;66g;a;29?jga2900qo?=d;291?6=8r.in7;:;I17b>N4<11/8o47;h64>5<<a=21<75f4883>>o3i3:17boi:188yg7?m3:1?7>50z&af?363A9?j6F<499'0g<03`><6=44i5:94?=hio0;66sm18694?4=83:p(ol54b9K71`<@:>37d:9:188kd`=831vn<:6:181>5<7s-hi69m4H26e?M5302c?:7>5;nce>5<<uk;;57>53;294~"ej3?97E=;f:J00==#<k0:46g;7;29?l2?2900c9k50;9~fa3=8391<7>t$c`917=O;=l0D>:7;%6a>4><a==1<75f4983>>i3m3:17pl>9683>1<729q/no4:4:J00c=O;=20(9l51b9j02<722c?47>5;h6:>5<<g=o1<75rb06`>5<3290;w)lm:468L62a3A9?46*;b;3`?l202900e9650;9j0<<722e?i7>5;|`27`<72<0;6=u+bc862>N4<o1C?964$5`95a=n<>0;66g;8;29?l2>2900e9o50;9l0`<722wi=:m50;794?6|,kh19;5G35d8L62?3->i6<k4i5594?=n<10;66g;9;29?l2f2900c9k50;9~f4>3290>6=4?{%`a>00<@:>m7E=;8:&7f?453`><6=44i5:94?=n<00;66g;a;29?j2b2900qo?7c;291?6=8r.in7;9;I17b>N4<11/8o4=2:k73?6=3`>36=44i5;94?=n<h0;66a;e;29?xd6<:0;694?:1y'fg<2<2B88k5G35:8 1d=:81b8:4?::k7<?6=3`>26=44o5g94?=z{=9;6=48{_604>;6;?0?463>35873>;6;h0?m63>2d87=>;6:j0?;63>2e873>{t<;o1<7<>{_156>X3;11U8>84^274?[24;2T?<<5Q4258Z1653W9=<6P<5g9]70c<V:?o7S=:c:\77`=Y<:n0R9=l;_60f>X3;h1U8?j4^50`?[25j2T?>l5Q43;896372=>01>=j:27896572:?01>=m:278965f2:?01>=6:278965?2:?01>:9:27896222:?01<8::c:8yv70n3:1>vP<599>52`=j?1v9==:184[24:278>k4<1:?07a<e=278?n4m5:?07`<e=278?=4m5:?07g<e=2wx=>650;0xZ6`134;847l9;|q705<72<qU89>4=0:g>11<5:8o6974=20f>11<582n6994}r61<?6=?;qU8?64=01a>7b<5:996?j4=212>7b<5:9;6?j4=21b>7b<5:926?j4=21;>7b<58::6?j4=023>7b<5ol1>i52fd81`>;al38o70?=7;0g?875>38o70?=5;0g?875<38o70?=3;0g?876l38o70?>c;0g?876j38o70?>a;0g?876138o70ji:3f89ac=:m16hi4=d:?gg?4c34ni6?j4=07:>7b<58?36?j4=075>7b<58?>6?j4=074>7b<58<86?j4=041>7b<58<:6?j4=043>7b<58?m6?j4=014>7b<58936?j4=011>7b<589:6?j4=3g6>7b<5;o=6?j4=3d2>7b<5;lh6?j4=220>7b<5::?6?j4=226>7b<5::=6?j4=224>7b<5::36?j4=3g4>7b<5;o36?j4=3g:>7b<5;oj6?j4=3ga>7b<5;oh6?j4=3gg>7b<5;on6?j4=3ge>7b<5;l;6?j4=3d1>7b<5;l86?j4=3d7>7b<5;l>6?j4=3d5>7b<5;l<6?j4=3d;>7b<5;l26?j4=3db>7b<5;li6?j4=3dg>7b<5;ln6?j4=3de>7b<5::;6?j4=222>7b<5::96?j4=326>7b<5;:?6?j4=320>7b<5;:96?j4=322>7b<5;:;6?j4=0df>7b<58lo6?j4=0d`>7b<58li6?j4=0db>7b<58l26?j4=0d;>7b<58l<6?j4=0d5>7b<58l>6?j4=0d0>7b<58l96?j4=0d2>7b<58l;6?j4=0ge>7b<58on6?j4=0gg>7b<58oh6?j4=0ga>7b<58oj6?j4=32a>7b<5;:j6?j4=32:>7b<5;:36?j4=324>7b<5;:=6?j4=0de>7b<58l?6?j4=0g:>7b<58o36?j4}r3;3?6=:rT8jn521959f3=z{=926=470z\77<=:;;l1>i5232f96a=:;=:1>i5232a96a=:;:o1>i5232d96a=:;:h1>i5235496a=:;=?1>i52ce81`>;dk38o70mm:3f89fg=:m16o44=d:?e7?4c34l96?j4=g396a=:n909h63jf;0g?8c>2;n01h652e9>a2<5l27n:7<k;<g6>7b<58;86?j4=031>7b<58;:6?j4=033>7b<58:m6?j4=057>7b<58=86?j4=054>7b<58k?6?j4=0c0>7b<58k:6?j4=0c3>7b<58k96?j4=0c`>7b<58kj6?j4=0ca>7b<58ko6?j4=0cf>7b<58h=6?j4=0`7>7b<58h>6?j4=0`4>7b<58h36?j4=0a1>7b<58i:6?j4=0a3>7b<58hm6?j4=0`f>7b<5;:o6>:m;<02<?53j279>>4<4c9>612=;=h01?<j:26a?844139?n63=4g800g=::<91?9l4=377>62e348;i7=;b:?154<4<k16>=h535`897772:>i70<>2;17f>;59:088o52206971d<5;;>6>:m;<02=?53j279=;4<4c9>641=;=h01??n:26a?846j39?n63=1b800g=::8n1?9l4=303>62e348:i7=;b:?15c<4<k16>??535`897452:>i70<=4;17f>;5:<088o5223:971d<5;8=6>:m;<013?53j279>44<4c9>67g=;=h01?<m:26a?845k39?n63=31800g=::;n1?9l4=30e>62e3488=7=;b:?177<4<k16>>=535`897532:>i70<<7;17f>;5;<088o52224971d<5;9i6>:m;<00<?53j279?l4<4c9>66c=;=h01?=l:26a?844l39?n63=3g800g=::=:1?9l4=362>62e348?>7=;b:?103<4<k16>9=535`897222:>i70<;7;17f>;5<1088o5225;971d<5;>j6>:m;<07`?53j2798o4<4c9>61e=;=h01?:j:26a?842839?n63=50800g=::<81?9l4=0:5>7b<582<6?j4=05e>7b<uz;<;7>52z\750=:9>=1n;5rs0g3>5<5sW9h563=048a2>{t9ml1<7<t^2a;?847<3h=7p}>dd83>7}Y;j=01?><:c48yv7cl3:1>vP<c79>654=j?1v<jl:181[5d=279<<4m6:p5ad=838pR>m;;<034?d13ty:h44?:3y]7f4<58ln6o84}r3g<?6=:rT8o<521gf9f3=z{8n<6=4={_1`4>;6nj0i:6s|1e494?4|V:hm70?ib;`5?xu6l<0;6?uQ3cg894`f2k<0q~?k4;296~X4jm16=k75b79~w4b42909wS=mc:?2b=<e>2wx=i<50;0xZ6de34;m;7l9;|q2`4<72;qU?oo4=0d5>g0<uz;o<7>52z\0f<=:9o?1n;5rs0af>5<5sW9i;63>f28a2>{t9jn1<7<t^2`5?87a:3h=7p}>cb83>7}Y;k?01<h>:c48yv7dj3:1>vP<b59>5c6=j?1v<mn:181[5e;27:ik4m6:p5f?=838pR>l=;<3fa?d13ty:o54?:3y]7g7<58oo6o84}r3`3?6=:rT8n=521da9f3=z{8i=6=4={_1bb>;6mk0i:6s|1b794?4|V:kn70?ja;`5?xu6m>0;6?uQ3bd8976e2k<0q~?j6;296~X4kl16>=o5b79~w4c22909wS=ld:?14<<e>2wx=h:50;0xZ6ed348;47l9;|q2a6<72;qU?nl4=324>g0<uz;n>7>52z\0gd=::9<1n;5rs0g2>5<5sW9h?63>fg8a2>{t9mk1<7<t^2`;?87a<3h=7p}>cg83>7}Y;hn01<k6:c48yv7d<3:1>vP<ab9>5`>=j?1v>o;:180[5?82799<4<5:?117<4=2wx?l<50;1xZ61a348?i7=:;<064?523ty8m<4?:2y]72c<5;>o6>;4=36`>63<uz9j<7>53z\03a=::=k1?85225`970=z{:3m6=4<{_14g>;5<108963=48801>{t;0o1<7=t^25a?843>39>70<;7;16?xu41j0;6>uQ36;897242:?01?:::278yv5>j3:1?vP<799>617=;<16>9<5349~w6?f2908wS=87:?17c<4=2798=4<5:p7<?=839pR>99;<00a?523488h7=:;|q0==<72:qU?:;4=31a>63<5;9h6>;4}r1:3?6=;rT8;95222:970=:::k1?85rs2;5>5<4sW9<?63=36801>;5;?0896s|38794?5|V:=970<<4;16?844=39>7p}<9583>6}Y;>;01?==:27897542:?0q~=63;297~X4?916>>>5349>667=;<1v>7>:180[51m279>i4<5:?16c<4=2wx?4>50;1xZ60c3489n7=:;<01g?523ty84k4?:2y]73e<5;826>;4=30b>63<uz93i7>53z\02g=::;21?852235970=z{:2o6=4<{_15e>;5:<08963=27801>{t;1i1<7=t^24:?845:39>70<=4;16?xu40k0;6>uQ37:897472:?01?<>:278yv5?i3:1?vP<669>64c=;<16><h5349~w6>>2908wS=96:?15f<4=279=i4<5:p7=>=839pR>8:;<02e?52348:n7=:;|q0eg<72:qU?584=33:>63<5;;<6>;4}r1be?6=;rT84852207970=::8<1?85rs2c:>5<4sW93863=12801>;59=0896s|3`:94?5|V:2870<>1;16?846:39>7p}<a683>6}Y;1801?>i:27897772:?0q~=n6;297~X40816>8:5349>65c=;<1v>o::180[50i2798k4<5:?116<4=2wx?4j50;1xZ60a348?87=:;<00=?523ty85?4?:2y]732<5;886>;4=30f>63<uz93;7>53z\026=::9n1?85220:970=z{<h1<7<t=272>g7<58<>6>>4}r30g?6=:r7:?o4<5:?205<fn2wx?>950;33874j3h>70=<a;`5?872139:70?:8;12?872>39:70?:5;`6?872?39:70?93;12?871:39:70?91;12?871839:70?:f;12?874?3h>70?<8;`6?874:39:70?<1;12?xu6;k0;69u212`9f3=:9:>18l5213a90==:9;n1855rs21g>5<5s499j7=:;<10`?d13ty8>k4?:4y>77`=j?16=:75489>5=3=<116=5?5469>5=?=<>1v>=l:185854l39>70=<c;`5?870?3h>70?76;`6?87??3h>70?8f;`6?xu4;80;6>u2320970=:;:;1n;5232296`=z{:996=4={<106?d1349887:8;|q07c<72:q6?9>5349>76c=:l16?>h5b79~w6272909w0=;0;`5?853:3><7p}<3c83>7}:;:i1?85232`9f3=z{:9;6=4<{<105?523498<7l9;<100?2?3ty8?h4?:2y>76c=j?16?>h5349>714=<11v>=<:187854i3h>70=<9;`6?85403h>70=<4;ce?xu4;?0;6<;t=21:>g0<58::6>?4=023>67<5ol1?<52fd805>;al39:70?=7;12?875>39:70?=5;12?875<39:70?=3;12?876l39:70?>c;12?876j39:70?>a;12?876139:70ji:2389ac=;816hi4<1:?gg?5634ni6>?4}r101?6=<0q6?>65b79>6`3=;816>h85309>6c7=;816>km5309>755=;816?=:5309>753=;816?=85309>751=;816?=65309>6`1=;816>h65309>6`?=;816>ho5309>6`d=;816>hm5309>6`b=;816>hk5309>6``=;816>k>5309>6c4=;816>k=5309>6c2=;816>k;5309>6c0=;816>k95309>6c>=;816>k75309>6cg=;816>kl5309>6cb=;816>kk5309>6c`=;816?=>5309>757=;816?=<5309>653=;816>=:5309>655=;816>=<5309>657=;816>=>5309>5cc=;816=kj5309>5ce=;816=kl5309>5cg=;816=k75309>5c>=;816=k95309>5c0=;816=k;5309>5c5=;816=k<5309>5c7=;816=k>5309>5``=;816=hk5309>5`b=;816=hm5309>5`d=;816=ho5309>65d=;816>=o5309>65?=;816>=65309>651=;816>=85309>5c`=;816=k:5309>5`?=;816=h65309~w6262908w0=;6;`6?853=3h>70=;2;ce?xu4<=0;6<9t=265>g0<58=?6>?4=050>67<58k?6>?4=0c0>67<58k:6o;4=0c3>g3<58k96>?4=0c`>67<58kj6>?4=0ca>g3<58ko6>?4=0cf>67<58h=6>?4=0`7>g3<58h>6>?4=0`4>67<58h36>?4=0a1>67<58i:6>?4=0a3>67<58hm6>?4=0`f>67<uz9??7>514y>713=j?16oi4<1:?`g?5634ii6>?4=bc974=:k008=63i3;12?8`52:;01k?5309>b5<4927nj7=>;<g:>67<5l21?<52e6805>;b>39:70k::23894742:;01<?=:23894762:;01<??:238946a2:;0q~kj:1858ec2:?01k=5b79>gc<3027o=7:8;<f0>1?<5m>1845rsb:94?3|5jn1n;52190902=:9>h18l5219c902=:9?o1855rsbg94?4|5ji1?852cg8bb>{tk>0;68u2cb8a2>;60;0?563>8c873>;6>m0?463>7b87e>{tl90;6?u2cc801>;c93km7p}l6;291~;dj3h=70?73;64?87?j3>270?9c;6;?870k3>27p}k2;296~;di39>70j<:`d8yve2290>w0mn:c4894>42=301<9m:5;894>f2=301<8m:5:8yvb32909w0m6:2789a2=io1vn:50;7x9f?=j?16=;o5499>52b=<116=5:5469>5=e=<11v<<=:185877939>70?=7;`5?877;3>370??5;64?877?3>270??8;6:?xuak3:1?v3>008a2>;6<80?463>3e87<>{t9981<7<t=023>63<58:86lh4}rda>5<4s4;;<7l9;<376?2?34;8h7:n;|q241<72;q6jk4<5:?240<fn2wxjl4?:2y>bc<e>27:8?4;7:?27`<302wx==850;0x9cc=;<16==95ag9~wc?=839p1kk5b79>517=<>16=>k5469~w46?2909w0hk:278946?2hl0q~h7:1808`c2k<01<=i:55894242==0q~?>8;296~;6:>08963>1e8a2>{t98=1<7<t=005>63<58;h6o84}r315?6==r7:>;4m6:?246<3?27:<84;8:?242<3i27:<44;7:p540=838p1<<::278947e2k<0q~?=0;290~;6:<0i:63>0487=>;68>0?;63>0887<>{t98?1<7<t=007>63<58;j6o84}r32b?6=;r7:>94m6:?242<3027:<54;7:p542=838p1<<<:278947>2k<0q~?>e;296~;6::0i:63>0987<>{tm=0;6?u2f2801>;b13h=7p}j3;296~;a:39>70k7:c48yvcc290>w0h=:c489f`=<>16h<4;8:?g7?2f34n>6994}rg1>5<5s4l:6>;4=d59f3=z{li1<7:t=g39f3=:l80?563k3;64?8b22=20q~k>:1818`72:?01h85b79~w`d=839p1k>5b79>`6<3027o87:8;|qf4?6=:r7nj7=:;<g6>g0<uzoj6=4={<ge>g0<5m>1855rs02f>5<5s4;:h7=:;<327?d13ty:<i4?:3y>54e=;<16=<<5b79~w46d2909w0?>b;16?87693h=7p}>0c83>7}:98k1?8521029f3=z{8:j6=4={<32=?5234;;j7l9;|qge?6=:r7n57=:;<fe>g0<uzn26=4={<g;>63<5mo1n;5rse:94?4|5l=1?852de8a2>{tl>0;6?u2e7801>;ck3h=7p}k6;296~;b=39>70jm:c48yv72m3:1>5u2dg801>;6>:0i:63mc;64?855k3><70==b;64?855i3><70==9;64?85503><70==7;64?855>3><70==5;64?855<3><70==3;64?855:3><70==1;64?85583><70=>f;64?856m3><70=>d;64?856k3><70=>b;64?856i3><70=>9;64?85603><70=>7;64?856>3><70=>5;64?856<3><70=>3;64?856:3><70=>1;64?85683><70=?f;64?857m3><70=?d;64?857k3><70=?b;64?85713><70=?a;64?87393>27p}i4;296~;cm39>70ll:`d8yv`22909w0jk:2789gb=io1vk850;0x9ae=;<16nh4nf:pb2<72;q6ho4<5:?ab?ga3ty:ni4?:4y>545=;<16=n<5b79>g5<3?278>i4;8:?06`<302wx=?650;0x94752:?01n>5ag9~w44>2909w0?>1;16?8e62hl0q~?=a;296~;69908963l2;ce?xu6:k0;6?u211d970=:k:0jj6s|13a94?4as4;>57<j;<36<?4b34;>:7<j;<361?4b34;>;7<j;<357?4b34;=>7<j;<355?4b34;=<7<j;<36b?4b348n97<j;<0f2?4b348m=7<j;<0eg?4b349;?7<j;<130?4b349;97<j;<132?4b349;;7<j;<13<?4b348n;7<j;<0f<?4b348n57<j;<0fe?4b348nn7<j;<0fg?4b348nh7<j;<0fa?4b348nj7<j;<0e4?4b348m>7<j;<0e7?4b348m87<j;<0e1?4b348m:7<j;<0e3?4b348m47<j;<0e=?4b348mm7<j;<0ef?4b348mh7<j;<0ea?4b348mj7<j;<134?4b349;=7<j;<136?4b34;9h7oi;|q20=<72;q6=875349>51c=io1v<;;:18787213h=70?93;16?873m3><70?<d;64?xu6<>0;6?u214:970=:9=n1mk5rs070>5<2s4;>47l9;<356?5234;?i7:7;<30`?2>34;?h7:8;|q200<72;q6=885349>51g=io1v<;>:184872>3h=70?90;16?873i3>370?;b;6:?873l3>270?;c;6;?874m3>j7p}>4583>7}:9<?1?85215;9ec=z{8?;6=47{<361?d134;>j7=:;<37e?2034;?n7:7;<30b?2?34;?h7:7;<37=?2134;?o7:8;|q203<72;q6=895349>51d=io1v<;=:185872?3h=70?91;16?873j3><70?;d;6b?873k3>270?<e;6:?xu6=m0;69mt=041>g0<5;:o6>l4=33;>6d<5;886>l4=367>6d<5;8n6>l4=31:>6d<5;>m6>l4=370>6d<5;??6>l4=32f>6d<5;;:6>l4=32e>6d<5;;;6>l4=331>6d<5;;86>l4=337>6d<5;;>6>l4=33:>6d<5;;=6>l4=334>6d<5;;j6>l4=33a>6d<5;;h6>l4=33g>6d<5;8;6>l4=33f>6d<5;;m6>l4=302>6d<5;896>l4=307>6d<5;8>6>l4=30;>6d<5;8=6>l4=304>6d<5;826>l4=30b>6d<5;8i6>l4=30`>6d<5;9;6>l4=30g>6d<5;8m6>l4=312>6d<5;996>l4=310>6d<5;9?6>l4=314>6d<5;9>6>l4=315>6d<5;9i6>l4=31;>6d<5;9j6>l4=31f>6d<5;9h6>l4=31g>6d<5;9m6>l4=363>6d<5;>:6>l4=361>6d<5;>=6>l4=360>6d<5;>>6>l4=364>6d<5;>36>l4=36:>6d<5;>j6>l4=36g>6d<5;>i6>l4=36`>6d<5;>n6>l4=373>6d<5;?:6>l4=371>6d<5kn18:52bb87<>;6<;0?m6s|14a94?2ds4;==7l9;<03`?5f348:47=n;<017?5f348?87=n;<01a?5f348857=n;<07b?5f348>?7=n;<060?5f348;i7=n;<025?5f348;j7=n;<024?5f348:>7=n;<027?5f348:87=n;<021?5f348:57=n;<022?5f348:;7=n;<02e?5f348:n7=n;<02g?5f348:h7=n;<014?5f348:i7=n;<02b?5f3489=7=n;<016?5f348987=n;<011?5f348947=n;<012?5f3489;7=n;<01=?5f3489m7=n;<01f?5f3489o7=n;<004?5f3489h7=n;<01b?5f3488=7=n;<006?5f3488?7=n;<000?5f3488;7=n;<001?5f3488:7=n;<00f?5f348847=n;<00e?5f3488i7=n;<00g?5f3488h7=n;<00b?5f348?<7=n;<075?5f348?>7=n;<072?5f348??7=n;<071?5f348?;7=n;<07<?5f348?57=n;<07e?5f348?h7=n;<07f?5f348?o7=n;<07a?5f348><7=n;<065?5f348>>7=n;<`f>11<5kn1855215090<=z{8?i6=4;cz?225<e>279<i4<9:?15=<41279>>4<9:?101<41279>h4<9:?17<<412798k4<9:?116<41279994<9:?14`<41279=<4<9:?14c<41279==4<9:?157<41279=>4<9:?151<41279=84<9:?15<<41279=;4<9:?152<41279=l4<9:?15g<41279=n4<9:?15a<41279>=4<9:?15`<41279=k4<9:?164<41279>?4<9:?161<41279>84<9:?16=<41279>;4<9:?162<41279>44<9:?16d<41279>o4<9:?16f<41279?=4<9:?16a<41279>k4<9:?174<41279??4<9:?176<41279?94<9:?172<41279?84<9:?173<41279?o4<9:?17=<41279?l4<9:?17`<41279?n4<9:?17a<41279?k4<9:?105<412798<4<9:?107<412798;4<9:?106<41279884<9:?102<41279854<9:?10<<412798l4<9:?10a<412798o4<9:?10f<412798h4<9:?115<412799<4<9:?117<4127ij7:8;<`f>1><58>:69o4}r36e?6=<kq6=8h5b79>65b=;116><65399>675=;116>9:5399>67c=;116>>75399>61`=;116>8=5399>602=;116>=k5399>647=;116>=h5399>646=;116><<5399>645=;116><:5399>643=;116><75399>640=;116><95399>64g=;116><l5399>64e=;116><j5399>676=;116><k5399>64`=;116>??5399>674=;116>?:5399>673=;116>?65399>670=;116>?95399>67?=;116>?o5399>67d=;116>?m5399>666=;116>?j5399>67`=;116>>?5399>664=;116>>=5399>662=;116>>95399>663=;116>>85399>66d=;116>>65399>66g=;116>>k5399>66e=;116>>j5399>66`=;116>9>5399>617=;116>9<5399>610=;116>9=5399>613=;116>995399>61>=;116>975399>61g=;116>9j5399>61d=;116>9m5399>61c=;116>8>5399>607=;116>8<5399>fc<3027:8>4;8:p56?=839p1<=8:278945?2:?01<=n:`d8yv74?3:1>v3>368a2>;6;h0?;6s|12194?4|58996>;4=017>d`<uz;8<7>57z?277<e>27:?;4;9:?271<3127:?l4;9:?26`<3?27:>n4;9:?26a<312wx=>;50;0x94562:?01<=9:`d8yv75n3:1;v3>308a2>;6;?0?;63>3587<>;6;h0?463>2d87<>;6:j0?m63>2e87e>{t9?31<7<t=053>66<58<26lh4}r35a?6=:r7:;=4;d:?22`<fn2wx=:850;0x94172hl01<9;:278yv7103:1?v3>6g804>;6>008<63>698bb>{t9?n1<7=t=04e>1b<58<26o64=04g>d`<uz;<97>52z?22c<fn27:;>4<5:p5g4=83?p1<86:24894d02k<01<m>:27894>e2=201<8k:558yv71?3:1>v3>69804>;6>>0jj6s|1c394?3|58<36>84=0`5>g0<58i;6>;4=0:a>1g<58<h6994}r35g?6=:r7::54m8:?22f<fn2wx=;850;0x94002::01<89:`d8yv7e83:19v3>66802>;6j<0i:63>bg801>;60h0?m63>6c873>{t9?h1<7<t=044>g><58<i6lh4}r351?6=:r7::;4<0:?220<fn2wx=lh50;7x94012:<01<l;:c4894db2:?01<8n:55894>d2==0q~?9a;296~;6>?0i463>6`8bb>{t91n1<7?8{<351?5134;j87<j;<3b7?4b34;j=7<j;<3b4?4b34;j>7<j;<3bg?4b34;jm7<j;<3bf?4b34;jh7<j;<3ba?4b34;i:7<j;<3a0?4b34;i97<j;<3a3?4b34;i47<j;<3`6?4b34;h=7<j;<3`4?4b34;ij7<j;<3aa?4b34;3i7oi;<3;0?2f3ty:;?4?:3y>522=j?16=:75499~w4162909w0?83;`5?87013><7p}>7`83>6}:9>=1>h5216d96`=:91?1mk5rs05;>5<5s4;<;7=:;<34=?ga3ty:5>4?:3y>5d2=;<16=475ag9~w4?a290?w0?n4;`5?87fm39>70?69;64?87?:3>37p}>9383>7}:9h91?85218:9ec=z{83n6=4:{<3b7?d134;jh7=:;<3:=?2?34;3>7:n;<3:<?203ty:5=4?:3y>5d7=;<16=4;5ag9~w4?d290<w0?n1;`5?87fj39>70?65;64?87>>3>270?73;6b?87>03>270?67;6;?xu60o0;6?u21`2970=:90>1mk5rs0;a>5<?s4;j<7l9;<3be?5234;297:7;<3:2?2?34;247:7;<3:0?2134;2;7:8;<3;0?2?3ty:5<4?:3y>5d4=;<16=485ag9~w4?c290=w0?n2;`5?87fk39>70?66;64?87?;3>370?68;6b?87>?3>27p}>a683>6}:9hi1n;521c4970=:9>i18:5rs0c6>5<4s4;jm7l9;<3a0?5234;<h7:8;|q2e3<72:q6=ll5b79>5g3=;<16=:l5469~w4g?2908w0?nd;`5?87e?39>70?8c;6;?xu6i00;6>u21`g9f3=:9k21?85216`90==z{8h86=4;{<3a<?d134;h>7=:;<3;e?2?34;=i7:8;|q2ff<72=hp1<m>:c48976c2;201??7:3:897442;201?:;:3:8974b2;201?=6:3:8972a2;201?;<:3:897332;201?>j:3:897762;201?>i:3:897772;201??=:3:897742;201??;:3:897722;201??6:3:897712;201??8:3:8977f2;201??m:3:8977d2;201??k:3:897472;201??j:3:8977a2;201?<>:3:897452;201?<;:3:897422;201?<7:3:897412;201?<8:3:8974>2;201?<n:3:8974e2;201?<l:3:897572;201?<k:3:8974a2;201?=>:3:897552;201?=<:3:897532;201?=8:3:897522;201?=9:3:8975e2;201?=7:3:8975f2;201?=j:3:8975d2;201?=k:3:8975a2;201?:?:3:897262;201?:=:3:897212;201?:<:3:897222;201?:8:3:8972?2;201?:6:3:8972f2;201?:k:3:8972e2;201?:l:3:8972b2;201?;?:3:897362;201?;=:3:89f7=<>16o=4;8:p5gd=83>iw0?l0;`5?847l38<70<>8;04?845;38<70<;4;04?845m38<70<<9;04?843n38<70<:3;04?842<38<70<?e;04?846938<70<?f;04?846838<70<>2;04?846;38<70<>4;04?846=38<70<>9;04?846>38<70<>7;04?846i38<70<>b;04?846k38<70<>d;04?845838<70<>e;04?846n38<70<=1;04?845:38<70<=4;04?845=38<70<=8;04?845>38<70<=7;04?845138<70<=a;04?845j38<70<=c;04?844838<70<=d;04?845n38<70<<1;04?844:38<70<<3;04?844<38<70<<7;04?844=38<70<<6;04?844j38<70<<8;04?844i38<70<<e;04?844k38<70<<d;04?844n38<70<;0;04?843938<70<;2;04?843>38<70<;3;04?843=38<70<;7;04?843038<70<;9;04?843i38<70<;d;04?843j38<70<;c;04?843m38<70<:0;04?842938<70<:2;04?8e52==01n?5499~w4df290?nv3>bg8a2>;58m09:63=19812>;5::09:63=45812>;5:l09:63=38812>;5<o09:63=52812>;5==09:63=0d812>;59809:63=0g812>;59909:63=13812>;59:09:63=15812>;59<09:63=18812>;59?09:63=16812>;59h09:63=1c812>;59j09:63=1e812>;5:909:63=1d812>;59o09:63=20812>;5:;09:63=25812>;5:<09:63=29812>;5:?09:63=26812>;5:009:63=2`812>;5:k09:63=2b812>;5;909:63=2e812>;5:o09:63=30812>;5;;09:63=32812>;5;=09:63=36812>;5;<09:63=37812>;5;k09:63=39812>;5;h09:63=3d812>;5;j09:63=3e812>;5;o09:63=41812>;5<809:63=43812>;5<?09:63=42812>;5<<09:63=46812>;5<109:63=48812>;5<h09:63=4e812>;5<k09:63=4b812>;5<l09:63=51812>;5=809:63=53812>;d;3><70m=:5:8yv7e13:18lu21cg9f3=::9n1>85220:960=::;91>852256960=::;o1>85222;960=::=l1>852241960=::<>1>85221g960=::8;1>85221d960=::8:1>852200960=::891>852206960=::8?1>85220;960=::8<1>852205960=::8k1>85220`960=::8i1>85220f960=::;:1>85220g960=::8l1>852233960=::;81>852236960=::;?1>85223:960=::;<1>852235960=::;31>85223c960=::;h1>85223a960=::::1>85223f960=::;l1>852223960=:::81>852221960=:::>1>852225960=:::?1>852224960=:::h1>85222:960=:::k1>85222g960=:::i1>85222f960=:::l1>852252960=::=;1>852250960=::=<1>852251960=::=?1>852255960=::=21>85225;960=::=k1>85225f960=::=h1>85225a960=::=o1>852242960=::<;1>852240960=:k:0?46s|28f94?4|5;o>6>;4=22b>d`<uz8h=7>52z?1a0<e>27:i54<5:p6d>=838p1?k9:278966e2hl0q~<lc;296~;5m?0i:63>e8801>{t:k91<7<t=3d2>63<5:;=6lh4}r0g3?6=:r79j<4m6:?2b1<4=2wx>oo50;0x97`d2:?01><>:`d8yv4cm3:1>v3=fb8a2>;6no0896s|2c`94?4|5::86>;4=204>d`<uz8oj7>52z?046<e>279<;4<5:p6ge=838p1>>;:278964?2hl0q~<j0;296~;48=0i:63=06801>{t:kn1<7<t=226>63<5:826lh4}r0f5?6=:r78<84m6:?14=<4=2wx>ok50;0x96612:?01><n:`d8yv4b:3:1>v3<078a2>;5800896s|2cd94?4|5::<6>;4=20a>d`<uz8n?7>52z?042<e>279<l4<5:p6f6=838p1>>7:278964d2hl0q~<j4;296~;4810i:63=0c801>{t:0o1<7<t=3g4>63<5::26lh4}r0`6?6=:r79i:4m6:?2ad<4=2wx>4h50;0x97c?2:?01>>l:`d8yv4d;3:1>v3=e98a2>;6mk0896s|2`294?4|5;o26>;4=22g>d`<uz8h87>52z?1a<<e>27:in4<5:p6d7=838p1?kn:278966b2hl0q~<l5;296~;5mh0i:63>ee801>{t:h81<7<t=3ga>63<5::m6lh4}r0`2?6=:r79io4m6:?2a`<4=2wx>l=50;0x97cd2:?01>??:`d8yv4d?3:1>v3=eb8a2>;6mo0896s|2`694?4|5;oo6>;4=232>d`<uz8h47>52z?1aa<e>27:j=4<5:p6d3=838p1?kj:27896752hl0q~<l9;296~;5ml0i:63>f0801>{t:h<1<7<t=3ge>63<5:;86lh4}r0`e?6=:r79ik4m6:?2b7<4=2wx>l950;0x97`72:?01>?;:`d8yv4dj3:1>v3=f18a2>;6n:0896s|2`;94?4|5;l96>;4=236>d`<uz8hh7>52z?1b7<e>27:j84<5:p6dg=838p1?h<:27896702hl0q~<le;296~;5n:0i:63>f7801>{t:hh1<7<t=3d7>63<5:;36lh4}r0`b?6=:r79j94m6:?2b2<4=2wx>lm50;0x97`22:?01>?6:`d8yv4c83:1>v3=f48a2>;6n10896s|2`f94?4|5;l=6>;4=23b>d`<uz8o=7>52z?1b3<e>27:j44<5:p6dc=838p1?h8:278967e2hl0q~<k2;296~;5n>0i:63>f`801>{t:hl1<7<t=3d;>63<5:;h6lh4}r0g7?6=:r79j54m6:?2bg<4=2wx>o>50;0x97`>2:?01>?k:`d8yv4c<3:1>v3=f88a2>;6nj0896s|2c394?4|5;lj6>;4=23f>d`<uz8o97>52z?1bd<e>27:ji4<5:p6g4=838p1?hm:278967a2hl0q~<k6;296~;5nk0i:63>fd801>{t:k>1<7<t=3dg>63<5:8;6lh4}r0g<?6=:r79ji4m6:?145<4=2wx>o;50;0x97`b2:?01><=:`d8yv4c13:1>v3=fd8a2>;5880896s|2c494?4|5;lm6>;4=200>d`<uz8om7>52z?1bc<e>279<?4<5:p6g1=838p1>>?:27896432hl0q~<kb;296~;4890i:63=02801>{t:k21<7<t=222>63<5:8>6lh4}r0gg?6=:r78<<4m6:?141<4=2wx>o750;0x96652:?01><9:`d8yv4cl3:1>v3<038a2>;58<0896s|33f94?42s48;h7=;c:?166<4<j16>>7535a8972a2:>h70<:4;17g>;598088n5221d971e<5;;86>:l;<021?53k279=:4<4b9>64g=;=i01??l:26`?845839?o63=1d800f=::;81?9m4=306>62d3489;7=;c:?16<<4<j16>?l535a897572:>h70<=d;17g>;5;;088n52226971e<5;9=6>:l;<00f?53k279?54<4b9>66b=;=i01?=i:26`?843939?o63=47800f=::=91?9m4=36;>62d348?m7=;c:?10f<4<j16>9k535a897362:>h70==d;ce?xu5080;6?u221f972=:;9k1855rs20f>5<5=r79=54<4b9>612=;=i01?<j:26`?842;39?o63=0d800f=::8:1?9m4=331>62d348:87=;c:?15<<4<j16><8535a8977e2:>h70<>d;17g>;59o088n52233971e<5;8?6>:l;<01<?53k279>;4<4b9>67g=;=i01?<l:26`?845n39?o63=30800f=:::91?9m4=314>62d348897=;c:?17d<4<j16>>k535a8975d2:>h70<;0;17g>;5<;088n52257971e<5;><6>:l;<07=?53k2798i4<4b9>61d=;=i01?;?:26`?842:39?o63<2d8bb>{t:1i1<7<t=33;>61<5::j6974}r0:3?6=:r79>>4<7:?04g<302wx>;h50;0x97232:=01>?9:5;8yv42i3:1>v3=2d803>;48k0?56s|27794?4|5;926>94=235>1><uz8<<7>52z?10c<4?278><4;8:p627=838p1?;<:25896462=30q~<82;296~;5==08;63<2687<>{t:>91<7<t=32f>61<5:8<6974}r042?6=:r79=<4<7:?06<<302wx>::50;0x976a2:=01><7:5:8yv40=3:1>v3=11803>;4:10?56s|26594?4|5;;96>94=20:>1?<uz8<47>52z?156<4?278>l4;8:p62?=838p1??;:258964f2=30q~<8a;296~;59<08;63<2c87<>{t:>n1<7<t=33:>61<5:8h6974}r04f?6=:r79=;4<7:?06g<312wx>:m50;0x97702:=01><l:5:8yv40m3:1>v3=1`803>;4800?46s|26d94?4|5;;i6>94=22:>1?<uz83<7>52z?15f<4?278<n4;8:p6=4=838p1??k:258966d2=30q~<75;296~;5:908;63<0d87<>{t:191<7<t=33f>61<5::o6964}r0;0?6=:r79=k4<7:?04a<312wx>5850;0x97462:=01>>j:5;8yv4??3:1>v3=23803>;48o0?46s|29:94?4|5;8?6>94=22e>1?<uz8357>52z?160<4?278==4;8:p6=b=838p1?<7:25896762=30q~<7a;296~;5:?08;63<1187=>{t:1h1<7<t=304>61<5:;:6964}r0;a?6=:r79>44<7:?057<302wx>5h50;0x974f2:=01>?=:5;8yv4>83:1>v3=2c803>;49:0?46s|28394?4|5;8h6>94=230>1?<uz8287>52z?175<4?278=84;8:p6<4=838p1?<k:25896732=20q~<63;296~;5:o08;63<1587=>{t:0?1<7<t=312>61<5:;>6974}r0:2?6=:r79??4<7:?052<302wx>4650;0x97542:=01>?8:5;8yv4>13:1>v3=35803>;4910?46s|28a94?4|5;9<6>94=23:>1?<uz82m7>52z?170<4?278=54;9:p6<d=838p1?=9:258967>2=20q~<:7;296~;5;k08;63<1c87<>{t:<?1<7<t=31;>61<5:;j6964}r062?6=:r79?l4<7:?05d<312wx>8l50;0x975b2:=01>?l:5;8yv4203:1>v3=3b803>;49k0?56s|24;94?4|5;9o6>94=23`>1><uz8>o7>52z?17c<4?278=i4;8:p60b=838p1?:?:258967c2=30q~<:e;296~;5<808;63<1d87<>{t:<l1<7<t=361>61<5:;n6974}r056?6=:r798;4<7:?065<302wx>;>50;0x97242:=01>?i:5:8yv4193:1>v3=44803>;49o0?56s|27194?4|5;><6>94=203>1?<uz8=87>52z?10=<4?278>?4;8:p630=838p1?:6:25896452=30q~<97;296~;5<h08;63<2287<>{t:?k1<7<t=36g>61<5:8?6974}r05<?6=:r798o4<7:?066<312wx>;750;0x972d2:=01><;:5:8yv41j3:1>v3=4d803>;4:<0?46s|27a94?4|5;?;6>94=206>1?<uz8=h7>52z?114<4?278>;4;8:p63c=838p1?;=:25896412=30q~<?c;2960}::9?1>h5221696`=::991>h5221096`=::9;1>h5221296`=:9oo1>h521gf96`=:9oi1>h521g`96`=:9ok1>h521g;96`=:9o21>h521g596`=:9o<1>h521g796`=:9o91>h521g096`=:9o;1>h521g296`=:9ll1>h521dg96`=:9ln1>h521da96`=:9lh1>h521dc96`=::9h1>h5221c96`=::931>h5221:96`=::9=1>h5221496`=:9ol1>h521g696`=:9l31>h521d:96`=:9;o1mk5rs0:;>5<4s4;3:7=:;<3;3?5234;357oi;|q2<3<72?q6=585b79>5=3=<>16=5j5499>77b=<>16??k5489>5=c=<11v<6?:181870n39>70?71;ce?xu0<3:1>v3>0987e>;6800?i6s|7683>7}:l=0?m63k5;6f?xu61h0;6?u218;90<=:90=18h5rs06e>5<5s4;?i7:6;<37g?2b3ty::94?:3y>57e=io16=>h54`9~w4262909w0?;1;ce?87383>37p}>4383>7}:9=81mk5215190<=z{89o6=4={<30`?ga34;?<7:8;|q27c<72;q6=9>5489>56`=io1v<:<:18187383>j70?;3;6f?xu6k:0;6?u219f9ec=:9131855rs0:1>5<5s4;3>7oi;<3;5?2?3ty:4>4?:3y>5=5=io16=5:5489~w41b2908w0?71;6:?87?13>j70?8d;ce?xu60=0;6?u219390d=:91>18h5rs05a>5<5s4;<n7oi;<34`?2f3ty:4l4?:3y>5=g=io16=5m54`9~w4>e2909w0?7b;ce?87?k3>27p}>8b83>7}:9131845219a90`=z{89n6=4={<30b?2>34;8i7:j;|q23f<72;q6=:j5489>52e=<l1vq~:<2;296~X3;;16>o4;339'711=111v9=6:181[241279n7:<9:&002<>12wx8?650;0xZ14?348i69<7;%173?g53ty8m94?:3y]7=6<5;h1?5>4$264>30<uz9j>7>52z\03c=::k08;k5+355934=z{:k:6=4={_14a>;5j39<i6*<46847>{t;h:1<7<t^25g?84e2:=o7)=;7;57?xu41o0;6?uQ36a897d=;>i0(>:8:648yv5>m3:1>vP<7c9>6g<4?k1/?995769~w6?d2909wS=89:?1f?5012.88:488:p7<d=838pR>97;<0a>61?3-9?;796;|q0=d<72;qU?:94=3`9721<,:><6:o4}r1:=?6=:rT8;;522c8033=#;==1;o5rs2;;>5<5sW9<963=b;141>"4<>0<o6s|38594?4|V:=?70<m:257?!53?3=o7p}<9783>7}Y;>901?l53618 6202>o0q~=65;296~X4?;16>o4<739'711=?o1v>7;:181[509279n7=81:&002<?82wx?4=50;0xZ617348i6>9?;%173?>63ty85<4?:3y]73c<5;h1?;k4$264>=4<uz92<7>52z\02a=::k08:i5+3559<6=z{:2m6=4={_15g>;5j39=o6*<468;0>{t;1o1<7<t^24a?84e2:<i7)=;7;:6?xu40m0;6?uQ37c897d=;?k0(>:8:948yv5?k3:1>vP<689>6g<4>01/?995869~w6>e2909wS=98:?1f?5102.88:478:p7=g=838pR>88;<0a>6003-9?;766;|q0<<<72;qU?;84=3`9730<,:><65o4}r1;<?6=:rT8:8522c8020=#;==14o5rs2ca>5<5sW93:63=b;1;2>"4<>03o6s|3`c94?4|V:2>70<m:2:6?!53?32o7p}<a883>7}Y;1>01?l53968 62021o0q~=n8;296~X40:16>o4<829'711=0o1v>o8:181[5?:279n7=72:&002<>82wx?l850;0xZ6>6348i6>6>;%173??63ty8m84?:3y]72g<5;h1?:o4$264><4<uz92h7>52z\02c=::k08:k5+3559=6=z{:396=4={_150>;5j39=86*<468:0>{t;1=1<7<t^240?84e2:<87)=;7;;6?xu3<90;6?uQ452897d=<=:0(>:8:848yv2483:1>vP;319>6g<3;91/?995969~w6cc2909wS=l9:?1f?5d12.88:46a:p7`d=838pR>m7;<0a>6e?3-9?;77m;|q0ad<72;qU?n94=3`97f1<,:><64m4}r1f=?6=:rT8o;522c80g3=#;==15i5rs2g;>5<5sW9h963=b;1`1>"4<>02i6s|3d594?4|V:i?70<m:2a7?!53?33m7p}<e483>7}Y;j801?l53b08 6202h:0q~=j4;296~X4k816>o4<c09'711=i81v>k<:181[5d8279n7=l0:&002<f;2wx?h<50;0xZ6da348i6>li;%173?g33ty8i<4?:3y]7gc<5;h1?ok4$264>d3<uz9n<7>52z\0fa=::k08ni5+3559e3=z{:nm6=4={_1ag>;5j39io6*<468b3>{t;mo1<7<t^2`a?84e2:hi7)=;7;c;?xu4lm0;6?uQ3cc897d=;kk0(>:8:`;8yv5ck3:1>vP<b89>6g<4j01/?995a`9~w6bf2909wS=m7:?1f?5e?2.88:4nb:p7a?=838pR>l9;<0a>6d13-9?;7ol;|q0`=<72;qU?o;4=3`97g3<,:><68m4}r1g3?6=:rT8n9522c80f1=#;==19i5rs2f5>5<5sW9i?63=b;1a7>"4<>0>i6s|3e794?4|V:h970<m:2`1?!53?3?m7p}<d583>7}Y;k;01?l53c38 6202?:0q~=k3;296~X4j916>o4<b19'711=>81v>j=:181[5fn279n7=nf:&002<1:2wx?i?50;0xZ6gb348i6>oj;%173?043ty8j94?:3y]7f`<5;h1?nh4$264>32<uz9m?7>52z\0g`=::k08oh5+355920=z{:l96=4={_1``>;5j39hh6*<46853>{t;o;1<7<t^2a`?84e2:ih7)=;7;4;?xu4n90;6?uQ3b`897d=;jh0(>:8:7;8yv5bn3:1>vP<c`9>6g<4kh1/?9956`9~w6cb2909wS=l3:?1f?5d;2.88:49b:p7`0=838pR>l7;<0a>6d?3-9?;78l;|q0`g<72;qU?lj4=3`97db<,:><6;j4}r1g4?6=:rT8mn522c80ef=#;==1:h5rs2d`>5<5sW9mo63=b;1eg>"4<>0=j6s|34:94?4|V:?370<m:27;?!53?3=;7p}<f783>7}Y;o<01?l53g48 6202>80q~:>5;296~X39<16>o4;149'711=?<1vqcm<e;296~N4<11vbn=i:181M5302weo9>50;0xL62?3tdh8<4?:3yK71><ugi?>7>52zJ00==zfj>86=4={I17<>{ik=>1<7<tH26;?xhd<<0;6?uG35:8yke3>3:1>vF<499~jf202909wE=;8:mg1>=838pD>:7;|l`0<<72;qC?964}oa7e?6=:rB8855rnb6a>5<5sA9?46sac5a94?4|@:>37p`l4e83>7}O;=20qcm;e;296~N4<11vbn:i:181M5302weo8>50;0xL62?3tdh9<4?:3yK71><ugi>>7>52zJ00==zfj?86=4={I17<>{ik<>1<7<tH26;?xhd=<0;6?uG35:8yke2>3:1>vF<499~jf302909wE=;8:mg0>=838pD>:7;|l`1<<72;qC?964}oa6e?6=:rB8855rnb7a>5<5sA9?46sac4a94?4|@:>37p`l5e83>7}O;=20qcm:e;296~N4<11vbn;i:181M5302weo;>50;0xL62?3tdh:<4?:3yK71><ugi=>7>52zJ00==zfj<86=4={I17<>{ik?>1<7<tH26;?xhd><0;6?uG35:8yke1>3:1>vF<499~jf002909wE=;8:mg3>=838pD>:7;|l`2<<72;qC?964}oa5e?6=:rB8855rnb4a>5<5sA9?46sac7a94?4|@:>37p`l6e83>7}O;=20qcm9e;296~N4<11vbn8i:181M5302weo:>50;0xL62?3tdh;<4?:3yK71><ugi<>7>52zJ00==zfj=86=4={I17<>{ik>>1<7<tH26;?xhd?<0;6?uG35:8yke0>3:1>vF<499~jf102909wE=;8:mg2>=838pD>:7;|l`3<<72;qC?964}oa4e?6=:rB8855rnb5a>5<5sA9?46sac6a94?4|@:>37p`l7e83>7}O;=20qcm8e;296~N4<11vbn9i:181M5302weo5>50;0xL62?3tdh4<4?:3yK71><ugi3>7>52zJ00==zfj286=4={I17<>{ik1>1<7<tH26;?xhd0<0;6?uG35:8yke?>3:1>vF<499~jf>02909wE=;8:mg=>=838pD>:7;|l`<<<72;qC?964}oa;e?6=:rB8855rnb:a>5<5sA9?46sac9a94?4|@:>37p`l8e83>7}O;=20qcm7e;296~N4<11vbll9:182M5302wen=950;3xL62?3tdi<54?:0yK71><ugh;57>51zJ00==zfk:j6=4>{I17<>{ij9h1<7?tH26;?xhe8j0;6<uG35:8ykd7l3:1=vF<499~jg6b290:wE=;8:mf5`=83;pD>:7;|la55<728qC?964}o`25?6=9rB8855rnc31>5<6sA9?46sab0194?7|@:>37p`m1583>4}O;=20qcl>5;295~N4<11vbo?9:182M5302wen<950;3xL62?3tdi=54?:0yK71><ugh:57>51zJ00==zfk;j6=4>{I17<>{ij8h1<7?tH26;?xhe9j0;6<uG35:8ykd6l3:1=vF<499~jg7b290:wE=;8:mf4`=83;pD>:7;|la65<728qC?964}o`15?6=9rB8855rnc01>5<6sA9?46sab3194?7|@:>37p`m2583>4}O;=20qcl=5;295~N4<11vbo<9:182M5302wen?950;3xL62?3tdi>54?:0yK71><ugh957>51zJ00==zfk8j6=4>{I17<>{ij;h1<7?tH26;?xhe:j0;6<uG35:8ykd5l3:1=vF<499~jg4b290:wE=;8:mf7`=83;pD>:7;|la75<728qC?964}o`05?6=9rB8855rnc11>5<6sA9?46sab2194?7|@:>37p`m3583>4}O;=20qcl<5;295~N4<11vbo=9:182M5302wen>950;3xL62?3tdi?54?:0yK71><ugh857>51zJ00==zfk9j6=4>{I17<>{ij:h1<7?tH26;?xhe;j0;6<uG35:8ykd4l3:1=vF<499~jg5b290:wE=;8:mf6`=83;pD>:7;|la05<728qC?964}o`75?6=9rB8855rnc61>5<6sA9?46sab5194?7|@:>37p`m4583>4}O;=20qcl;5;295~N4<11vbo:9:182M5302wen9950;3xL62?3tdi854?:0yK71><ugh?57>51zJ00==zfk>j6=4>{I17<>{ij=h1<7?tH26;?xhe<j0;6<uG35:8ykd3l3:1=vF<499~jg2b290:wE=;8:mf1`=83;pD>:7;|la15<728qC?964}o`65?6=9rB8855rnc71>5<6sA9?46sab4194?7|@:>37p`m5583>4}O;=20qcl:5;295~N4<11vbo;9:182M5302wen8950;3xL62?3tdi954?:0yK71><ugh>57>51zJ00==zfk?j6=4>{I17<>{ij<h1<7?tH26;?xhe=j0;6<uG35:8ykd2l3:1=vF<499~jg3b290:wE=;8:mf0`=83;pD>:7;|la25<728qC?964}o`55?6=9rB8855rnc41>5<6sA9?46sab7194?7|@:>37p`m6583>4}O;=20qcl95;295~N4<11vbo89:182M5302wen;950;3xL62?3tdi:54?:0yK71><ugh=57>51zJ00==zfk<j6=4>{I17<>{ij?h1<7?tH26;?xhe>j0;6<uG35:8ykd1l3:1=vF<499~jg0b290:wE=;8:mf3`=83;pD>:7;|la35<728qC?964}o`45?6=9rB8855rnc51>5<6sA9?46sab6194?7|@:>37p`m7583>4}O;=20qcl85;295~N4<11vbo99:182M5302wen:950;3xL62?3tdi;54?:0yK71><ugh<57>51zJ00==zfk=j6=4>{I17<>{ij>h1<7?tH26;?xhe?j0;6<uG35:8ykd0l3:1=vF<499~jg1b290:wE=;8:mf2`=83;pD>:7;|la<5<728qC?964}o`;5?6=9rB8855rnc:1>5<6sA9?46sab9194?7|@:>37p`m8583>4}O;=20qcl75;295~N4<11vbo69:182M5302wen5950;3xL62?3tdi454?:0yK71><ugh357>51zJ00==zfk2j6=4>{I17<>{ij1h1<7?tH26;?xhe0j0;6<uG35:8ykd?l3:1=vF<499~jg>b290:wE=;8:mf=`=83;pD>:7;|la=5<728qC?964}o`:5?6=9rB8855rnc;1>5<6sA9?46sab8194?7|@:>37p`m9583>4}O;=20qcl65;295~N4<11vbo79:182M5302wen4950;3xL62?3tdi554?:0yK71><ugh257>51zJ00==zfk3j6=4>{I17<>{ij0h1<7?tH26;?xhe1j0;6<uG35:8ykd>l3:1=vF<499~jg?b290:wE=;8:mf<`=83;pD>:7;|lae5<728qC?964}o`b5?6=9rB8855rncc1>5<6sA9?46sab`194?7|@:>37p`ma583>4}O;=20qcln5;295~N4<11vboo9:182M5302wenl950;3xL62?3tdim54?:0yK71><ughj57>51zJ00==zfkkj6=4>{I17<>{ijhh1<7?tH26;?xheij0;6<uG35:8ykdfl3:1=vF<499~jggb290:wE=;8:mfd`=83;pD>:7;|laf5<728qC?964}o`a5?6=9rB8855rnc`1>5<6sA9?46sabc194?7|@:>37p`mb583>4}O;=20qclm5;295~N4<11vbol9:182M5302weno950;3xL62?3tdin54?:0yK71><ughi57>51zJ00==zfkhj6=4>{I17<>{ijkh1<7?tH26;?xhejj0;6<uG35:8ykdel3:1=vF<499~jgdb290:wE=;8:mfg`=83;pD>:7;|lag5<728qC?964}o``5?6=9rB8855rnca1>5<6sA9?46sabb194?7|@:>37p`mc583>4}O;=20qcll5;295~N4<11vbom9:182M5302wenn950;3xL62?3tdio54?:0yK71><ughh57>51zJ00==zfkij6=4>{I17<>{ijjh1<7?tH26;?xhekj0;6<uG35:8ykddl3:1=vF<499~jgeb290:wE=;8:mff`=83;pD>:7;|la`5<728qC?964}o`g5?6=9rB8855rncf1>5<6sA9?46sabe194?7|@:>37p`md583>4}O;=20qclk5;295~N4<11vboj9:182M5302weni950;3xL62?3tdih54?:0yK71><ugho57>51zJ00==zfknj6=4>{I17<>{ijmh1<7?tH26;?xhelj0;6<uG35:8ykdcl3:1=vF<499~jgbb290:wE=;8:mfa`=83;pD>:7;|laa5<728qC?964}o`f5?6=9rB8855rncg1>5<6sA9?46sabd194?7|@:>37p`me583>4}O;=20qclj5;295~N4<11vbok9:182M5302wenh950;3xL62?3tdii54?:0yK71><ughn57>51zJ00==zfkoj6=4>{I17<>{ijlh1<7?tH26;?xhemj0;6<uG35:8ykdbl3:1=vF<499~jgcb290:wE=;8:mf``=83;pD>:7;|lab5<728qC?964}o`e5?6=9rB8855rncd1>5<6sA9?46sabg194?7|@:>37p`mf583>4}O;=20qcli5;295~N4<11vboh9:182M5302wenk950;3xL62?3tdij54?:0yK71><ughm57>51zJ00==zfklj6=4>{I17<>{ijoh1<7?tH26;?xhenj0;6<uG35:8ykdal3:1=vF<499~jg`b290:wE=;8:mfc`=83;pD>:7;|l`45<728qC?964}oa35?6=9rB8855rnb21>5<6sA9?46sac1194?7|@:>37p`l0583>4}O;=20qcm?5;295~N4<11vbn>9:182M5302weo=950;3xL62?3tdh<54?:0yK71><ugi;57>51zJ00==zfj:j6=4>{I17<>{ik9h1<7?tH26;?xhd8j0;6<uG35:8yke7l3:1=vF<499~jf6b290:wE=;8:mg5`=83;pD>:7;|l`55<728qC?964}oa25?6=9rB8855rnb31>5<6sA9?46sac0194?7|@:>37p`l1583>4}O;=20qcm>5;295~N4<11vbn?9:182M5302weo<950;3xL62?3tdh=54?:0yK71><ugi:57>51zJ00==zfj;j6=4>{I17<>{ik8h1<7?tH26;?xhd9j0;6<uG35:8yke6l3:1=vF<499~jf7b290:wE=;8:mg4`=83;pD>:7;|l`65<728qC?964}oa15?6=9rB8855rnb01>5<6sA9?46sac3194?7|@:>37p`l2583>4}O;=20qcm=5;295~N4<11vbn<9:182M5302weo?950;3xL62?3tdh>54?:0yK71><ugi957>51zJ00==zfj8j6=4>{I17<>{ik;h1<7?tH26;?xhd:j0;6<uG35:8yke5l3:1=vF<499~jf4b290:wE=;8:mg7`=83;pD>:7;|l`75<728qC?964}oa05?6=9rB8855rnb11>5<6sA9?46sac2194?7|@:>37p`l3583>4}O;=20qcm<5;295~N4<11vbn=9:182M5302weo>950;3xL62?3tdh?54?:0yK71><ugi857>51zJ00==zfj9j6=4>{I17<>{ik:h1<7?tH26;?xhd;j0;6<uG35:8yke4l3:1=vF<499~yx{GHJqn=546ee65e44zHIHp<pNOPzCD
\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v new file mode 100644 index 000000000..68a8caaf6 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v @@ -0,0 +1,3839 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: M.63c +// \ \ Application: netgen +// / / Filename: fifo_xlnx_32x36_2clk.v +// /___/ /\ Timestamp: Fri Oct 15 00:50:08 2010 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog /tmp/_cg/fifo_xlnx_32x36_2clk.ngc /tmp/_cg/fifo_xlnx_32x36_2clk.v +// Device : 3s2000fg456-5 +// Input file : /tmp/_cg/fifo_xlnx_32x36_2clk.ngc +// Output file : /tmp/_cg/fifo_xlnx_32x36_2clk.v +// # of Modules : 1 +// Design Name : fifo_xlnx_32x36_2clk +// Xilinx : /opt/Xilinx/12.2/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module fifo_xlnx_32x36_2clk ( + rd_en, almost_full, prog_full, wr_en, full, empty, wr_clk, rst, rd_clk, dout, din +)/* synthesis syn_black_box syn_noprune=1 */; + input rd_en; + output almost_full; + output prog_full; + input wr_en; + output full; + output empty; + input wr_clk; + input rst; + input rd_clk; + output [35 : 0] dout; + input [35 : 0] din; + + // synthesis translate_off + + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ; + wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ; + wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ; + wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ; + wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ; + wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ; + wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/N11 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/N11 ; + wire \BU2/N16 ; + wire \BU2/N14 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ; + wire \BU2/U0/grf.rf/mem/dout_i_not0001 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N147 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N145 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N143 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N141 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N137 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N135 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N139 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N133 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N131 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N129 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N127 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N123 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N121 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N125 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N119 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N117 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N115 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N113 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N109 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N107 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N111 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N103 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N101 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N105 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N97 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N95 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N99 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N93 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N91 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N89 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N87 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N83 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N81 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N85 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N79 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N77 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N75 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N73 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N69 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N67 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N71 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N65 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N63 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N61 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N59 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N55 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N53 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N57 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N51 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N49 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N47 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N45 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N41 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N39 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N43 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N37 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N35 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N33 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N31 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N27 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N25 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N29 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N23 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N21 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N19 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N17 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N13 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N11 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N15 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N9 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N7 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/N5 ; + wire \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ; + wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ; + wire \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ; + wire \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ; + wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ; + wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ; + wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ; + wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ; + wire \BU2/U0/grf.rf/rstblk/wr_rst_comb ; + wire \BU2/U0/grf.rf/rstblk/rd_rst_comb ; + wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ; + wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ; + wire \BU2/U0/grf.rf/rstblk/rst_d1_93 ; + wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ; + wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ; + wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ; + wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ; + wire \BU2/U0/grf.rf/rstblk/rst_d2_88 ; + wire \BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ; + wire \BU2/U0/grf.rf/rstblk/rst_d3_86 ; + wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ; + wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ; + wire \BU2/N1 ; + wire NLW_VCC_P_UNCONNECTED; + wire NLW_GND_G_UNCONNECTED; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ; + wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ; + wire [35 : 0] din_2; + wire [35 : 0] dout_3; + wire [35 : 0] \BU2/U0/grf.rf/mem/gdm.dm/dout_i ; + wire [35 : 0] \BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 ; + wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 ; + wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 ; + wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 ; + wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count ; + wire [5 : 4] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad ; + wire [5 : 1] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut ; + wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy ; + wire [5 : 4] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 ; + wire [1 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state ; + wire [1 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 ; + wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 ; + wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count ; + wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc ; + wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc ; + wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 ; + wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg ; + wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 ; + wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg ; + wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin ; + wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin ; + wire [1 : 0] \BU2/U0/grf.rf/rstblk/wr_rst_reg ; + wire [2 : 0] \BU2/U0/grf.rf/rstblk/rd_rst_reg ; + wire [0 : 0] \BU2/rd_data_count ; + assign + dout[35] = dout_3[35], + dout[34] = dout_3[34], + dout[33] = dout_3[33], + dout[32] = dout_3[32], + dout[31] = dout_3[31], + dout[30] = dout_3[30], + dout[29] = dout_3[29], + dout[28] = dout_3[28], + dout[27] = dout_3[27], + dout[26] = dout_3[26], + dout[25] = dout_3[25], + dout[24] = dout_3[24], + dout[23] = dout_3[23], + dout[22] = dout_3[22], + dout[21] = dout_3[21], + dout[20] = dout_3[20], + dout[19] = dout_3[19], + dout[18] = dout_3[18], + dout[17] = dout_3[17], + dout[16] = dout_3[16], + dout[15] = dout_3[15], + dout[14] = dout_3[14], + dout[13] = dout_3[13], + dout[12] = dout_3[12], + dout[11] = dout_3[11], + dout[10] = dout_3[10], + dout[9] = dout_3[9], + dout[8] = dout_3[8], + dout[7] = dout_3[7], + dout[6] = dout_3[6], + dout[5] = dout_3[5], + dout[4] = dout_3[4], + dout[3] = dout_3[3], + dout[2] = dout_3[2], + dout[1] = dout_3[1], + dout[0] = dout_3[0], + din_2[35] = din[35], + din_2[34] = din[34], + din_2[33] = din[33], + din_2[32] = din[32], + din_2[31] = din[31], + din_2[30] = din[30], + din_2[29] = din[29], + din_2[28] = din[28], + din_2[27] = din[27], + din_2[26] = din[26], + din_2[25] = din[25], + din_2[24] = din[24], + din_2[23] = din[23], + din_2[22] = din[22], + din_2[21] = din[21], + din_2[20] = din[20], + din_2[19] = din[19], + din_2[18] = din[18], + din_2[17] = din[17], + din_2[16] = din[16], + din_2[15] = din[15], + din_2[14] = din[14], + din_2[13] = din[13], + din_2[12] = din[12], + din_2[11] = din[11], + din_2[10] = din[10], + din_2[9] = din[9], + din_2[8] = din[8], + din_2[7] = din[7], + din_2[6] = din[6], + din_2[5] = din[5], + din_2[4] = din[4], + din_2[3] = din[3], + din_2[2] = din[2], + din_2[1] = din[1], + din_2[0] = din[0]; + VCC VCC_0 ( + .P(NLW_VCC_P_UNCONNECTED) + ); + GND GND_1 ( + .G(NLW_GND_G_UNCONNECTED) + ); + LUT3_L #( + .INIT ( 8'h90 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ), + .LO(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ) + ); + LUT4_L #( + .INIT ( 16'h9000 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]), + .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ), + .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ), + .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ) + ); + LUT4_L #( + .INIT ( 16'h9000 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ), + .I3(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ) + ); + LUT4_L #( + .INIT ( 16'h8421 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), + .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ) + ); + LUT4_L #( + .INIT ( 16'h8241 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .LO(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ) + ); + LUT3_L #( + .INIT ( 8'h7F )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .LO(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 ) + ); + LUT3_L #( + .INIT ( 8'h7F )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>111 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .LO(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 ) + ); + LUT2_L #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_SW0 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), + .LO(\BU2/N16 ) + ); + LUT2_L #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_SW0 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), + .LO(\BU2/N14 ) + ); + INV \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<0>11_INV_0 ( + .I(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ) + ); + INV \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<0>11_INV_0 ( + .I(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_1 ( + .I0(wr_en), + .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .O(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ) + ); + LUT4 #( + .INIT ( 16'h2333 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_1 ( + .I0(rd_en), + .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>12 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>12 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1 ( + .I0(wr_en), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), + .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), + .I2(wr_en), + .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<5> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5]) + ); + LUT4 #( + .INIT ( 16'h9000 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i78 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]), + .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ), + .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ) + ); + LUT4 #( + .INIT ( 16'h9000 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ), + .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<4> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<3> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<2> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2]) + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<1> ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1]) + ); + LUT4 #( + .INIT ( 16'h5450 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000105 ( + .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ), + .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ) + ); + LUT4 #( + .INIT ( 16'h8421 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ) + ); + LUT4 #( + .INIT ( 16'h5450 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000107 ( + .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), + .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ), + .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ), + .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]), + .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1 ( + .I0(wr_en), + .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ) + ); + LUT4 #( + .INIT ( 16'hECA0 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000183 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ), + .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ) + ); + LUT4 #( + .INIT ( 16'h8421 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ) + ); + LUT4 #( + .INIT ( 16'h8241 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ) + ); + LUT4 #( + .INIT ( 16'h2333 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21 ( + .I0(rd_en), + .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ) + ); + LUT3 #( + .INIT ( 8'hA6 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<4>11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 ), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ) + ); + LUT3 #( + .INIT ( 8'hA6 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<4>11 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 ), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N5 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N7 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1011 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N45 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N47 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N9 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N11 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N49 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N51 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1211 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N53 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N55 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1311 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N57 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N59 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1411 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N61 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N63 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1511 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N65 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N67 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1611 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N69 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N71 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1711 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N73 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N75 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1811 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N77 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N79 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1911 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N81 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N83 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2011 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N85 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N87 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N13 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N15 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX21111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N89 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N91 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2211 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N93 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N95 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2311 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N97 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N99 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2411 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N101 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N103 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2511 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N105 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N107 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2611 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N109 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N111 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2711 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N113 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N115 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2811 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N117 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N119 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2911 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N121 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N123 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3011 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N125 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N127 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N17 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N19 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX31111 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N129 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N131 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3211 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N133 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N135 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3311 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N137 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N139 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3411 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N141 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N143 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3511 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N145 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N147 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX411 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N21 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N23 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX511 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N25 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N27 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX611 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N29 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N31 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX711 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N33 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N35 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX811 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N37 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N39 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8]) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX911 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/mem/gdm.dm/N41 ), + .I2(\BU2/U0/grf.rf/mem/gdm.dm/N43 ), + .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9]) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .I3(\BU2/N16 ), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .I3(\BU2/N14 ), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ) + ); + LUT3 #( + .INIT ( 8'hA2 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_REGOUT_EN11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .I2(rd_en), + .O(\BU2/U0/grf.rf/mem/dout_i_not0001 ) + ); + LUT2 #( + .INIT ( 4'hD )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_not00011 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ), + .I1(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ) + ); + LUT4 #( + .INIT ( 16'h8E8A )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux00001 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I3(rd_en), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00021 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ) + ); + LUT4 #( + .INIT ( 16'h6996 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00021 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ) + ); + LUT4 #( + .INIT ( 16'h40FF )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<0>1 ( + .I0(rd_en), + .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0]) + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<2>11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<2>11 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00011 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), + .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00011 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), + .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ) + ); + LUT3 #( + .INIT ( 8'hF2 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<1>1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]), + .I1(rd_en), + .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]), + .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1]) + ); + LUT3 #( + .INIT ( 8'h08 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux00031 ( + .I0(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5]), + .I2(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0000_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0001_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0002_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0003_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0000_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0001_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0002_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0003_Result1 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<1>11 ( + .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<1>11 ( + .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00001 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00001 ( + .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]), + .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \BU2/U0/grf.rf/rstblk/rd_rst_comb1 ( + .I0(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ), + .I1(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ), + .O(\BU2/U0/grf.rf/rstblk/rd_rst_comb ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \BU2/U0/grf.rf/rstblk/wr_rst_comb1 ( + .I0(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ), + .I1(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ), + .O(\BU2/U0/grf.rf/rstblk/wr_rst_comb ) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .Q(almost_full) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .Q(full) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .Q(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0]), + .Q(dout_3[0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1]), + .Q(dout_3[1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2]), + .Q(dout_3[2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3]), + .Q(dout_3[3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4]), + .Q(dout_3[4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_5 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5]), + .Q(dout_3[5]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_6 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6]), + .Q(dout_3[6]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_7 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7]), + .Q(dout_3[7]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_8 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8]), + .Q(dout_3[8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_9 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9]), + .Q(dout_3[9]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_10 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10]), + .Q(dout_3[10]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_11 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11]), + .Q(dout_3[11]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_12 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12]), + .Q(dout_3[12]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_13 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13]), + .Q(dout_3[13]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_14 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14]), + .Q(dout_3[14]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_15 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15]), + .Q(dout_3[15]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_16 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16]), + .Q(dout_3[16]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_17 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17]), + .Q(dout_3[17]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_18 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18]), + .Q(dout_3[18]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_19 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19]), + .Q(dout_3[19]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_20 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20]), + .Q(dout_3[20]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_21 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21]), + .Q(dout_3[21]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_22 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22]), + .Q(dout_3[22]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_23 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23]), + .Q(dout_3[23]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_24 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24]), + .Q(dout_3[24]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_25 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25]), + .Q(dout_3[25]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_26 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26]), + .Q(dout_3[26]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_27 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27]), + .Q(dout_3[27]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_28 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28]), + .Q(dout_3[28]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_29 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29]), + .Q(dout_3[29]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_30 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30]), + .Q(dout_3[30]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_31 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31]), + .Q(dout_3[31]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_32 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32]), + .Q(dout_3[32]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_33 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33]), + .Q(dout_3[33]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_34 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34]), + .Q(dout_3[34]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/dout_i_35 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35]), + .Q(dout_3[35]) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[35]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N147 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[35]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N145 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[34]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N143 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[34]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N141 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[33]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N137 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[32]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N135 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[33]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N139 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[32]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N133 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[31]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N131 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[31]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N129 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[30]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N127 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[29]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N123 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[29]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N121 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[30]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N125 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[28]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N119 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[28]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N117 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[27]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N115 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[27]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N113 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[26]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N109 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[25]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N107 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[26]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N111 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[24]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N103 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[24]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N101 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[25]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N105 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[23]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N97 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[22]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N95 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[23]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N99 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[22]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N93 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[21]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N91 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[21]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N89 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[20]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N87 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[19]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N83 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[19]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N81 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[20]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N85 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[18]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N79 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[18]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N77 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[17]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N75 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[17]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N73 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[16]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N69 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[15]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N67 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[16]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N71 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[15]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N65 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[14]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N63 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[14]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N61 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[13]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N59 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[12]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N55 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[12]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N53 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[13]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N57 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[11]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N51 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[11]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N49 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[10]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N47 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[10]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N45 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[9]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N41 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[8]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N39 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[9]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N43 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[8]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N37 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[7]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N35 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[7]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N33 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[6]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N31 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[5]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N27 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[5]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N25 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[6]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N29 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[4]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N23 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[4]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N21 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[3]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N19 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[3]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N17 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[2]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N13 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[1]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N11 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[2]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N15 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[1]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N9 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[0]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N7 ) + ); + RAM16X1D \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1 ( + .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]), + .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]), + .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]), + .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]), + .D(din_2[0]), + .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]), + .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]), + .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]), + .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]), + .WCLK(wr_clk), + .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ), + .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ), + .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N5 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_35 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_34 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_33 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_32 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_31 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_30 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_29 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_28 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_27 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_26 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_25 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_24 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_23 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_22 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_21 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_20 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_19 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_18 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_17 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_16 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_15 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_14 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_13 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_12 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_11 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_10 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_9 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_8 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_7 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_6 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_5 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/mem/gdm.dm/dout_i_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]), + .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0]), + .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_2 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_0 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_1 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_3 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/wpntr/count_4 ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ), + .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ), + .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .Q(prog_full) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4]), + .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_5 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5]), + .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<0> ( + .CI(\BU2/N1 ), + .DI(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ), + .S(\BU2/rd_data_count [0]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<1> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<2> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<3> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]) + ); + MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<4> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]), + .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]), + .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<4> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4]) + ); + XORCY \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<5> ( + .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4]), + .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5]), + .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1]), + .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0]), + .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(empty) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_2 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]) + ); + FDPE #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_0 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_1 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_3 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]) + ); + FDCE #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gl0.rd/rpntr/count_4 ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ), + .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_0 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_1 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_2 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_3 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_4 ( + .C(rd_clk), + .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]), + .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_1 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_2 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_3 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_4 ( + .C(wr_clk), + .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]), + .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]), + .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/wr_rst_reg_0 ( + .C(wr_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/wr_rst_reg_1 ( + .C(wr_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rd_rst_reg_0 ( + .C(rd_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rd_rst_reg_1 ( + .C(rd_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rd_rst_reg_2 ( + .C(rd_clk), + .D(\BU2/rd_data_count [0]), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rst_d1 ( + .C(wr_clk), + .D(\BU2/rd_data_count [0]), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/rst_d1_93 ) + ); + FDPE \BU2/U0/grf.rf/rstblk/rd_rst_asreg ( + .C(rd_clk), + .CE(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ), + .D(\BU2/rd_data_count [0]), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1 ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ) + ); + FDPE \BU2/U0/grf.rf/rstblk/wr_rst_asreg ( + .C(wr_clk), + .CE(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ), + .D(\BU2/rd_data_count [0]), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1 ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rst_d2 ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/rstblk/rst_d1_93 ), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/rst_d2_88 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2 ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ), + .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2 ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ), + .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/rstblk/rst_d3 ( + .C(wr_clk), + .D(\BU2/U0/grf.rf/rstblk/rst_d2_88 ), + .PRE(rst), + .Q(\BU2/U0/grf.rf/rstblk/rst_d3_86 ) + ); + FDC #( + .INIT ( 1'b0 )) + \BU2/U0/grf.rf/rstblk/RST_FULL_GEN ( + .C(wr_clk), + .CLR(rst), + .D(\BU2/U0/grf.rf/rstblk/rst_d3_86 ), + .Q(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ) + ); + FDP #( + .INIT ( 1'b1 )) + \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i ( + .C(rd_clk), + .D(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ), + .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]), + .Q(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ) + ); + VCC \BU2/XST_VCC ( + .P(\BU2/N1 ) + ); + GND \BU2/XST_GND ( + .G(\BU2/rd_data_count [0]) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo new file mode 100644 index 000000000..eb98a2b70 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo @@ -0,0 +1,47 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_32x36_2clk YourInstanceName ( + .rst(rst), + .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [35 : 0] + .wr_en(wr_en), + .rd_en(rd_en), + .dout(dout), // Bus [35 : 0] + .full(full), + .almost_full(almost_full), + .empty(empty), + .prog_full(prog_full)); + +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco new file mode 100644 index 000000000..1cf4c8ba5 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco @@ -0,0 +1,84 @@ +############################################################## +# +# Xilinx Core Generator version 12.2 +# Date: Fri Oct 15 07:50:15 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=true +CSET component_name=fifo_xlnx_32x36_2clk +CSET data_count=false +CSET data_count_width=5 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Independent_Clocks_Distributed_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=24 +CSET full_threshold_negate_value=23 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=36 +CSET input_depth=32 +CSET output_data_width=36 +CSET output_depth=32 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=5 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=5 +# END Parameters +GENERATE +# CRC: 8e84ee7f diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise new file mode 100644 index 000000000..b9eb7bd1a --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise @@ -0,0 +1,72 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="fifo_xlnx_32x36_2clk.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation"/> + <association xil_pn:name="Implementation"/> + </file> + <file xil_pn:name="fifo_xlnx_32x36_2clk.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation"/> + <association xil_pn:name="Implementation"/> + <association xil_pn:name="PostMapSimulation"/> + <association xil_pn:name="PostRouteSimulation"/> + <association xil_pn:name="PostTranslateSimulation"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_32x36_2clk.ngc" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-10-15T00:50:17" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F8449944117490A53CFE9CD2127BE2AA" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt new file mode 100644 index 000000000..b8c69a9f7 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt @@ -0,0 +1,12 @@ +# Output products list for <fifo_xlnx_32x36_2clk> +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_32x36_2clk.gise +fifo_xlnx_32x36_2clk.ngc +fifo_xlnx_32x36_2clk.v +fifo_xlnx_32x36_2clk.veo +fifo_xlnx_32x36_2clk.xco +fifo_xlnx_32x36_2clk.xise +fifo_xlnx_32x36_2clk_flist.txt +fifo_xlnx_32x36_2clk_readme.txt +fifo_xlnx_32x36_2clk_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt new file mode 100644 index 000000000..8ab5679fd --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt @@ -0,0 +1,46 @@ +The following files were generated for 'fifo_xlnx_32x36_2clk' in directory +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_xlnx_32x36_2clk.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_32x36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_32x36_2clk.v: + Unisim Verilog file containing the information required to simulate + the module. + +fifo_xlnx_32x36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_32x36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_32x36_2clk.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_32x36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_32x36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + +fifo_xlnx_32x36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl new file mode 100644 index 000000000..ec9426357 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is <core_name>_xmdf +package provide fifo_xlnx_32x36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::fifo_xlnx_32x36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_32x36_2clk +} +# ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_32x36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise new file mode 100644 index 000000000..9abec8c3e --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc new file mode 100644 index 000000000..9cb73d5ce --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$4cb40<,[o}e~g`n;"2*726&;$9,)?40893456789:;8=5?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>;;1A3<4=6;2;%<<5=4:0076753:81EC^ZT;FJE956294:>6==:HLSQQ<CAK68=7>112906?IR\Y__6IAN<2394;743:81CXZ_UU8GKG:493:5=?5<6;KMTPR=l`d7?84?>06873<H]]Z^X7j`uu>01?69l29x>=>?ff662(363=>08=HI1097>LHW]]0OE]O33;2=54=32@D[YY4KIQ@?7?699;1?6B[[PTV9@JVF4:0;2<<44;MVPUSS2ME[N1=50?68102792<97;7;;7;:24=?<22;<=:48D:B5>?330:;5?56659:23?6:231EC^ZT;CG@WG;03:5=?56:HLSQQ<FLMXI054?>0g8=?OIX\^1|ah_dosp|Ys`{oxd1650?06?<<NFY__6}|`g^gntqX|axneQnsrgqp9>=878>744FNQWW>uthoVof|ywPtipfwmYimnki1650?3g?<<NFY__6}|`g^dvhiYs`{oxd1650?07?<<NFY__6}|`g^dvhiYs`{oxdRo|sdpw8=<76;>057GAPTV9twi`Wog`Rzgrdqk[kc`i}o747>1199:>JSSX\^1hlzn_bmvjq:?294:n675OTVSQQ<ulVnjxlQlotlw8=<768h057AZTQWW>rtXlh~jSnaznu>;>5853H837LJKR@>3:==FLMXJ0<07;@FGVD:5611JHI\N<2<;?DBCZH6?255NDEPB808?3HNO^L29>99B@ATF4>4j7LJKR@>;>58?3HNO^L27>99B@ATE49437LJKRC>2:==FLMXI0?07;@FGVG:4611JHI\M<5<;?DBCZK6>255NDEPA838?3HNO^O28>`9B@ATE410;255NDEPA8=843HFG56O\YOA\V@A63K90NX<7;CWP[LHAG81H>6MJ139@L@ELWECHIC]J_U[SA7=DA=1H@FO;;BNHF6=DD[30OBCBIUVF@42<KFXNSJKAESCWMJHXAGLD;6M]E@VF@4=C:2NH>6JF6:FJE969?2NBM1??>69GMD:697=0HDO313<4?AOF4895;6JFA=37:2=CAH6:9394DHC?53803MCJ0<917:FJE97?6>1OEL2>9?48@LG;97=0HDO321<4?AOF4;;5;6JFA=01:2=CAH69?394DHC?61803MCJ0?;17:FJE9416>1OEL2=7?58@LG;:14<7IGN<3;=2>BNI585;6JFA=13:<=CAH68=7>17:FJE9566?1OEL2<>79GMD:36?1OEL2:>79GMD:16?1OEL28>79GMD:?6?1OEL26>79GMG:76>1OEO2>0?58@LD;984<7IGM<00=3>BNJ5;82:5KIC>20;1<L@H7=808;EKA8409?2NBN1?8>69GMG:607=0HDL318<5?AOE484<7IGM<32=3>BNJ58:2:5KIC>16;1<L@H7>>08;EKA8729?2NBN1<:>69GMG:5>7=0HDL326<4?AOE4;25;6JFB=0::3=CAK692:5KIC>04;?<L@H7?<4?>69GMG:497<0HDL33?48@LD;<7<0HDL35?48@LD;>7<0HDL37?48@LD;07<0HDL39?58@LVF494<7IG_A=3=3>BNXH69245KIQC?7?69?2NB\L2<>69GMUD;87=0HD^M<0<4?AOWJ58556JFPC>0>5803MC[N1=16:FLE969?2NDM1??>69GKD:697=0HBO313<4?AIF4895;6J@A=37:2=CGH6:9394DNC?53803MEJ0<917:FLE97?6>1OCL2>9?48@JG;97=0HBO321<4?AIF4;;5;6J@A=01:2=CGH69?394DNC?61803MEJ0?;17:FLE9416>1OCL2=7?58@JG;:14<7IAN<3;=2>BHI585;6J@A=13:<=CGH68=7>17:FLE9566?1OCL2<>79GKD:36?1OCL2:>79GKD:16?1OCL28>79GKD:?6?1OCL26>69GKDYUMN<0HBL30?58@JD;994<7IAM<03=3>BHJ5;92:5KOC>27;1<LFH7=908;EMA8439?2NDN1?9>69GKG:6?7=0HBL319<4?AIE4835:6J@B=3=3>BHJ58;2:5KOC>15;1<LFH7>?08;EMA8759?2NDN1<;>69GKG:5=7=0HBL327<4?AIE4;=5;6J@B=0;:2=CGK695384DN@?6;1<LFH7?=06;EMA867=87=0HBL330<5?AIE4:4=7IAM<5<5?AIE4<4=7IAM<7<5?AIE4>4=7IAM<9<5?AIE404<7IAM_SGD3>BHXH6;2:5KOQC?5;1<LFZJ0?06;EMSE95=87=0HB^N<2<4?AIWJ5:5;6J@PC>2:2=CGYH7>374DNRA86<76>1OC]L33?18AKG43LDIn6KA_DA@[WCFLj1NBRKLC^UQMQC53O897K6:;GCOW@4<NM90JIM;;GF@A6=ALY>0JI^J4:DGV@7<O:1LBI<4I108M44<A;80E>64IOKWTZ6702CEEY^P00:8MKOSXV:946GAIUR\46><AGC_\R>;8:KMMQVX8<20ECG[P^25<>OIA]ZT<:74IOKWWQGSM>1BBDZP0158MKOSW9;<7D@FT^213>OIA]U;?:5FNHV\411<AGC_S=;8;HLJPZ61?2CEEYQ?769JJLRX81=0ECG[_1;4?LHN\V:J;6GAIU]3F2=NF@^T<N94IOKW[5B03@DBXR>J7:KMMQY7N>1BBDZP1158MKOSW8;<7D@FT^313>OIA]U:?:5FNHV\511<AGC_S<;8;HLJPZ71?2CEEYQ>769JJLRX91=0ECG[_0;4?LHN\V;J;6GAIU]2F2=NF@^T=N94IOKW[4B03@DBXR?J7:KMMQY6N>1BBDZP2158MKOSW;;<7D@FT^013>OIA]U9?:5FNHV\611<AGC_S?;8;HLJPZ41?2CEEYQ=769JJLRX:1=0ECG[_3;4?LHN\V8J;6GAIU]1F2=NF@^T>N94IOKW[7B03@DBXR<J7:KMMQY5N>1BBDZP3158MKOSW:;<7D@FT^113>OIA]U8?:5FNHV\711<AGC_S>;8;HLJPZ51?2CEEYQ<769JJLRX;1=0ECG[_2;4?LHN\V9J;6GAIU]0F2=NF@^T?N94IOKW[6B03@DBXR=J7:KMMQY4N?1BBDZPA79JJLRXJ;1GE?5CO79OKDBBL>1GCJGLAM68HPR6<2F^X?:4LTV00>JR\=<0@XZ;_E48HPR3WE?0A^I@N49NQ]E^k2Gjfb|Yesqjkke<E`dd~[k}shmm6>H7:2D:86@>0768J460<2D:<5:4N02:7>H69=1E=<>;;O3251=I988?7C?>359M54233G;:995A1047?K76?=1E=<6;;O32=6=I9;>0B<<?4:L2642<F88986@>2268J443<2D:>8:4N0050>H6:>>0B<<74:L26<5<F89?7C?<059M56733G;8>95A1217?K74<=1E=>;;;O3021=I9:=?7C?<859M56?43G;?86@>4168J426<2D:8?:4N0600>H6<?90B<;<;O357>H6?=1E=:9<;O3;7>H61:1E>==4N330?K45;2D9?>5A2518J7343G8=?6@=729M6=5<F;387C=?3:L056=I;;90B>=<;O177>H4=:1E?;=4N250?K5?;2D85>5A4118J1743G>9?6@;329M015<F=?87C:93:L736=I<180B8<4N608J<`<FKUIY^^FN^RQKUU03GO_[B\D1:M1?JM63Y>0\L\[a:RJJZDR[@NSn6^FN^@VWKGJM:1[^H?4Q09Qa>TFEK;=S^=9_R15e>TBIMUME_][c:PFEAYPAM^CSLm4RDCG[ROC\AUI=6]>3:QJIZEHDECXEB@PCIG@O3=TG\XHI:5\RWCO[D1<[[\J@RL;;RQQE1=T[[H?7YW_E208Q5)`zo$yj"ilx/aoo})JpfxT~iQnup\cfYg{:;<=Q]erwop4553\:$kh!rg-dg}(ddbr$Aua}_sf\tkruWniTtb|?013\V`urd};8>6[?/fpe*w`(ojr%oaew/LzlvZtcWyd~Ril_ymq4565W[oxyaz>339V4*aun'xm#jmw.bnh|*Kg{UyhR~ats]dgZ~hz9:;?R\jstnw564<]9%l~k }f.e`|+ekcq%Ftb|Pre]sjqtXojUsc>?05]Qavsk|8997X> gsd-vc)`kq$h`fv Mymq[wbXxg~ySjmPxnp3453XZly~`y?<2:W3+bta&{l$knv!cmi{+H~hzVxoS}`{r^e`[}iu89:=S_k|umv277=R8&myj#|i/fa{*fjlp&GscQ}d^rmpwY`kVrd~=>?7^Pfwpjs9:80Y=!hrg,qb*adp'iggu!Bxnp\swYwf}xTknQwos2345YUmzgx<==;T2,cw`)zo%lou lljz,I}iuW~xT|cz}_fa\|jt789;T^h}zlu306>S7'nxm"h gbz-gim'Drd~Ry}_qlwvZadWqey<=>=_Sgpqir6;;1^<"i}f/pe+be&jf`t"Cwos]tvZvi|{UloRv`r1237ZTb{|f=><4U1-dvc(un&mht#mcky-N|jtX{U{by|Pgb]{kw678=UYi~{ct011?P6(o{l%~k!hcy,`hn~(EqeySz|Ppovq[beXpfx;<=;PRdqvhq74:2_;#j|i.sd,cf~)keas#@v`r^uq[uhszVmhSua}0125[Wct}e~:??5Z0.eqb+ta'nis"nbdx.O{kwYpzVzexQhc^zlv567?VXnxb{1338Q5)`zo$yj"ilx/aoo})ulVzexQmio>3:77<]9%l~k }f.e`|+ekcq%yhR~ats]amk:66;;0Y=!hrg,qb*adp'iggu!}d^rmpwYeag692??4U1-dvc(un&mht#mcky-q`Zvi|{Uiec2<>338Q5)`zo$yj"ilx/aoo})ulVzexQmio>7:77<]9%l~k }f.e`|+ekcq%yhR~ats]amk:26;;0Y=!hrg,qb*adp'iggu!}d^rmpwYeag6=2??4U1-dvc(un&mht#mcky-q`Zvi|{Uiec28>338Q5)`zo$yj"ilx/aoo})ulVzexQmio>;:76<]9%l~k }f.e`|+ekcq%yhR~ats]amkY7:91^<"i}f/pe+be&jf`t"|k_qlwvZdnfV;9<6[?/fpe*w`(ojr%oaew/sf\tkruWkceS?<?;T2,cw`)zo%lou lljz,vaYwf}xTnd`P3328Q5)`zo$yj"ilx/aoo})ulVzexQmio]765=R8&myj#|i/fa{*fjlp&xoS}`{r^`jjZ3582_;#j|i.sd,cf~)keas#jPpovq[goiW?8;7X> gsd-vc)`kq$h`fv re]sjqtXj`dT;?>4U1-dvc(un&mht#mcky-q`Zvi|{UiecQ7279V4*aun'xm#jmw.bnh|*tcWyd~Rlfn^zlv5678;=0Y=!hrg,qb*adp'iggu!}d^rmpwYeagUsc>?01312>S7'nxm"h gbz-gim'{nT|cz}_ckm[}iu89::>:5Z0.eqb+ta'nis"nbdx.pg[uhszVhbbRv`r12354413\:$kh!rg-dg}(ddbr$~iQnup\flhXpfx;<=<=7:W3+bta&{l$knv!cmi{+wbXxg~ySoga_ymq45659;<0Y=!hrg,qb*adp'iggu!}d^rmpwYeagUsc>?0204?P6(o{l%~k!hcy,`hn~(zmU{by|Pbhl\|jt78999>;5Z0.eqb+ta'nis"nbdx.pg[uhszVhbbRv`r123071<]9%l~k }f.e`|+ekcq%yhR~ats]amkYg{:;<9?=6:W3+bta&{l$knv!cmi{+wbXxg~ySoga_ymq4562:>1^<"i}f/pe+be&jf`t"|k_qlwvZdnfVrd~=>?5005?P6(o{l%~k!hcy,`hn~(zmU{by|Pbhl\|jt789<946[?/fpe*w`(ojr%oaew/sf\tkruWkceSua}012554403\:$kh!rg-dg}(ddbr$~iQnup\flhXpfx;<=8=2c9V4*aun'xm#jmw.bnh|*tcWyd~Rlfn^zlv567>Vhoh=<9;T2,cw`)zo%lou lljz,vaYwf}xTnd`Pxnp34515?2_;#j|i.sd,cf~)keas#jPpovq[goiWqey<=>81328Q5)`zo$yj"ilx/aoo})ulVzexQhc=2=65=R8&myj#|i/fa{*fjlp&xoS}`{r^e`848582_;#j|i.sd,cf~)keas#jPpovq[be;:78;7X> gsd-vc)`kq$h`fv re]sjqtXoj682?>4U1-dvc(un&mht#mcky-q`Zvi|{Ulo1:1219V4*aun'xm#jmw.bnh|*tcWyd~Ril<4<14>S7'nxm"h gbz-gim'{nT|cz}_fa?2;473\:$kh!rg-dg}(ddbr$~iQnup\cf:06;:0Y=!hrg,qb*adp'iggu!}d^rmpwY`k525=k5Z0.eqb+ta'nis"nbdx.pg[uhszVmhS=?i;T2,cw`)zo%lou lljz,vaYwf}xTknQ>1g9V4*aun'xm#jmw.bnh|*tcWyd~Ril_33e?P6(o{l%~k!hcy,`hn~(zmU{by|Pgb]05c=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[17a3\:$kh!rg-dg}(ddbr$~iQnup\cfY29o1^<"i}f/pe+be&jf`t"|k_qlwvZadW?;m7X> gsd-vc)`kq$h`fv re]sjqtXojU<=k5Z0.eqb+ta'nis"nbdx.pg[uhszVmhS5<9;T2,cw`)zo%lou lljz,vaYwf}xTknQnssgd8585>2_;#j|i.sd,cf~)keas#jPpovq[beXizxnk1?1279V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqab:56;<0Y=!hrg,qb*adp'iggu!}d^rmpwY`kVkx~hi33?05?P6(o{l%~k!hcy,`hn~(zmU{by|Pgb]bwwc`4=49:6[?/fpe*w`(ojr%oaew/sf\tkruWniTm~|jg=7=63=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[duumn6=2?84U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde?3;413\:$kh!rg-dg}(ddbr$~iQnup\cfYf{{ol050=5:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfcZ65=2_;#j|i.sd,cf~)keas#jPpovq[beXizxnkR?=5:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfcZ45=2_;#j|i.sd,cf~)keas#jPpovq[beXizxnkR==5:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfcZ25=2_;#j|i.sd,cf~)keas#jPpovq[beXizxnkR;=5:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfcZ05=2_;#j|i.sd,cf~)keas#jPpovq[beXizxnkR9=5:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfcZ>512_;#j|i.sd,cf~)keas#jPpovq[beXizxnkRj><1<1=>S7'nxm"h gbz-gim'{nT|cz}_fa\evtboVn:0<0=9:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfcZb64;4956[?/fpe*w`(ojr%oaew/sf\tkruWniTm~|jg^f2868512_;#j|i.sd,cf~)keas#jPpovq[beXizxnkRj><5<1=>S7'nxm"h gbz-gim'{nT|cz}_fa\evtboVn:080=9:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfcZb64?4956[?/fpe*w`(ojr%oaew/sf\tkruWniTm~|jg^f2828512_;#j|i.sd,cf~)keas#jPpovq[beXizxnkRj><9<1<>S7'nxm"h gbz-gim'{nT|cz}_fa\evtboVn:S=<7;T2,cw`)zo%lou lljz,vaYwf}xTknQnssgd[a7X9;20Y=!hrg,qb*adp'iggu!}d^rmpwY`kVkx~hiPd0]16==R8&myj#|i/fa{*fjlp&xoS}`{r^e`[duumnUo=R==8:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfcZb6W=837X> gsd-vc)`kq$h`fv re]sjqtXojUjkh_e3\17><]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmTh<Q9299V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqabYc9V=946[?/fpe*w`(ojr%oaew/sf\tkruWniTm~|jg^f2[=423\:$kh!rg-dg}(ddbr$~iQnup\cfYg{:;<=<:;T2,cw`)zo%lou lljz,vaYwf}xTknQwos2344423\:$kh!rg-dg}(ddbr$~iQnup\cfYg{:;<?<:;T2,cw`)zo%lou lljz,vaYwf}xTknQwos2346423\:$kh!rg-dg}(ddbr$~iQnup\cfYg{:;<9<:;T2,cw`)zo%lou lljz,vaYwf}xTknQwos2340423\:$kh!rg-dg}(ddbr$~iQnup\cfYg{:;<;<:;T2,cw`)zo%lou lljz,vaYwf}xTknQwos2342463\:$kh!rg-dg}(ddbr${Qnup\flh;878:7X> gsd-vc)`kq$h`fv ws]sjqtXj`d7=3<>;T2,cw`)zo%lou lljz,swYwf}xTnd`32?02?P6(o{l%~k!hcy,`hn~({U{by|Pbhl?7;463\:$kh!rg-dg}(ddbr${Qnup\flh;<78:7X> gsd-vc)`kq$h`fv ws]sjqtXj`d793<>;T2,cw`)zo%lou lljz,swYwf}xTnd`36?02?P6(o{l%~k!hcy,`hn~({U{by|Pbhl?3;463\:$kh!rg-dg}(ddbr${Qnup\flh;078;7X> gsd-vc)`kq$h`fv ws]sjqtXj`dT<?>4U1-dvc(un&mht#mcky-tvZvi|{UiecQ>219V4*aun'xm#jmw.bnh|*quWyd~Rlfn^014>S7'nxm"h gbz-gim'~xT|cz}_ckm[6473\:$kh!rg-dg}(ddbr${Qnup\flhX<;:0Y=!hrg,qb*adp'iggu!xr^rmpwYeagU>>=5Z0.eqb+ta'nis"nbdx.uq[uhszVhbbR8=0:W3+bta&{l$knv!cmi{+rtXxg~ySoga_603?P6(o{l%~k!hcy,`hn~({U{by|Pbhl\<70<]9%l~k }f.e`|+ekcq%|~R~ats]amkYg{:;<=<8;T2,cw`)zo%lou lljz,swYwf}xTnd`Pxnp34566:?1^<"i}f/pe+be&jf`t"y}_qlwvZdnfVrd~=>?1358Q5)`zo$yj"ilx/aoo})pzVzexQmio]{kw6788;9:6[?/fpe*w`(ojr%oaew/vp\tkruWkceSua}012162=R8&myj#|i/fa{*fjlp&}yS}`{r^`jjZ~hz9:;><<9;T2,cw`)zo%lou lljz,swYwf}xTnd`Pxnp34555?2_;#j|i.sd,cf~)keas#z|Ppovq[goiWqey<=><2348Q5)`zo$yj"ilx/aoo})pzVzexQmio]{kw678=8<7X> gsd-vc)`kq$h`fv ws]sjqtXj`dTtb|?016263=R8&myj#|i/fa{*fjlp&}yS}`{r^`jjZ~hz9:;9?94U1-dvc(un&mht#mcky-tvZvi|{UiecQwos234075>2_;#j|i.sd,cf~)keas#z|Ppovq[goiWqey<=>9299V4*aun'xm#jmw.bnh|*quWyd~Rlfn^zlv567>8;9;6[?/fpe*w`(ojr%oaew/vp\tkruWkceSua}012567d<]9%l~k }f.e`|+ekcq%|~R~ats]amkYg{:;<;Qmde212>S7'nxm"h gbz-gim'~xT|cz}_ckm[}iu89:<>:5Z0.eqb+ta'nis"nbdx.uq[uhszVhbbRv`r12334473\:$kh!rg-dg}(ddbr${Qnup\cf:76;:0Y=!hrg,qb*adp'iggu!xr^rmpwY`k5;5>=5Z0.eqb+ta'nis"nbdx.uq[uhszVmh0?0=0:W3+bta&{l$knv!cmi{+rtXxg~ySjm33?03?P6(o{l%~k!hcy,`hn~({U{by|Pgb>7:76<]9%l~k }f.e`|+ekcq%|~R~ats]dg939:91^<"i}f/pe+be&jf`t"y}_qlwvZad4?49<6[?/fpe*w`(ojr%oaew/vp\tkruWni7;3<?;T2,cw`)zo%lou lljz,swYwf}xTkn27>0d8Q5)`zo$yj"ilx/aoo})pzVzexQhc^22b>S7'nxm"h gbz-gim'~xT|cz}_fa\54`<]9%l~k }f.e`|+ekcq%|~R~ats]dgZ46n2_;#j|i.sd,cf~)keas#z|Ppovq[beX;8l0Y=!hrg,qb*adp'iggu!xr^rmpwY`kV>:j6[?/fpe*w`(ojr%oaew/vp\tkruWniT9<h4U1-dvc(un&mht#mcky-tvZvi|{UloR8>f:W3+bta&{l$knv!cmi{+rtXxg~ySjmP70d8Q5)`zo$yj"ilx/aoo})pzVzexQhc^:12>S7'nxm"h gbz-gim'~xT|cz}_fa\evtbo5:5>;5Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef>2:70<]9%l~k }f.e`|+ekcq%|~R~ats]dgZgtzlm7>3<9;T2,cw`)zo%lou lljz,swYwf}xTknQnssgd8685>2_;#j|i.sd,cf~)keas#z|Ppovq[beXizxnk1:1279V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqab:26;<0Y=!hrg,qb*adp'iggu!xr^rmpwY`kVkx~hi36?05?P6(o{l%~k!hcy,`hn~({U{by|Pgb]bwwc`4>49:6[?/fpe*w`(ojr%oaew/vp\tkruWniTm~|jg=:=60=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnU;>85Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]260=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnU9>85Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]060=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnU?>85Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]660=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnU=>85Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]460=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnU3>45Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]g5969:01^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQk1=3=6<=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnUo=1<1289V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabYc9595>45Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]g5929:01^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQk1=7=6<=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnUo=181289V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabYc95=5>45Z0.eqb+ta'nis"nbdx.uq[uhszVmhSl}}ef]g59>9:11^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyijQk1^21<>S7'nxm"h gbz-gim'~xT|cz}_fa\evtboVn:S<<7;T2,cw`)zo%lou lljz,swYwf}xTknQnssgd[a7X:;20Y=!hrg,qb*adp'iggu!xr^rmpwY`kVkx~hiPd0]06==R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnUo=R:=8:W3+bta&{l$knv!cmi{+rtXxg~ySjmParpfcZb6W<837X> gsd-vc)`kq$h`fv ws]sjqtXojUjkh_e3\27><]9%l~k }f.e`|+ekcq%|~R~ats]dgZgtzlmTh<Q8299V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabYc9V2996[?/fpe*w`(ojr%oaew/vp\tkruWniTtb|?01211>S7'nxm"h gbz-gim'~xT|cz}_fa\|jt789;996[?/fpe*w`(ojr%oaew/vp\tkruWniTtb|?01011>S7'nxm"h gbz-gim'~xT|cz}_fa\|jt7899996[?/fpe*w`(ojr%oaew/vp\tkruWniTtb|?01611>S7'nxm"h gbz-gim'~xT|cz}_fa\|jt789?996[?/fpe*w`(ojr%oaew/vp\tkruWniTtb|?01411>S7'nxm"h gbz-gim'~xT|cz}_fa\|jt789=8<6[?/fpe*w`(oe:%~i!hr0,qbr`s'Dg~tR\NM^PG[@HXN^L_><<i;T2,cw`)zo%l`= }d.eq5+tao~$A`{w_SCN[WC@G\^TIC?>2e9V4*aun'xm#jb?.sf,cw7)zo}mx"mzrs]escrX{}ki1>12e9V4*aun'xm#jb?.sf,cw7)zo}mx"mzrs]escrX{}ki1?12b9V4*aun'xm#jb?.sf,cw7)zo}mx"mzrs]escrX{}kiR>=c:W3+bta&{l$ka>!re-dv4(un~l#n{}r^dtbqYt|h~nS<=:;T2,cw`)zo%l`= }d.eq5+tao~$ox|}_guepZusi}oTaxv?013?4;513\:$kh!rg-dh5(ul&my=#|iwgv,gptuWo}mxR}{aug\ip~789;7<3?<5:W3+bta&{l$ka>!re-dv4(un~l#n{}r^dtbqYt|h~nS`{w01228484>2_;#j|i.sd,ci6)zm%l~< }fvdw+fsuzVl|jyQ|t`vf[hs89::0<0>299V4*aun'xm#jb?.sf,cw7)zo}mx"kbpu{\br`sWoh9;6[?/fpe*w`(oe:%~i!hr0,qbr`s'lg{xtQiwgv\m7`<]9%l~k }f.eo4+tc'nx:"hxfu-fiur~Wo}mxRgPmtz3456482_;#j|i.sd,ci6)zm%l~< }fvdw+`kw|pUm{kzPi^ov|56788827X> gsd-vc)`d9$yh"i}ar,qwqu(k9%hm|vndv?4;4>3\:$kh!rg-dh5(ul&mym~ }suq,g5)di{xrbhz31?0:?P6(o{l%~k!hl1,q`*auiz$yy} c1-`ewt~fl~7>3<6;T2,cw`)zo%l`= }d.eqev(u{}y$o=!laspzj`r;;78m7X> gsd-vc)`d9$yh"i}ar,qwqu(k9%laxv!glY3Y+aj9'g:>k5Z0.eqb+ta'nf;"j gscp*wus{&i;#jczx/en_4[)ody%a~<i;T2,cw`)zo%l`= }d.eqev(u{}y$o=!hmtz-ch]5U'mf#c|2g9V4*aun'xm#jb?.sf,cwgt&{y"m?/fov|+ajS:W%k`}!mr0e?P6(o{l%~k!hl1,q`*auiz$yy} c1-dip~)odQ?Q#ibs/op66=R8&myj#|i/fn3*wb(o{kx"}{s.a3+s7;87887X> gsd-vc)`d9$yh"i}ar,qwqu(k9%}=1?1229V4*aun'xm#jb?.sf,cwgt&{y"m?/w3?6;443\:$kh!rg-dh5(ul&mym~ }suq,g5)q9595>>5Z0.eqb+ta'nf;"j gscp*wus{&i;#{?34?0a?P6(o{l%~k!hl1,q`*auiz$yy} c1-u5Z6Xign;<=>>2c9V4*aun'xm#jb?.sf,cwgt&{y"m?/w3\5Zgil9:;<<<m;T2,cw`)zo%l`= }d.eqev(u{}y$o=!y1^0\ekb789::>o5Z0.eqb+ta'nf;"j gscp*wus{&i;#{?P3^cm`567888i7X> gsd-vc)`d9$yh"i}ar,qwqu(k9%}=R:Pnnv34566:01^<"i}f/pe+bj7&{n$ko|.sqww*e6'jky~t`jt=2=6<=R8&myj#|i/fn3*wb(o{kx"}{s.a2+fguzpdnx1?1289V4*aun'xm#jb?.sf,cwgt&{y"m>/bcqv|hb|585>45Z0.eqb+ta'nf;"j gscp*wus{&i:#no}rxlfp959:o1^<"i}f/pe+bj7&{n$ko|.sqww*e6'ng~t#ib[1_-ch7)e88m7X> gsd-vc)`d9$yh"i}ar,qwqu(k8%laxv!glY2Y+aj{'gx>k5Z0.eqb+ta'nf;"j gscp*wus{&i:#jczx/en_7[)ody%a~<i;T2,cw`)zo%l`= }d.eqev(u{}y$o<!hmtz-ch]4U'mf#c|2g9V4*aun'xm#jb?.sf,cwgt&{y"m>/fov|+ajS=W%k`}!mr00?P6(o{l%~k!hl1,q`*auiz$yy} c0-u5969::1^<"i}f/pe+bj7&{n$ko|.sqww*e6';7=3<<;T2,cw`)zo%l`= }d.eqev(u{}y$o<!y1=0=66=R8&myj#|i/fn3*wb(o{kx"}{s.a2+s7;;7887X> gsd-vc)`d9$yh"i}ar,qwqu(k8%}=1:12c9V4*aun'xm#jb?.sf,cwgt&{y"m>/w3\4Zgil9:;<<<m;T2,cw`)zo%l`= }d.eqev(u{}y$o<!y1^3\ekb789::>o5Z0.eqb+ta'nf;"j gscp*wus{&i:#{?P2^cm`567888i7X> gsd-vc)`d9$yh"i}ar,qwqu(k8%}=R=Paof34566:k1^<"i}f/pe+bj7&{n$ko|.sqww*e6';T8R``t12344473\:$kh!rg-dh5(ul&mym~ }suq,gjkw8;:0Y=!hrg,qb*ak8'xo#j|ns/pppv)dgdz:>45Z0.eqb+ta'nf;"j gscp*wus{&xjaRkbpu{\bgYn;91^<"i}f/pe+bj7&{n$ko|.sqww*tfeVof|ywPfc]j[jt789:8=6[?/fpe*w`(oe:%~i!hr`q-vvrt'{kfShctx]efZoXg{:;<=?=3:W3+bta&{l$ka>!re-qtkru'DidyczPcnwmp72<]9%l~k }f.eo4+tc'{zex!BcnwmpZeh}g~:>95Z0.eqb+ta'nf;"j rqlwv*Kdg|dSnaznu010>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|:8?7X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{4368Q5)`zo$yj"ic0/pg+wvi|{%Fob{at^alqkr2:=1^<"i}f/pe+bj7&{n$~}`{r.O`kphsWje~by8=4:W3+bta&{l$ka>!re-qtkru'DidyczPcnwmp2433\:$kh!rg-dh5(ul&x{by| MbmvjqYdg|d4?74U1-dvc(un&mg<#|k/srmpw)JkfexRm`uov\g|:76;i0Y=!hrg,qb*ak8'xo#~ats-Ngjsi|VidyczPcx>3:Zts:01^<"i}f/pe+bj7&{n$~}`{r.O`kphsWje~byQly=3=6f=R8&myj#|i/fn3*wb(zyd~"Clotlw[firf}Uhu1?1_sv1=>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|Vir0?0=c:W3+bta&{l$ka>!re-qtkru'DidyczPcnwmpZe~4;4T~y<6;T2,cw`)zo%l`= }d.psjqt(Eje~byQlotlw[f;;78h7X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{_b{?7;Yu|;30Y=!hrg,qb*ak8'xo#~ats-Ngjsi|VidyczPcx>7:7e<]9%l~k }f.eo4+tc'{zex!BcnwmpZeh}g~Tot2;>^pw6<=R8&myj#|i/fn3*wb(zyd~"Clotlw[firf}Uhu1;12b9V4*aun'xm#jb?.sf,vuhsz&Ghcx`{_bmvjqYdq5?5Sz=9:W3+bta&{l$ka>!re-qtkru'DidyczPcnwmpZe~4?49o6[?/fpe*w`(oe:%~i!}povq+Heh}g~Tob{at^az838Xz}827X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{_b{?3;4d3\:$kh!rg-dh5(ul&x{by| MbmvjqYdg|dSnw37?]qp7g<]9%l~k }f.eo4+tc'{zex!BcnwmpZeh}g~Ttb|30?0b?P6(o{l%~k!hl1,q`*twf}x$Anaznu]`kphsWqey0<0=a:W3+bta&{l$ka>!re-qtkru'DidyczPcnwmpZ~hz585>l5Z0.eqb+ta'nf;"j rqlwv*Kdg|dSnaznu]{kw:46;k0Y=!hrg,qb*ak8'xo#~ats-Ngjsi|VidyczPxnp?0;4f3\:$kh!rg-dh5(ul&x{by| MbmvjqYdg|dSua}<4<1e>S7'nxm"h gm2-va)uxg~y#@m`uov\gjsi|Vrd~1812`9V4*aun'xm#jb?.sf,vuhsz&Ghcx`{_bmvjqYg{6<2?o4U1-dvc(un&mg<#|k/srmpw)JkfexRm`uov\|jt;078o7X> gsd-vc)`d9$yh"|nup,Ifirf}Uhcx`{_ymq8=8Xz};m7X> gsd-vc)`d9$yh"|nup,gjsi|5:5=k5Z0.eqb+ta'nf;"j rqlwv*eh}g~7=3?i;T2,cw`)zo%l`= }d.psjqt(kfex1<11g9V4*aun'xm#jb?.sf,vuhsz&idycz33?3e?P6(o{l%~k!hl1,q`*twf}x$ob{at=6=5c=R8&myj#|i/fn3*wb(zyd~"m`uov?1;7a3\:$kh!rg-dh5(ul&x{by| cnwmp9099o1^<"i}f/pe+bj7&{n$~}`{r.alqkr;?7;m7X> gsd-vc)`d9$yh"|nup,gjsi|525=h5Z0.eqb+ta'nf;"j rqlwv*eh}g~T<<k4U1-dvc(un&mg<#|k/srmpw)dg|dS<?j;T2,cw`)zo%l`= }d.psjqt(kfexR<>e:W3+bta&{l$ka>!re-qtkru'je~byQ<1d9V4*aun'xm#jb?.sf,vuhsz&idyczP40g8Q5)`zo$yj"ic0/pg+wvi|{%hcx`{_43f?P6(o{l%~k!hl1,q`*twf}x$ob{at^42a>S7'nxm"h gm2-va)uxg~y#naznu]45`=R8&myj#|i/fn3*wb(zyd~"m`uov\<74<]9%l~k }f.eo4+tc'{zex!lotlw[a7;87897X> gsd-vc)`d9$yh"|nup,gjsi|Vn:0<0=2:W3+bta&{l$ka>!re-qtkru'je~byQk1=0=67=R8&myj#|i/fn3*wb(zyd~"m`uov\`4:46;80Y=!hrg,qb*ak8'xo#~ats-`kphsWm;783<=;T2,cw`)zo%l`= }d.psjqt(kfexRj><4<16>S7'nxm"h gm2-va)uxg~y#naznu]g5909:;1^<"i}f/pe+bj7&{n$~}`{r.alqkrXl86<2?<4U1-dvc(un&mg<#|k/srmpw)dg|dSi?38?02?P6(o{l%~k!hl1,q`*twf}x$ob{at^f2[5463\:$kh!rg-dh5(ul&x{by| cnwmpZb6W88:7X> gsd-vc)`d9$yh"|nup,gjsi|Vn:S?<>;T2,cw`)zo%l`= }d.psjqt(kfexRj>_202?P6(o{l%~k!hl1,q`*twf}x$ob{at^f2[1463\:$kh!rg-dh5(ul&x{by| cnwmpZb6W<8:7X> gsd-vc)`d9$yh"|nup,gjsi|Vn:S;<>;T2,cw`)zo%l`= }d.psjqt(kfexRj>_602?P6(o{l%~k!hl1,q`*twf}x$ob{at^f2[=433\:$kh!rg-dh5(ul&x{by| cnwmpZhh|9:;=>h4U1-dvc(un&mg<#y}/fubw+awn'}y|k!Baef\`l`aWyd~R~nd^cg`5678Vir0=0<f:W3+bta&{l$ka>!ws-dsdu)oyl%{~i/Lcg`ZbnnoU{by|Pp`f\eab789:Tot2>>2d8Q5)`zo$yj"ic0/uq+bqf{'m{j#y}pg-NeabXl`lmS}`{r^rb`Zgcl9:;<Rmv<3<0b>S7'nxm"h gm2-sw)`hy%k}h!wsre+HgclVnbjkQnup\tdbXimn;<=>Pcx>0:6`<]9%l~k }f.eo4+qu'n}j#if/uqtc)JimnThdhi_qlwvZvflVkoh=>?0^az8184n2_;#j|i.sd,ci6){%l{l}!gqd-swva'DkohRjffg]sjqtXxhnTmij?012\g|:26:l0Y=!hrg,qb*ak8'}y#jyns/esb+quxo%FmijPdhde[uhszVzjhRokd1234Ze~4?48j6[?/fpe*w`(oe:%{!hw`q-cu`){zm#@okd^fjbcYwf}xT|ljPaef3456Xkp6<2>h4U1-dvc(un&mg<#y}/fubw+awn'}y|k!Baef\`l`aWyd~R~nd^cg`5678Vir050;0:W3+bta&{l$ka>!ws-dsdu)oyl%{~i/Lcg`ZbnnoU{by|Pp`f\eab789:T`xz31?63?P6(o{l%~k!hl1,tv*apiz$l|k xrqd,IdbcWmcmjR~ats]seaYflm:;<=Qcuu>1:16<]9%l~k }f.eo4+qu'n}j#if/uqtc)JimnThdhi_qlwvZvflVkoh=>?0^nvp959<91^<"i}f/pe+bj7&~x$kzo|.fre*rtwn&GjhiQkigd\tkruWykoSljk0123[iss4=4?<6[?/fpe*w`(oe:%{!hw`q-cu`){zm#@okd^fjbcYwf}xT|ljPaef3456Xd|~793:?;T2,cw`)zo%l`= xr.etev(`xo$|~}h M`fg[aoanVzexQae]b`a6789Ugyy29>528Q5)`zo$yj"ic0/uq+bqf{'m{j#y}pg-NeabXl`lmS}`{r^rb`Zgcl9:;<Rbzt=5=05=R8&myj#|i/fn3*rt(o~kx"j~i.vpsb*KflmUoekhPpovq[ugcWhno<=>?_mww8=8382_;#j|i.sd,ci6){%l{l}!gqd-swva'DkohRjffg]sjqtXxhnTmij?012\hpr;17>;7X> gsd-vc)`d9$|~"ixar,dtc(pzyl$Aljk_ekebZvi|{U{miQnde2345Yg{6829>4U1-dvc(un&mg<#y}/fubw+awn'}y|k!Baef\`l`aWyd~R~nd^cg`5678Vrd~1:1419V4*aun'xm#jb?.vp,crgt&nzm"z|f.Ob`aYcaolT|cz}_qcg[dbc89:;Sua}<4<74>S7'nxm"h gm2-sw)`hy%k}h!wsre+HgclVnbjkQnup\tdbXimn;<=>Pxnp?2;273\:$kh!rg-dh5(pz&m|m~ hpg,tvu`(EhnoSigif^rmpwYwimUjhi>?01]{kw:06=:0Y=!hrg,qb*ak8'}y#jyns/esb+quxo%FmijPdhde[uhszVzjhRokd1234Z~hz5258=5Z0.eqb+ta'nf;"z| gvcp*bva&~x{j"Cnde]gmc`Xxg~yS}ok_`fg4567Wqey040=f:W3+bta&{l$ka>!ws-dsdu)oyl%{~i/ekebZvi|{U{mi2<>3d8Q5)`zo$yj"ic0/uq+bqf{'m{j#y}pg-gmc`Xxg~yS}ok<5<1b>S7'nxm"h gm2-sw)`hy%k}h!wsre+aoanVzexQae>6:7`<]9%l~k }f.eo4+qu'n}j#if/uqtc)caolT|cz}_qcg8385n2_;#j|i.sd,ci6){%l{l}!gqd-swva'mcmjR~ats]sea:06;l0Y=!hrg,qb*ak8'}y#jyns/esb+quxo%oekhPpovq[ugc4149j6[?/fpe*w`(oe:%{!hw`q-cu`){zm#igif^rmpwYwim622?k4U1-dvc(un&mg<#y}/fubw+awn'}y|k!kigd\tkruWykoS><j;T2,cw`)zo%l`= xr.etev(`xo$|~}h dhde[uhszVzjhR:=e:W3+bta&{l$ka>!ws-dsdu)oyl%{~i/ekebZvi|{U{miQ:2d9V4*aun'xm#jb?.vp,crgt&nzm"z|f.fjbcYwf}xT|ljP63g8Q5)`zo$yj"ic0/uq+bqf{'m{j#y}pg-gmc`Xxg~yS}ok_60f?P6(o{l%~k!hl1,tv*apiz$l|k xrqd,`l`aWyd~R~nd^:1a>S7'nxm"h gm2-sw)`hy%k}h!wsre+aoanVzexQae]:72=R8&myj#|i/fn3*rt(o~kx"j~i.vpsb*bnnoU{by|Pp`f\eab789:7?3=8;T2,cw`)zo%l`= xr.etev(`xo$|~}h dhde[uhszVzjhRokd1234929;>1^<"i}f/pe+bj7&~x$kzo|.fre*rtwn&nbjkQnup\tdbXimn;<=>35?14?P6(o{l%~k!hl1,tv*apiz$l|k xrqd,`l`aWyd~R~nd^cg`56785<5?:5Z0.eqb+ta'nf;"z| gvcp*bva&~x{j"jffg]sjqtXxhnTmij?012?3;503\:$kh!rg-dh5(pz&m|m~ hpg,tvu`(l`lmS}`{r^rb`Zgcl9:;<161369V4*aun'xm#jb?.vp,crgt&nzm"z|f.fjbcYwf}xT|ljPaef3456;178j7X> gsd-vc)`d9$|~"ixar,dtc(pzyl$|ah_gwohZo4:2_;#j|i.sd,ci6){%l{l}!gqd-swva'yxdkRhzlm]j[hs89:8?95Z0.eqb+ta'nf;"z| gvcp*bva&~x{j"~}of]eqijXaVg~t=>?30000>S7'nxm"h gm2-sw)`hy%k}h!wsre+uthoVl~`aQf_lw{45649:987X> gsd-vc)`d9$|~"ixar,dtc(pzyl$|ah_gwohZoXe|r;<==8339V4*aun'xm#jb?.vp,crgt&nzm"z|f.rqkbYa}efTeR``t12357?<]9%l~k }f.eo4+qu'n}j#y|tr-`5*efz{seiy2?>3;8Q5)`zo$yj"ic0/uq+bqf{'}xx~!l1.abvwim}6:2?74U1-dvc(un&mg<#y}/fubw+qt|z%h="mnrs{maq:56;30Y=!hrg,qb*ak8'}y#jyns/uppv)d9&ij~waeu>0:7`<]9%l~k }f.eo4+qu'n}j#y|tr-`5*aj}q$laV>R.fo2*h75n2_;#j|i.sd,ci6){%l{l}!wrvp+f7(ods"jcT1\,div(j{;l0Y=!hrg,qb*ak8'}y#jyns/uppv)d9&mfyu hmZ0^*bkt&dy9j6[?/fpe*w`(oe:%{!hw`q-svrt'j;$k`{w.foX7X(`ez$f?h4U1-dvc(un&mg<#y}/fubw+qt|z%h="ibuy,di^2Z&ngx"`}=3:W3+bta&{l$ka>!ws-dsdu)z~x#n? v0>3:75<]9%l~k }f.eo4+qu'n}j#y|tr-`5*p64849?6[?/fpe*w`(oe:%{!hw`q-svrt'j;$z<2=>318Q5)`zo$yj"ic0/uq+bqf{'}xx~!l1.t28685;2_;#j|i.sd,ci6){%l{l}!wrvp+f7(~86?2?l4U1-dvc(un&mg<#y}/fubw+qt|z%h="x>_1]bja6789;9n6[?/fpe*w`(oe:%{!hw`q-svrt'j;$z<Q>_`lg45679;h0Y=!hrg,qb*ak8'}y#jyns/uppv)d9&|:S?Qnne234575j2_;#j|i.sd,ci6){%l{l}!wrvp+f7(~8U8Sl`k012357d<]9%l~k }f.eo4+qu'n}j#y|tr-`5*p6W=Uecy>?0131=>S7'nxm"h gm2-sw)`hy%{~z|/b0,gdtuqgo0=0=9:W3+bta&{l$ka>!ws-dsdu)z~x#n< c`pq}kcs484956[?/fpe*w`(oe:%{!hw`q-svrt'j8$ol|}yogw878512_;#j|i.sd,ci6){%l{l}!wrvp+f4(khxyuck{<2<1b>S7'nxm"h gm2-sw)`hy%{~z|/b0,chs&ngP<P hm0,n57`<]9%l~k }f.eo4+qu'n}j#y|tr-`6*aj}q$laV?R.fop*hu5n2_;#j|i.sd,ci6){%l{l}!wrvp+f4(ods"jcT2\,div(j{;l0Y=!hrg,qb*ak8'}y#jyns/uppv)d:&mfyu hmZ1^*bkt&dy9j6[?/fpe*w`(oe:%{!hw`q-svrt'j8$k`{w.foX0X(`ez$f?=4U1-dvc(un&mg<#y}/fubw+qt|z%h>"x><1<17>S7'nxm"h gm2-sw)`hy%{~z|/b0,r4:66;90Y=!hrg,qb*ak8'}y#jyns/uppv)d:&|:0?0=3:W3+bta&{l$ka>!ws-dsdu)z~x#n< v0>0:75<]9%l~k }f.eo4+qu'n}j#y|tr-`6*p64=49n6[?/fpe*w`(oe:%{!hw`q-svrt'j8$z<Q?_`lg45679;h0Y=!hrg,qb*ak8'}y#jyns/uppv)d:&|:S<Qnne234575j2_;#j|i.sd,ci6){%l{l}!wrvp+f4(~8U9Sl`k012357d<]9%l~k }f.eo4+qu'n}j#y|tr-`6*p6W:Ujbi>?0131f>S7'nxm"h gm2-sw)`hy%{~z|/b0,r4Y3Wge<=>?1328Q5)`zo$yj"ic0/uq+bqf{'}xx~!lolr265=R8&myj#|i/fn3*rt(o~kx"z}{s.aliu4582_;#j|i.sd,ci6){%l{l}!wrvp+fijx:8o7X> gsd-vc)`d9$|~"ixar,twqu(ohl%o>!laspzj`r;878o7X> gsd-vc)`d9$|~"ixar,twqu(ohl%o>!laspzj`r;978o7X> gsd-vc)`d9$|~"ixar,twqu(ohl%o>!laspzj`r;:78o7X> gsd-vc)`d9$|~"ixar,twqu(ohl%o>!laspzj`r;;7987X> gsd-vc)`d9$|~"ixar,twqu(ohl%o>!hmtz-ch]7U'mf=#c>329V4*aun'xm#jb?.vp,crgt&~y"inf/a0+bkrp'mfW<S!glq-iv543\:$kh!rg-dh5(pz&m|m~ xsuq,cd`)k:%laxv!glY1Y+aj{'gx?>5Z0.eqb+ta'nf;"z| gvcp*rus{&mjj#m</fov|+ajS:W%k`}!mr10?P6(o{l%~k!hl1,tv*apiz$|y} g`d-g6)`e|r%k`U;]/enw+kt:>1^<"i}f/pe+bj7&~x$kzo|.vqww*afn'i8#{?30?04?P6(o{l%~k!hl1,tv*apiz$|y} g`d-g6)q95;5>:5Z0.eqb+ta'nf;"z| gvcp*rus{&mjj#m</w3?6;403\:$kh!rg-dh5(pz&m|m~ xsuq,cd`)k:%}=1=1269V4*aun'xm#jb?.vp,crgt&~y"inf/a0+s7;<78m7X> gsd-vc)`d9$|~"ixar,twqu(ohl%o>!y1^2\ekb789::>k5Z0.eqb+ta'nf;"z| gvcp*rus{&mjj#m</w3\5Zgil9:;<<<i;T2,cw`)zo%l`= xr.etev(p{}y$klh!c2-u5Z4Xign;<=>>2g9V4*aun'xm#jb?.vp,crgt&~y"inf/a0+s7X;Vkeh=>?000e?P6(o{l%~k!hl1,tv*apiz$|y} g`d-g6)q9V>Tbbz?01226f=R8&myj#|i/fn3*rt(o~kx"z}{s.pbiZgkefySk{cl^k00>S7'nxm"h gm2-sw)`hy%{~z|/scn[djjgz~Tjxbc_h]nq}67899>7X> gsd-vc)`d9$|~"ixar,twqu(zhgTmac`su]eqijXaVg~t=>?0016?P6(o{l%~k!hl1,tv*apiz$|y} r`o\eikh{}UmyabPi^llp56798837X> gsd-vc)`d9$|~"ixar,twqu(zhgTjxbc_g`\m73<]9%l~k }f.eo4+qu'n}j#y|tr-qehYa}efTe?j4U1-dvc(un&mg<#y}/fubw+qt|z%ym`Qiumn\mZkrp9:;<?k4U1-dvc(un&mg<#y}/fubw+qt|z%ym`Qiumn\mZkrp9:;<<?k;T2,cw`)zo%l`= xr.pbiZquWldTe<?i;T2,cw`)zo%l`= xr.pbiZquWldTe<Q>229V4*aun'xm#jb?.vp,suhsz&Ghcx`{_bmvjq433\:$kh!rg-dh5(pz&}{by| MbmvjqYdg|d=?:4U1-dvc(un&mg<#y}/vrmpw)JkfexRm`uov161=R8&myj#|i/fn3*rt(yd~"Clotlw[firf}9986[?/fpe*w`(oe:%{!xpovq+Heh}g~Tob{at507?P6(o{l%~k!hl1,tv*qwf}x$Anaznu]`kphs=;>0Y=!hrg,qb*ak8'}y#z~ats-Ngjsi|Vidycz9259V4*aun'xm#jb?.vp,suhsz&Ghcx`{_bmvjq15<2_;#j|i.sd,ci6){%||cz}/LalqkrXkfex5<6;T2,cw`)zo%l`= xr.usjqt(Eje~byQlotlw[f;878h7X> gsd-vc)`d9$|~"ynup,Ifirf}Uhcx`{_b{?4;Yu|;30Y=!hrg,qb*ak8'}y#z~ats-Ngjsi|VidyczPcx>2:7e<]9%l~k }f.eo4+qu'~zex!BcnwmpZeh}g~Tot2>>^pw6<=R8&myj#|i/fn3*rt(yd~"Clotlw[firf}Uhu1<12b9V4*aun'xm#jb?.vp,suhsz&Ghcx`{_bmvjqYdq585Sz=9:W3+bta&{l$ka>!ws-ttkru'DidyczPcnwmpZe~4:49o6[?/fpe*w`(oe:%{!xpovq+Heh}g~Tob{at^az868Xz}827X> gsd-vc)`d9$|~"ynup,Ifirf}Uhcx`{_b{?0;4d3\:$kh!rg-dh5(pz&}{by| MbmvjqYdg|dSnw34?]qp7?<]9%l~k }f.eo4+qu'~zex!BcnwmpZeh}g~Tot2:>3a8Q5)`zo$yj"ic0/uq+rvi|{%Fob{at^alqkrXkp6>2R|{289V4*aun'xm#jb?.vp,suhsz&Ghcx`{_bmvjqYdq5<5>n5Z0.eqb+ta'nf;"z| wqlwv*Kdg|dSnaznu]`}909W{~956[?/fpe*w`(oe:%{!xpovq+Heh}g~Tob{at^az8285k2_;#j|i.sd,ci6){%||cz}/LalqkrXkfexRmv<6<\vq4f3\:$kh!rg-dh5(pz&}{by| MbmvjqYdg|dSua}<1<1e>S7'nxm"h gm2-sw)pxg~y#@m`uov\gjsi|Vrd~1?12`9V4*aun'xm#jb?.vp,suhsz&Ghcx`{_bmvjqYg{692?o4U1-dvc(un&mg<#y}/vrmpw)JkfexRm`uov\|jt;;78j7X> gsd-vc)`d9$|~"ynup,Ifirf}Uhcx`{_ymq8185i2_;#j|i.sd,ci6){%||cz}/LalqkrXkfexRv`r=7=6d=R8&myj#|i/fn3*rt(yd~"Clotlw[firf}Usc29>3c8Q5)`zo$yj"ic0/uq+rvi|{%Fob{at^alqkrXpfx7;3<n;T2,cw`)zo%l`= xr.usjqt(Eje~byQlotlw[}iu4149h6[?/fpe*w`(oe:%{!xpovq+Heh}g~Tob{at^zlv9>9W{~:j6[?/fpe*w`(oe:%{!xpovq+firf}6;2<h4U1-dvc(un&mg<#y}/vrmpw)dg|d0<0>f:W3+bta&{l$ka>!ws-ttkru'je~by2=>0d8Q5)`zo$yj"ic0/uq+rvi|{%hcx`{<2<2b>S7'nxm"h gm2-sw)pxg~y#naznu>7:4`<]9%l~k }f.eo4+qu'~zex!lotlw8086n2_;#j|i.sd,ci6){%||cz}/bmvjq:168l0Y=!hrg,qb*ak8'}y#z~ats-`kphs4>4:j6[?/fpe*w`(oe:%{!xpovq+firf}632<k4U1-dvc(un&mg<#y}/vrmpw)dg|dS=?j;T2,cw`)zo%l`= xr.usjqt(kfexR?>e:W3+bta&{l$ka>!ws-ttkru'je~byQ=1d9V4*aun'xm#jb?.vp,suhsz&idyczP30g8Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_53f?P6(o{l%~k!hl1,tv*qwf}x$ob{at^72a>S7'nxm"h gm2-sw)pxg~y#naznu]55`=R8&myj#|i/fn3*rt(yd~"m`uov\34c<]9%l~k }f.eo4+qu'~zex!lotlw[=453\:$kh!rg-dh5(pz&}{by| cnwmpZb64949>6[?/fpe*w`(oe:%{!xpovq+firf}Uo=1?1239V4*aun'xm#jb?.vp,suhsz&idyczPd0>1:74<]9%l~k }f.eo4+qu'~zex!lotlw[a7;;7897X> gsd-vc)`d9$|~"ynup,gjsi|Vn:090=2:W3+bta&{l$ka>!ws-ttkru'je~byQk1=7=67=R8&myj#|i/fn3*rt(yd~"m`uov\`4:16;80Y=!hrg,qb*ak8'}y#z~ats-`kphsWm;7;3<=;T2,cw`)zo%l`= xr.usjqt(kfexRj><9<15>S7'nxm"h gm2-sw)pxg~y#naznu]g5Z6592_;#j|i.sd,ci6){%||cz}/bmvjqYc9V;9=6[?/fpe*w`(oe:%{!xpovq+firf}Uo=R<=1:W3+bta&{l$ka>!ws-ttkru'je~byQk1^115>S7'nxm"h gm2-sw)pxg~y#naznu]g5Z2592_;#j|i.sd,ci6){%||cz}/bmvjqYc9V?9=6[?/fpe*w`(oe:%{!xpovq+firf}Uo=R8=1:W3+bta&{l$ka>!ws-ttkru'je~byQk1^515>S7'nxm"h gm2-sw)pxg~y#naznu]g5Z>5:2_;#j|i.sd,ci6){%||cz}/bmvjqYc:5:5>?5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th?2>>308Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_e0?6;453\:$kh!rg-dh5(pz&}{by| cnwmpZb54:49>6[?/fpe*w`(oe:%{!xpovq+firf}Uo>1:1239V4*aun'xm#jb?.vp,suhsz&idyczPd3>6:74<]9%l~k }f.eo4+qu'~zex!lotlw[a4;>7897X> gsd-vc)`d9$|~"ynup,gjsi|Vn90:0=2:W3+bta&{l$ka>!ws-ttkru'je~byQk2=:=64=R8&myj#|i/fn3*rt(yd~"m`uov\`7Y7:81^<"i}f/pe+bj7&~x${}`{r.alqkrXl;U:><5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th?Q=209V4*aun'xm#jb?.vp,suhsz&idyczPd3]064=R8&myj#|i/fn3*rt(yd~"m`uov\`7Y3:81^<"i}f/pe+bj7&~x${}`{r.alqkrXl;U>><5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th?Q9209V4*aun'xm#jb?.vp,suhsz&idyczPd3]464=R8&myj#|i/fn3*rt(yd~"m`uov\`7Y?:;1^<"i}f/pe+bj7&~x${}`{r.alqkrXl:6;2?<4U1-dvc(un&mg<#y}/vrmpw)dg|dSi=31?01?P6(o{l%~k!hl1,tv*qwf}x$ob{at^f08785:2_;#j|i.sd,ci6){%||cz}/bmvjqYc;595>?5Z0.eqb+ta'nf;"z| wqlwv*eh}g~Th>2;>308Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_e1?1;453\:$kh!rg-dh5(pz&}{by| cnwmpZb44?49>6[?/fpe*w`(oe:%{!xpovq+firf}Uo?191239V4*aun'xm#jb?.vp,suhsz&idyczPd2>;:77<]9%l~k }f.eo4+qu'~zex!lotlw[a5X8;;0Y=!hrg,qb*ak8'}y#z~ats-`kphsWm9T=??4U1-dvc(un&mg<#y}/vrmpw)dg|dSi=P2338Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_e1\777<]9%l~k }f.eo4+qu'~zex!lotlw[a5X<;;0Y=!hrg,qb*ak8'}y#z~ats-`kphsWm9T9??4U1-dvc(un&mg<#y}/vrmpw)dg|dSi=P6338Q5)`zo$yj"ic0/uq+rvi|{%hcx`{_e1\377<]9%l~k }f.eo4+qu'~zex!lotlw[a5X0;>0Y=!hrg,qb*ak8'}y#z~ats-`kphsWge<=>>169V4*aun'xm#`kb/emvpZo;87;37X> gsd-vc)jmd%ocxzPi=33:4><]9%l~k }f.ofi*bh}}Ub0<?1199V4*aun'xm#`kb/emvpZo;9;4:46[?/fpe*w`(elg$hb{{_h>27;7?3\:$kh!rg-nah)cg|~Te1?;>0:8Q5)`zo$yj"cjm.flqqYn48?5=55Z0.eqb+ta'dof#iazt^k?538602_;#j|i.sd,i`k(lfSd2>7?3;?P6(o{l%~k!bel-gkprXa5;32<64U1-dvc(un&gna"j`uu]j84?99>1^<"i}f/pe+hcj'me~xRg31?3;?P6(o{l%~k!bel-gkprXa58;2<64U1-dvc(un&gna"j`uu]j8779911^<"i}f/pe+hcj'me~xRg323<2<>S7'nxm"h mdo,`jssW`69?3?7;T2,cw`)zo%fi`!kotv\m9436820Y=!hrg,qb*kbe&ndyyQf<37=5==R8&myj#|i/lgn+air|Vc7>;0>8:W3+bta&{l$ahc dnww[l:5?7;37X> gsd-vc)jmd%ocxzPi=0;:4><]9%l~k }f.ofi*bh}}Ub0?71169V4*aun'xm#`kb/emvpZo;:7;37X> gsd-vc)jmd%ocxzPi=13:4><]9%l~k }f.ofi*bh}}Ub0>?1199V4*aun'xm#`kb/emvpZo;;;4:46[?/fpe*w`(elg$hb{{_h>07;7?3\:$kh!rg-nah)cg|~Te1=;>0:8Q5)`zo$yj"cjm.flqqYn4:?5=:5Z0.eqb+ta'dof#iazt^k?7;703\:$kh!rg-nah)cg|~Te1:1169V4*aun'xm#`kb/emvpZo;=7;<7X> gsd-vc)jmd%ocxzPi=4=52=R8&myj#|i/lgn+air|Vc7;3?8;T2,cw`)zo%fi`!kotv\m9>99>1^<"i}f/pe+hcj'me~xRg39?35?P6(o{l%~k!bel-gkprXaV:::6[?/fpe*w`(elg$hb{{_h]252=R8&myj#|i/lgn+air|VcT==?8;T2,cw`)zo%fi`!kotv\mZ769>1^<"i}f/pe+hcj'me~xRgP1334?P6(o{l%~k!bel-gkprXaV;8=:5Z0.eqb+ta'dof#iazt^k\51703\:$kh!rg-nah)cg|~TeR?:169V4*aun'xm#`kb/emvpZoX9?;<7X> gsd-vc)jmd%ocxzPi^3452=R8&myj#|i/lgn+air|VcT=5?8;T2,cw`)zo%fi`!kotv\mZ7>9?1^<"i}f/pe+hcj'me~xRgP2058Q5)`zo$yj"cjm.flqqYnW;::;6[?/fpe*w`(elg$hb{{_h]1541<]9%l~k }f.ofi*bh}}UbS?<>7:W3+bta&{l$ahc dnww[lY5;8=0Y=!hrg,qb*kbe&ndyyQf_3623>S7'nxm"h mdo,`jssW`U99<94U1-dvc(un&gna"j`uu]j[706?2_;#j|i.sd,i`k(lfSdQ=7058Q5)`zo$yj"cjm.flqqYnW;2:;6[?/fpe*w`(elg$hb{{_h]1=40<]9%l~k }f.ofi*bh}}UbS>?8;T2,cw`)zo%fi`!kotv\mZ579>1^<"i}f/pe+hcj'me~xRgP3034?P6(o{l%~k!bel-gkprXaV99=:5Z0.eqb+ta'dof#iazt^k\76703\:$kh!rg-nah)cg|~TeR=;169V4*aun'xm#`kb/emvpZoX;<;=7X> gsd-vc)jmd%ocxzPi^622>S7'nxm"h mdo,`jssW`U>=;5Z0.eqb+ta'dof#iazt^k\240<]9%l~k }f.ofi*bh}}UbS:?9;T2,cw`)zo%fi`!kotv\mZ>6>2_;#j|i.sd,i`k(lfSdQ6189V4*aun'xm#`kb/emvpZkbe5:5=l5Z0.eqb+ta'dof#iazt^ofi97768k0Y=!hrg,qb*kbe&ndyyQbel>25;7f3\:$kh!rg-nah)cg|~Tahc313<2e>S7'nxm"h mdo,`jssWdof0<=11`9V4*aun'xm#`kb/emvpZkbe5;?2<o4U1-dvc(un&gna"j`uu]nah:6=7;j7X> gsd-vc)jmd%ocxzPmdo?5386i2_;#j|i.sd,i`k(lfS`kb<05=5d=R8&myj#|i/lgn+air|Vgna1?7>0c8Q5)`zo$yj"cjm.flqqYjmd6:53?6;T2,cw`)zo%fi`!kotv\i`k;97;j7X> gsd-vc)jmd%ocxzPmdo?6586i2_;#j|i.sd,i`k(lfS`kb<33=5d=R8&myj#|i/lgn+air|Vgna1<=>0c8Q5)`zo$yj"cjm.flqqYjmd69?3?n;T2,cw`)zo%fi`!kotv\i`k;:=4:m6[?/fpe*w`(elg$hb{{_lgn87399h1^<"i}f/pe+hcj'me~xRcjm=05:4g<]9%l~k }f.ofi*bh}}Ufi`2=7?3b?P6(o{l%~k!bel-gkprXelg7>50>a:W3+bta&{l$ahc dnww[hcj4;35=45Z0.eqb+ta'dof#iazt^ofi9499h1^<"i}f/pe+hcj'me~xRcjm=13:4g<]9%l~k }f.ofi*bh}}Ufi`2<1?3b?P6(o{l%~k!bel-gkprXelg7??0>a:W3+bta&{l$ahc dnww[hcj4:95=l5Z0.eqb+ta'dof#iazt^ofi95368k0Y=!hrg,qb*kbe&ndyyQbel>01;7>3\:$kh!rg-nah)cg|~Tahc33?3:?P6(o{l%~k!bel-gkprXelg783?6;T2,cw`)zo%fi`!kotv\i`k;=7;27X> gsd-vc)jmd%ocxzPmdo?2;7>3\:$kh!rg-nah)cg|~Tahc37?3:?P6(o{l%~k!bel-gkprXelg743?6;T2,cw`)zo%fi`!kotv\i`k;17=?7X> gsd-vc)jmd%ln` hble-cgk`i'dlinm!ble,fimXelgTkh`jr`vlv*pfd`n%o~z}/scnhjiwS9W%~lc!r.q0[kinf`~%~lc dqpbi+bw;?r8:#|nm0`8Q5)`zo$yj"cjm.vntZtfeVxoSh`>c:W3+bta&{l$ahc tlr\vdkXzmUnb<?8;T2,cw`)zo%ym`Q}efmvpZci9m1^<"i}f/pe+wusjea$^^ZPFTNO[BCI9m1^<"i}f/pe+wusjea$~iQ}su]bwwc`:91^<"i}f/pe+wusjea$~iQ}su]bwwc`Wm;9<6[?/fpe*w`(zz~i`f!}d^pppZgtzlmTh??l;T2,cw`)zo%yylck.pg[wusWjefn<j4U1-dvc(un&xxxobd/sf\vvrXkfgi=<k4U1-dvc(un&xxxobd/sf\vvrXzlm7<3?j;T2,cw`)zo%yylck.pg[wusW{ol0<0>e:W3+bta&{l$~~zmlj-q`Ztt|Vxnk1<11e9V4*aun'xm#}{bmi,vaYu{}UyijQ?1e9V4*aun'xm#}{bmi,vaYu{}UyijQ>1e9V4*aun'xm#}{bmi,vaYu{}UyijQ=169V4*aun'xm#}{bmi,vvrXl8;<7X> gsd-vc)u{}hgg"||t^f152=R8&myj#|i/sqwfim(zz~Th>?k;T2,cw`)zo%yylck.uq[wusWhyyij<?;T2,cw`)zo%yylck.uq[wusWhyyijQk1328Q5)`zo$yj"||tcnh+rtXzz~Tm~|jg^f15f=R8&myj#|i/sqwfim({UyyQlol`2`>S7'nxm"h rrvahn)pzVxxxRm`mc32a>S7'nxm"h rrvahn)pzVxxxR|jg=2=5`=R8&myj#|i/sqwfim({UyyQ}ef>2:4b<]9%l~k }f.pppgjl'~xT~~zPrde\44b<]9%l~k }f.pppgjl'~xT~~zPrde\5d=R[LXTMAGNSb9VW@TX^@YBNAK<;WA@=>PNM^U_U]K<;VGB7>QBJj1\^DZJ_LMGAZGd3^XBXHQBOEG\Fa=PZ@^NSZGKTI]B`>QUA]OT[DJ[H^@2`>^ND@DS!UJM 1,2$VRRJ):%=-O\CHK6?]IUKP<0T^ZCIC58\VRXOGN<7U][_WA@f>^XKFXNSD@IO79[`gYNlo1SheQ_rhoUawungg;;7Ujb_LcikwPbzzcdb<>4Xeo\Ilhhz_oydaac:coijusWlg{xtl4amolwqYa}ef=7oolktrg?ggdc|zTal|des18gimc3mkmRm`uov+4,b<lh~jSnaznu*2-a=ci}kTob{at)0*`>bf|hUhcx`{(2+g?agsiVidycz'4(f8`drfWje~by&:)e9geqgXkfex%8&d:fbpdYdg|d$:'k;ecweZeh}g~#4$h4d`vb[firf}636=08;e`jp`tu>2nbb%>&6:fjj-7.?2nbb%??)69gmk.69 =0hd`'13+4?aoi 89";6jfn)37-2=cag":9$94dhl+53/03mce$<9&7:fjj-7?!>1oec&>9(48`lh/: =0hd`'21+4?aoi ;;";6jfn)01-2=cag"9?$94dhl+61/03mce$?;&7:fjj-41!>1oec&=7(58`lh/:1#<7iga(3;*2>bnf!9";6jfn)13-2=cag"8=$94dhl+77/03mce$>=&7:fjj-53!>1oec&<5(48`lh/< <0hd`'5(48`lh/> <0hd`'7(48`lh/0 <0hd`'9(48`lh;87=0hd`311<4?aoi48;5;6jfn=31:2=cag6:?394dhl?51803mce0<;17:fjj9716>1oec2>7?58`lh;914<7iga<0;=2>bnf5;5;6jfn=03:2=cag69=394dhl?67803mce0?=17:fjj9436>1oec2=5?58`lh;:?4<7iga<35=3>bnf5832:5kio>1=;0<l`d7>394dhl?75803mce0>?17:fjj9556>1oec2<3?58`lh;;=427iga<2794;1<l`d7?809;ekm86813mce0909;ekm80813mce0;09;ekm82813mce0509;ekm8<803me~x%>&7:flqq.6!11ocxz'11+;?air|!;:%55kotv+57/?3me~x%?<)99gkpr/9=#37iazt)36-==cg|~#=;'7;emvp-70!11ocxz'19+;?air|!;2%:5kotv+6,><lf$?>&8:flqq.59 20hb{{(30*<>bh}}"9?$64dnww,72.02ndyy&=5(:8`jss ;<"46j`uu*13,><lf$?6&8:flqq.51 =0hb{{(2+;?air|!9;%55kotv+74/?3me~x%==)99gkpr/;:#37iazt)17-==cg|~#?8'8;emvp-2.?2ndyy&:)69gkpr/> =0hb{{(6+4?air|!2";6j`uu*:-2=cg|~7<364dnww846902ndyy2>1?:8`jss488546j`uu>27;><lf0<:18:flqq:6=720hb{{<04=<>bh}}6:;364dnww84>902ndyy2>9?58`jss48437iazt=03:==cg|~7><07;emvp945611ocxz322<;?air|58?255kotv?608?3me~x1<9>99gkpr;:>437iazt=0;:==cg|~7>408;emvp94902ndyy2<0?:8`jss4:;546j`uu>06;><lf0>=18:flqq:4<7k0hb{{<2794;><lf0>;17:flqq:46>1ocxz34?58`jss4<4<7iazt=4=3>bh}}6<2:5kotv?<;1<lf0407;dfjb7h`l<1na}zv2g9emciXoldn~lz`r^t5[4*'P`fbbu.LOSG#C`hbzh~d~-?=.33e?coagVrgbuQ:13z02Z4ddbU{~biPftno7a=aaoeTta`w_431|60X:jf`S}|`g^dvhi*aaoeTkh`jr`vlvZp1W8&ECCK#NNLF052<n`ldSubax^726}51W;iggR~}of]eqij+n`ldSjkaescwkwYq>V;'wnQgar]jjqYddb7; nQgar]pvvr:8%iT~iQirds>5)eXmgki`hQ}su]p}ke:9%iTdl}Pre]geqgXkfex0>#c^fjjZqnl}b6?;"l_icp[rtXlh~jSnaznu?3(fYa}efTjaohs^pppZpfd4;'oRgbpmgnakrf|`eeSywe<0/gZstmVofnhjkee]qab;7$jU|~Rh}ep?2(fYr{lUocxzPrrv>5)eX}gnn~kb`w^nls86+kVbjRayesdokr;7$jU{~hb`ae]oeqcikp7; nQkotv\slbs`49= nQbsfmm[sgk58&hSjPddrwl836:%iTi|`r^kmn`esafdTxt~j=1.`[mgtW|doihcov?3(fYoizUj``a|t^dvhi;6$jUcm~Q}su?2(fYci}kTob{at^uj`qn:1%iTdl}Pws]bgn;7$jU~hQjcb?3(fYdgdgdbRmcobi>4)eX{UjofQcov?3(fYulVzexQxievk9<*dW|ynSkyit^fbpdYdg|d1="l_icp[djjgz~Ti`~{y<2/gZtcWmkmRm`uov\slbs`43'oRayesdokrYkg~7; nQxr^rmpwYpam~c14"l_qplcZcjx}sTxt~j=1.`[rtXlh~jSnaznu]tmaro50&hS}|jlncg[wc`{4;'oRj`uu]qwqYqie7; nQgar]geqgXkfex0>#c^rqkbYa}efTxe|jsi]mabgsmV|j`0:69-a\swYcmy~c18?=,b]svjaXmdzuRzgrdqk[kc`i}oTzlb25-a\twi`Wlg{xtQ{hsgplZgt{lxS{oc=5.`[mgtWkgei3?,b]svjaXn|fgSyf}erj\evubz}U}ma3:01.`khvhfldScobe<djbjYdgrT9<<w37]1gimXx{elSk{cl-a\rdjnlVfd{0>#c^rqmhYaaoeTxt~j=431|60+kVzycjQiumn\p|vb58&hS`kbos{\p|vb58&v?45iigm\|ihW<;9t>8P2bnh[uthoVl~`aQiigm\c`hbzh~d~Rx9_0]{wqY6<2l~`aj4iohfgqbea}oy~i5fnkg`pvdn|lxy;6gat^aoo==iojh~eaj7;ntfvcjhh1{~biPelrw}42<x{elShctx]wlwct`!:"=95rne\ahvsqV~c~h}g(0+20>vugnUna}zv_ujqavn/: ;?7}|`g^gntqX|axne&<)068twi`Wlg{xtQ{hsgpl-2.9=1{~biPelrw}Zrozlyc$8'>4:rqkbYbey~rSyf}erj+2,733yxdkRkbpu{\pmtb{a"<%<:4psmd[`kw|pUdk|h):*53=wzfmTi`~{y^vkv`uo410;2<l4psmd[`kw|pUdk|h^cpw`ts 9#:n6~}of]fiur~W}byi~fParqfvq.6!8h0|ah_dosp|Ys`{oxdRo|sdpw,7/6j2zycjQjmqvz[qnumzbTm~}jru*0-4d<x{elShctx]wlwct`Vkxh|{(5+2f>vugnUna}zv_ujqavnXizyn~y&:)0`8twi`Wlg{xtQ{hsgplZgt{lx$;'>b:rqkbYbey~rSyf}erj\evubz}"<%<l4psmd[`kw|pUdk|h^cpw`ts 1#:h6~}of]fiur~W}byi~fParqfvq:?294:n6~}of]fiur~W}byi~fPndebp`.7!8h0|ah_dosp|Ys`{oxdR`jg`vf,4/6j2zycjQjmqvz[qnumzbTbhintd*1-4d<x{elShctx]wlwct`Vdnklzj(2+2f>vugnUna}zv_ujqavnXflmjxh&;)0`8twi`Wlg{xtQ{hsgplZhboh~n$8'>b:rqkbYbey~rSyf}erj\j`af|l"=%<l4psmd[`kw|pUdk|h^lfcdrb >#:n6~}of]fiur~W}byi~fPndebp`.?!8n0|ah_dosp|Ys`{oxdR`jg`vf8=<7601{~biPftno56=wzfmTjxbc_ujqavn/8 ;87}|`g^dvhiYs`{oxd%?&129svjaXn|fgSyf}erj+6,743yxdkRhzlm]wlwct`!9"=>5rne\bpjkW}byi~f'4(30?uthoVl~`aQ{hsgpl-3.9:1{~biPftno[qnumzb#:$?<;qplcZ`rdeUdk|h)5*56=wzfmTjxbc_ujqavn/0 ;>7}|`g^dvhiYs`{oxd1650?3b?uthoVl~`aQ{hsgplZgt{lx$='>a:rqkbYa}efTxe|jsi]bwvcu|!;"=l5rne\bpjkW}byi~fParqfvq.5!8k0|ah_gwohZrozlycSl}|esv+7,7f3yxdkRhzlm]wlwct`Vkxh|{(5+2e>vugnUmyabPtipfwmYf{zoyx%;&1`9svjaXn|fgSyf}erj\evubz}"=%<o4psmd[cskdV~c~h}g_`qpawr/? ;j7}|`g^dvhiYs`{oxdRo|sdpw,=/6k2zycjQiumn\pmtb{aUj~k}t=:94;7f3yxdkRhzlm]wlwct`Vdnklzj(1+2e>vugnUmyabPtipfwmYimnki%?&1`9svjaXn|fgSyf}erj\j`af|l"9%<o4psmd[cskdV~c~h}g_ogdeqc/; ;j7}|`g^dvhiYs`{oxdR`jg`vf,1/6i2zycjQiumn\pmtb{aUeijo{e)7*5d=wzfmTjxbc_ujqavnXflmjxh&9)0c8twi`Wog`Rzgrdqk[kc`i}o#;$?n;qplcZ`rdeUdk|h^lfcdrb 1#:o6~}of]eqijX|axneQaefcwa9>=87<0~iQllj33?wbXlh~jSnaznu*3-46<zmUomyoPcnwmp-7.991yhRjnt`]`kphs ;#:<6|k_ecweZeh}g~#?$??;sf\`drfWje~by&;)028vaYci}kTob{at)7*55=ulVnjxlQlotlw,3/682xoSio{a^alqkr/? ;;7jPd`vb[firf}"3%<>4re]geqgXkfex1>1139q`Zbf|hUhcx`{<983:0=ulVoe:6|k_sqw7>tt|>1xndzjrs68wwus:k1a}!Pcf-emciXpedsS8?=x24\6fjlWyxdkRhzlm,mcj2<|{n56{addpehjq23kgei84ws]bgn0<{Uh`f??;vp\`drfWje~by&?)028swYci}kTob{at)3*55=pzVnjxlQlotlw,7/682}ySio{a^alqkr/; ;;7z|Pd`vb[firf}"?%<>4ws]geqgXkfex%;&119tvZbf|hUhcx`{(7+24>quWmkmRm`uov+3,773~xThlzn_bmvjq.?!880{Qkauc\gjsi|521<3;4ws]fj3=pzVxxxpNOpbd2?EF=021J7:51zQ7b?34k3<1=><m7g596d4>mrd?554>;o6:=?0<,=3=697?;|Q7`?34k3<1=><m7g596d4>m2Y:8i4:4683>455j>l<6?o=9d9P0a<2<>0;6<==b6d4>7g51o1o9>h50;395~U3n3?8o785120a3c1=:h82i6x[1cf94?7=93;h8v];f;70g?0=9:8i;k952`0:a>"3000:8h5Y48596~s6=>0:7x?:8;28y!7e93l0n8=i:1865?5==8qC8594Z5796~c=l3w/=n<552d8 1?22<9n7d;63;29?j2>j3:17b;98;29?l3f03:17b;;3;29?j34l3:17d;6d;29?l3>=3:17b;>0;29 4d42<987c?m2;28?j37n3:1(<l<:410?k7e:3;07b;?e;29 4d42<987c?m2;08?j37l3:1(<l<:410?k7e:3907b;?c;29 4d42<987c?m2;68?j37j3:1(<l<:410?k7e:3?07b;?9;29 4d42<987c?m2;48?j3703:1(<l<:410?k7e:3=07b;?7;29 4d42<987c?m2;:8?j37>3:1(<l<:410?k7e:3307b;?5;29 4d42<987c?m2;c8?j37<3:1(<l<:410?k7e:3h07b;?3;29 4d42<987c?m2;a8?j37:3:1(<l<:410?k7e:3n07b;?1;29 4d42<987c?m2;g8?j3783:1(<l<:410?k7e:3l07b:ie;29 4d42<987c?m2;33?>i3nm0;6)?m3;707>h6j;0:=65`4ga94?"6j:0>?>5a1c0957=<g=li6=4+1c19165<f8h96<=4;n6ee?6=,8h868=<;o3a6?7332e?j44?:%3a7?34;2d:n?4>5:9l0c>=83.:n>4:329m5g4=9?10c9h8:18'5g5==:90b<l=:058?j2a>3:1(<l<:410?k7e:3;376a;f483>!7e;3?8?6`>b382=>=h=8<1<7*>b28676=i9k81=l54o436>5<#9k919>=4n0`1>4d<3f?:87>5$0`0>0543g;i>7?l;:m656<72-;i?7;<3:l2f7<6l21d9<<50;&2f6<2;:1e=o<51d98k076290/=o=55218j4d528l07b;?a;29 4d42<987c?m2;03?>i3no0;6)?m3;707>h6j;09=65`4g694?"6j:0>?>5a1c0967=<g=l86=4+1c19165<f8h96?=4;h6`3?6=,8h869kn;o3a6?6<3`>h:7>5$0`0>1cf3g;i>7?4;h6`1?6=,8h869kn;o3a6?4<3`>h87>5$0`0>1cf3g;i>7=4;h6`7?6=,8h869kn;o3a6?2<3`>h>7>5$0`0>1cf3g;i>7;4;h6`4?6=,8h869kn;o3a6?0<3`>ij7>5$0`0>1cf3g;i>794;h6aa?6=,8h869kn;o3a6?><3`>ih7>5$0`0>1cf3g;i>774;h6ag?6=,8h869kn;o3a6?g<3`>in7>5$0`0>1cf3g;i>7l4;h6ae?6=,8h869kn;o3a6?e<3`>i57>5$0`0>1cf3g;i>7j4;h6a<?6=,8h869kn;o3a6?c<3`>i;7>5$0`0>1cf3g;i>7h4;h6a1?6=,8h869kn;o3a6?7732c?n94?:%3a7?2bi2d:n?4>1:9j0g5=83.:n>4;e`9m5g4=9;10e9l=:18'5g5=<lk0b<l=:018?l2e93:1(<l<:5gb?k7e:3;?76g;b183>!7e;3>nm6`>b3821>=n<hl1<7*>b287ad=i9k81=;54i5cf>5<#9k918ho4n0`1>41<3`>jh7>5$0`0>1cf3g;i>7?7;:k7ef<72-;i?7:ja:l2f7<6121b8nj50;&2f6<3mh1e=o<51`98m1ed290/=o=54dc8j4d528h07d:lb;29 4d42=oj7c?m2;3`?>o3kh0;6)?m3;6fe>h6j;0:h65f4b;94?"6j:0?il5a1c095`=<a=i36=4+1c190`g<f8h96<h4;h6`5?6=,8h869kn;o3a6?4732c?n;4?:%3a7?2bi2d:n?4=1:9j0dd=83.:n>4;e`9m5g4=:;10e9on:18'5g5=<lk0b<l=:318?l3??3:17o:78;295?6=8rB?4:5+1b090=><g8h;6=44}cda>5<6290;wE:77:&2g7<aj2emm7>5;|`70?6=j:0:;;4>c5yK0=1<R=?1=;u=4;00>73=:009:7<8:3:9a?b=:h09n7<6:3`9a?4f2;>1h7<7:35963<5=3886p*>c38607=#<10>8=5+4d8604=#9hi1=lh4i47`>5<#9k9198j4n0`1>5=<a<?i6=4+1c1910b<f8h96<54i47b>5<#9k9198j4n0`1>7=<a<?26=4+1c1910b<f8h96>54i47;>5<#9k9198j4n0`1>1=<a<?<6=4+1c1910b<f8h96854i475>5<#9k9198j4n0`1>3=<a<?>6=4+1c1910b<f8h96:54i477>5<#9k9198j4n0`1>==<a<>>6=44i4;7>5<<a<3<6=44o4;a>5<<a<?96=4+1c19105<f8h96=54i472>5<#9k9198=4n0`1>4=<a<?;6=4+1c19105<f8h96?54i46e>5<#9k9198=4n0`1>6=<a<>n6=4+1c19105<f8h96954i46g>5<#9k9198=4n0`1>0=<a<>h6=4+1c19105<f8h96;54i46a>5<#9k9198=4n0`1>2=<a<>j6=4+1c19105<f8h96554i4;0>5<<g<>36=44i445>5<#9k919;94n0`1>5=<a<<>6=4+1c19131<f8h96<54i447>5<#9k919;94n0`1>7=<a<<86=4+1c19131<f8h96>54i441>5<#9k919;94n0`1>1=<a<<:6=4+1c19131<f8h96854i443>5<#9k919;94n0`1>3=<a<?m6=4+1c19131<f8h96:54i47f>5<#9k919;94n0`1>==<g=3i6=44o5c4>5<#9k918l64n0`1>5=<g=k=6=4+1c190d><f8h96<54o5c6>5<#9k918l64n0`1>7=<g=k?6=4+1c190d><f8h96>54o5c0>5<#9k918l64n0`1>1=<g=k96=4+1c190d><f8h96854o5c2>5<#9k918l64n0`1>3=<g=k;6=4+1c190d><f8h96:54o5;e>5<#9k918l64n0`1>==<g<<36=44i4c;>5<<a<=:6=4+1c19124<f8h96=54i453>5<#9k919:<4n0`1>4=<a<<m6=4+1c19124<f8h96?54i44f>5<#9k919:<4n0`1>6=<a<<o6=4+1c19124<f8h96954i44`>5<#9k919:<4n0`1>0=<a<<i6=4+1c19124<f8h96;54i44b>5<#9k919:<4n0`1>2=<a<<26=4+1c19124<f8h96554o460>5<<g<9o6=44i4;g>5<<a=3o6=44i45a>5<#9k919:m4n0`1>5=<a<=j6=4+1c1912e<f8h96<54i45:>5<#9k919:m4n0`1>7=<a<=36=4+1c1912e<f8h96>54i454>5<#9k919:m4n0`1>1=<a<==6=4+1c1912e<f8h96854i456>5<#9k919:m4n0`1>3=<a<=?6=4+1c1912e<f8h96:54i450>5<#9k919:m4n0`1>==<a<2>6=4+1c191=0<f8h96=54i4:7>5<#9k919584n0`1>4=<a<286=4+1c191=0<f8h96?54i4:1>5<#9k919584n0`1>6=<a<2:6=4+1c191=0<f8h96954i4:3>5<#9k919584n0`1>0=<a<=m6=4+1c191=0<f8h96;54i45f>5<#9k919584n0`1>2=<a<=o6=4+1c191=0<f8h96554o5;b>5<<a<>=6=44i5;f>5<<a<k26=44o4;5>5<<g<3h6=44i4;6>5<<g<;;6=4+1c19165<f8h96=54o42e>5<#9k919>=4n0`1>4=<g<:n6=4+1c19165<f8h96?54o42g>5<#9k919>=4n0`1>6=<g<:h6=4+1c19165<f8h96954o42a>5<#9k919>=4n0`1>0=<g<:26=4+1c19165<f8h96;54o42;>5<#9k919>=4n0`1>2=<g<:<6=4+1c19165<f8h96554o425>5<#9k919>=4n0`1><=<g<:>6=4+1c19165<f8h96l54o427>5<#9k919>=4n0`1>g=<g<:86=4+1c19165<f8h96n54o421>5<#9k919>=4n0`1>a=<g<::6=4+1c19165<f8h96h54o423>5<#9k919>=4n0`1>c=<g=ln6=4+1c19165<f8h96<>4;n6e`?6=,8h868=<;o3a6?7632e?jn4?:%3a7?34;2d:n?4>2:9l0cd=83.:n>4:329m5g4=9:10c9hn:18'5g5==:90b<l=:068?j2a13:1(<l<:410?k7e:3;>76a;f983>!7e;3?8?6`>b3822>=h<o=1<7*>b28676=i9k81=:54o5d5>5<#9k919>=4n0`1>4><3f>m97>5$0`0>0543g;i>7?6;:m653<72-;i?7;<3:l2f7<6i21d9<;50;&2f6<2;:1e=o<51c98k073290/=o=55218j4d528i07b;>3;29 4d42<987c?m2;3g?>i29;0;6)?m3;707>h6j;0:i65`50394?"6j:0>?>5a1c095c=<g<:j6=4+1c19165<f8h96?>4;n6eb?6=,8h868=<;o3a6?4632e?j94?:%3a7?34;2d:n?4=2:9l0c5=83.:n>4:329m5g4=::10e9m8:18'5g5=<lk0b<l=:198m1e1290/=o=54dc8j4d52810e9m::18'5g5=<lk0b<l=:398m1e3290/=o=54dc8j4d52:10e9m<:18'5g5=<lk0b<l=:598m1e5290/=o=54dc8j4d52<10e9m?:18'5g5=<lk0b<l=:798m1da290/=o=54dc8j4d52>10e9lj:18'5g5=<lk0b<l=:998m1dc290/=o=54dc8j4d52010e9ll:18'5g5=<lk0b<l=:`98m1de290/=o=54dc8j4d52k10e9ln:18'5g5=<lk0b<l=:b98m1d>290/=o=54dc8j4d52m10e9l7:18'5g5=<lk0b<l=:d98m1d0290/=o=54dc8j4d52o10e9l::18'5g5=<lk0b<l=:028?l2e<3:1(<l<:5gb?k7e:3;:76g;b283>!7e;3>nm6`>b3826>=n<k81<7*>b287ad=i9k81=>54i5`2>5<#9k918ho4n0`1>42<3`>i<7>5$0`0>1cf3g;i>7?:;:k7ec<72-;i?7:ja:l2f7<6>21b8lk50;&2f6<3mh1e=o<51698m1gc290/=o=54dc8j4d528207d:nc;29 4d42=oj7c?m2;3:?>o3km0;6)?m3;6fe>h6j;0:m65f4ba94?"6j:0?il5a1c095g=<a=ii6=4+1c190`g<f8h96<m4;h6`e?6=,8h869kn;o3a6?7c32c?o44?:%3a7?2bi2d:n?4>e:9j0f>=83.:n>4;e`9m5g4=9o10e9m>:18'5g5=<lk0b<l=:328?l2e>3:1(<l<:5gb?k7e:38:76g;ac83>!7e;3>nm6`>b3816>=n<hk1<7*>b287ad=i9k81>>54i5;`>5<<g<3;6=4+1c191<4<f8h96=54o4:e>5<#9k9194<4n0`1>4=<g<2n6=4+1c191<4<f8h96?54o4:g>5<#9k9194<4n0`1>6=<g<2h6=4+1c191<4<f8h96954o4:a>5<#9k9194<4n0`1>0=<g<2j6=4+1c191<4<f8h96;54o4::>5<#9k9194<4n0`1>2=<g<236=4+1c191<4<f8h96554o4c5>5<#9k919l94n0`1>5=<g<k>6=4+1c191d1<f8h96<54o4c7>5<#9k919l94n0`1>7=<g<k86=4+1c191d1<f8h96>54o4c1>5<#9k919l94n0`1>1=<g<k:6=4+1c191d1<f8h96854o4c3>5<#9k919l94n0`1>3=<g<3m6=4+1c191d1<f8h96:54o4;f>5<#9k919l94n0`1>==<g<>26=44i467>5<<g=k26=44i4:4>5<<g<3j6=44b5;0>5<6290;w)?l2;da?M2>:2B?4:5`f`83>>{e<0>1<7?50;2x 4e52=237E:62:J7<2=h9k:1<75rb3ag>5<3290;w)?l2;d4?M2>:2B?4:5+11:91>o3>3:17d;?:188m4d32900c<l::188yg21m3:187>50z&2g7<a=2B?5?5G4958 46?281b8;4?::k7g?6=3`?;6=44o0`6>5<<uk><o7>54;294~"6k;0m;6F;939K0=1<@=80(<;::4;:?!7703?0e9850;9j15<722c:n94?::m2f0<722wi8:?50;194?6|,8i96k:4H5;1?M2??2B?>6*>5486=<=#9921=6g;6;29?l372900c<l::188yg20n3:1?7>50z&2g7<a<2B?5?5G4958L14<,8?>6876;%33<?7<a=<1<75f5183>>i6j<0;66sm46`94?2=83:p(<m=:g58L1?53A>3;6F;2:&210<2101/==655:k72?6=3`?;6=44i0`7>5<<g8h>6=44}c644?6=;3:1<v*>c38e0>N31;1C8594H508 4322<327)??8;38m10=831b9=4?::m2f0<722wi8:j50;794?6|,8i96k64H5;1?M2??2B?>6*>5486=<=n<?0;66g;7;29?l372900e<l;:188k4d22900qo:8e;297?6=8r.:o?4i4:J7=7=O<1=0D9<4$076>0?>3-;;47?4i5494?=n=90;66a>b483>>{e<?l1<7;50;2x 4e52o20D97=;I6;3>N3:2.:984:989j03<722c?;7>5;h73>5<<a8h?6=44o0`6>5<<uk><m7>54;294~"6k;0m;6F;939K0=1<@=80(<;::4;:?!7703?0e9850;9j15<722c:n94?::m2f0<722wi8:750;694?6|,8i96k94H5;1?M2??2.:<54:;h65>5<<a<:1<75f1c694?=h9k?1<75rb55;>5<3290;w)?l2;d4?M2>:2B?4:5+11:91>o3>3:17d;?:188m4d32900c<l::188yg20?3:187>50z&2g7<a?2B?5?5G4958 46?2<1b8;4?::k64?6=3`;i87>5;n3a1?6=3th?484?:583>5}#9j81j:5G4808L1>03-;;47;4i5494?=n=90;66g>b583>>i6j<0;66sm49694?2=83:p(<m=:g58L1?53A>3;6*>0986?l212900e8>50;9j5g2=831d=o;50;9~f4c3290?6=4?{%3`6?`23A>2>6F;869'55>=92c?:7>5;h6`>5<<a<:1<75`1c794?=zj8o86=4;:183!7d:3l>7E:62:J7<2=#9921=6g;6;29?l2d2900e8>50;9l5g3=831vn<k=:187>5<7s-;h>7h:;I6:6>N30>1/==651:k72?6=3`>h6=44i4294?=h9k?1<75rb0g2>5<3290;w)?l2;d6?M2>:2B?4:5+11:95>o3>3:17d:l:188m06=831d=o;50;9~f4c7290?6=4?{%3`6?`23A>2>6F;869'55>=92c?:7>5;h6`>5<<a<:1<75`1c794?=zj8nm6=4;:183!7d:3l>7E:62:J7<2=#9921=6g;6;29?l2d2900e8>50;9l5g3=831vn<jj:187>5<7s-;h>7h:;I6:6>N30>1/==651:k72?6=3`>h6=44i4294?=h9k?1<75rb0fg>5<3290;w)?l2;d6?M2>:2B?4:5+11:95>o3>3:17d:l:188m06=831d=o;50;9~f4bd290?6=4?{%3`6?`23A>2>6F;869'55>=92c?:7>5;h6`>5<<a<:1<75`1c794?=zj;>=6=4;:183!7d:3l>7E:62:J7<2=#9921=6g;6;29?l2d2900e8>50;9l5g3=831vn?:::187>5<7s-;h>7h:;I6:6>N30>1/==651:k72?6=3`>h6=44i4294?=h9k?1<75rb367>5<3290;w)?l2;d6?M2>:2B?4:5+11:95>o3>3:17d:l:188m06=831d=o;50;9~f724290?6=4?{%3`6?`23A>2>6F;869'55>=92c?:7>5;h6`>5<<a<:1<75`1c794?=zj;>96=4;:183!7d:3l>7E:62:J7<2=#9921=6g;6;29?l2d2900e8>50;9l5g3=831vn?:>:187>5<7s-;h>7h:;I6:6>N30>1/==651:k72?6=3`>h6=44i4294?=h9k?1<75rb363>5<3290;w)?l2;d6?M2>:2B?4:5+11:95>o3>3:17d:l:188m06=831d=o;50;9~f75a290?6=4?{%3`6?`23A>2>6F;869'55>=92c?:7>5;h6`>5<<a<:1<75`1c794?=zj;9n6=4;:183!7d:3l>7E:62:J7<2=#9921=6g;6;29?l2d2900e8>50;9l5g3=831vn?6j:187>5<7s-;h>7h:;I6:6>N30>1/==651:k72?6=3`>h6=44i4294?=h9k?1<75rb3:g>5<3290;w)?l2;d6?M2>:2B?4:5+11:95>o3>3:17d:l:188m06=831d=o;50;9~f7>d290?6=4?{%3`6?`23A>2>6F;869'55>=92c?:7>5;h6`>5<<a<:1<75`1c794?=zj;2i6=4;:183!7d:3l>7E:62:J7<2=#9921=6g;6;29?l2d2900e8>50;9l5g3=831vn?6n:187>5<7s-;h>7h:;I6:6>N30>1/==651:k72?6=3`>h6=44i4294?=h9k?1<75rb3::>5<3290;w)?l2;d6?M2>:2B?4:5+11:95>o3>3:17d:l:188m06=831d=o;50;9~f7>?290?6=4?{%3`6?`23A>2>6F;869'55>=92c?:7>5;h6`>5<<a<:1<75`1c794?=zj;2<6=4;:183!7d:3l>7E:62:J7<2=#9921=6g;6;29?l2d2900e8>50;9l5g3=831vn?69:187>5<7s-;h>7h:;I6:6>N30>1/==651:k72?6=3`>h6=44i4294?=h9k?1<75rb30`>5<3290;w)?l2;d6?M2>:2B?4:5+11:95>o3>3:17d:l:188m06=831d=o;50;9~f74e290?6=4?{%3`6?`23A>2>6F;869'55>=92c?:7>5;h6`>5<<a<:1<75`1c794?=zj;8j6=4;:183!7d:3l>7E:62:J7<2=#9921=6g;6;29?l2d2900e8>50;9l5g3=831vn?<6:187>5<7s-;h>7h:;I6:6>N30>1/==651:k72?6=3`>h6=44i4294?=h9k?1<75rb30;>5<3290;w)?l2;d6?M2>:2B?4:5+11:95>o3>3:17d:l:188m06=831d=o;50;9~f740290?6=4?{%3`6?`23A>2>6F;869'55>=92c?:7>5;h6`>5<<a<:1<75`1c794?=zj;8=6=4;:183!7d:3l>7E:62:J7<2=#9921=6g;6;29?l2d2900e8>50;9l5g3=831vn?<::187>5<7s-;h>7h:;I6:6>N30>1/==651:k72?6=3`>h6=44i4294?=h9k?1<75rb307>5<3290;w)?l2;d6?M2>:2B?4:5+11:95>o3>3:17d:l:188m06=831d=o;50;9~f71d290?6=4?{%3`6?`23A>2>6F;869K07=#9<?19474$02;>4=n<?0;66g;c;29?l372900c<l::188yg40j3:187>50z&2g7<a=2B?5?5G4958L14<,8?>6876;%33<?7<a=<1<75f4b83>>o283:17b?m5;29?xd5?h0;694?:1y'5f4=n<1C84<4H5:4?M253-;>97;69:&24=<63`>=6=44i5a94?=n=90;66a>b483>>{e:>31<7:50;2x 4e52o?0D97=;I6;3>N3:2.:984:989'55>=92c?:7>5;h6`>5<<a<:1<75`1c794?=zj;=36=4;:183!7d:3l>7E:62:J7<2=O<;1/=8;558;8 46?281b8;4?::k7g?6=3`?;6=44o0`6>5<<uk8<;7>54;294~"6k;0m96F;939K0=1<@=80(<;::4;:?!7703;0e9850;9j0f<722c><7>5;n3a1?6=3th9;;4?:583>5}#9j81j85G4808L1>03A>97)?:5;7:=>"6810:7d:9:188m1e=831b9=4?::m2f0<722wi>:;50;694?6|,8i96k;4H5;1?M2??2B?>6*>5486=<=#9921=6g;6;29?l2d2900e8>50;9l5g3=831vn?9;:187>5<7s-;h>7h:;I6:6>N30>1C8?5+14791<?<,8:36<5f4783>>o3k3:17d;?:188k4d22900qo<>a;290?6=8r.:o?4i5:J7=7=O<1=0D9<4$076>0?>3-;;47?4i5494?=n<j0;66g:0;29?j7e=3:17pl=1883>1<729q/=n<5f49K0<4<@=2<7E:=;%361?3>12.:<54>;h65>5<<a=i1<75f5183>>i6j<0;66sm20:94?2=83:p(<m=:g78L1?53A>3;6F;2:&210<2101/==651:k72?6=3`>h6=44i4294?=h9k?1<75rb334>5<3290;w)?l2;d6?M2>:2B?4:5G439'503==030(<>7:09j03<722c?o7>5;h73>5<<g8h>6=44}c022?6=<3:1<v*>c38e1>N31;1C8594H508 4322<327)??8;38m10=831b8n4?::k64?6=3f;i97>5;|`150<72=0;6=u+1b09b0=O<080D968;I61?!72=3?256*>0982?l212900e9m50;9j15<722e:n84?::a642=83>1<7>t$0a1>c3<@=397E:77:J76>"6=<0>545+11:95>o3>3:17d:l:188m06=831d=o;50;9~f774290?6=4?{%3`6?`23A>2>6F;869K07=#9<?19474$02;>4=n<?0;66g;c;29?l372900c<l::188yg46:3:187>50z&2g7<a=2B?5?5G4958L14<,8?>6876;%33<?7<a=<1<75f4b83>>o283:17b?m5;29?xd5810;694?:1y'5f4=n<1C84<4H5:4?!7703;0e9850;9j0f<722c><7>5;n3a1?6=3th9<:4?:583>5}#9j81j85G4808L1>03-;;47?4i5494?=n<j0;66g:0;29?j7e=3:17pl=0783>1<729q/=n<5f49K0<4<@=2<7)??8;38m10=831b8n4?::k64?6=3f;i97>5;|`140<72=0;6=u+1b09b0=O<080D968;%33<?7<a=<1<75f4b83>>o283:17b?m5;29?xd58=0;694?:1y'5f4=n<1C84<4H5:4?!7703;0e9850;9j0f<722c><7>5;n3a1?6=3th9<>4?:583>5}#9j81j85G4808L1>03-;;47?4i5494?=n<j0;66g:0;29?j7e=3:17pl=0383>1<729q/=n<5f49K0<4<@=2<7)??8;38m10=831b8n4?::k64?6=3f;i97>5;|`144<72=0;6=u+1b09b0=O<080D968;%33<?7<a=<1<75f4b83>>o283:17b?m5;29?xd5890;694?:1y'5f4=n<1C84<4H5:4?!7703;0e9850;9j0f<722c><7>5;n3a1?6=3th9:l4?:583>5}#9j81j85G4808L1>03-;;47?4i5494?=n<j0;66g:0;29?j7e=3:17pl=6883>1<729q/=n<5f49K0<4<@=2<7)??8;38m10=831b8n4?::k64?6=3f;i97>5;|`12=<72=0;6=u+1b09b0=O<080D968;%33<?7<a=<1<75f4b83>>o283:17b?m5;29?xd5>>0;694?:1y'5f4=n<1C84<4H5:4?!7703;0e9850;9j0f<722c><7>5;n3a1?6=3th9:;4?:583>5}#9j81j85G4808L1>03-;;47?4i5494?=n<j0;66g:0;29?j7e=3:17pl=6483>1<729q/=n<5f49K0<4<@=2<7)??8;38m10=831b8n4?::k64?6=3f;i97>5;|`121<72=0;6=u+1b09b0=O<080D968;%33<?7<a=<1<75f4b83>>o283:17b?m5;29?xd5>:0;694?:1y'5f4=n<1C84<4H5:4?!7703;0e9850;9j0f<722c><7>5;n3a1?6=3th9:?4?:583>5}#9j81j85G4808L1>03-;;47?4i5494?=n<j0;66g:0;29?j7e=3:17pl<0583>0<729q/=n<5f79K0<4<@=2<7)??8;38m10=831b8:4?::k7g?6=3`?;6=44o0`6>5<<uk9;?7>55;294~"6k;0m:6F;939K0=1<,8:36<5f4783>>o3?3:17d:l:188m06=831d=o;50;9~f665290>6=4?{%3`6?`13A>2>6F;869'55>=92c?:7>5;h64>5<<a=i1<75f5183>>i6j<0;66sm31394?3=83:p(<m=:g48L1?53A>3;6*>0982?l212900e9950;9j0f<722c><7>5;n3a1?6=3th8<=4?:483>5}#9j81j;5G4808L1>03-;;47?4i5494?=n<>0;66g;c;29?l372900c<l::188yg4an3:197>50z&2g7<a>2B?5?5G4958 46?281b8;4?::k73?6=3`>h6=44i4294?=h9k?1<75rb3dg>5<2290;w)?l2;d5?M2>:2B?4:5+11:95>o3>3:17d:8:188m1e=831b9=4?::m2f0<722wi>km50;794?6|,8i96k64H5;1?M2??2.:<54:;h65>5<<a==1<75f5183>>o6j=0;66a>b483>>{e:oo1<7;50;2x 4e52o<0D97=;I6;3>"6810:7d:9:188m11=831b8n4?::k64?6=3f;i97>5;|`1b4<72:0;6=u+1b090<7<@=397E:77:k7=?6=3`;?n7>5;n3ba?6=3th9j=4?:283>5}#9j8184?4H5;1?M2??2c?57>5;h37f?6=3f;ji7>5;|`1a2<72=0;6=u+1b09500<@=397E:77:k7=?6=3`?96=44i0`a>5<<g8kn6=44}c0fb?6=;3:1<v*>c387=4=O<080D968;h6:>5<<a8>i6=44o0cf>5<<uk8n97>54;294~"6k;0:9;5G4808L1>03`>26=44i4094?=n9kh1<75`1`g94?=zj;on6=4<:183!7d:3>2=6F;939K0=1<a=31<75f15`94?=h9ho1<75rb3g0>5<3290;w)?l2;362>N31;1C8594i5;94?=n=;0;66g>bc83>>i6il0;66sm2df94?5=83:p(<m=:5;2?M2>:2B?4:5f4883>>o6<k0;66a>ad83>>{e:l;1<7:50;2x 4e528?=7E:62:J7<2=n<00;66g:2;29?l7ej3:17b?ne;29?xd5mj0;6>4?:1y'5f4=<0;0D97=;I6;3>o313:17d?;b;29?j7fm3:17pl=dg83>1<729q/=n<51448L1?53A>3;6g;9;29?l352900e<lm:188k4gb2900qo<jb;297?6=8r.:o?4;909K0<4<@=2<7d:6:188m42e2900c<oj:188yg4cl3:187>50z&2g7<6=?1C84<4H5:4?l2>2900e8<50;9j5gd=831d=lk50;9~f7cf29086=4?{%3`6?2>92B?5?5G4958m1?=831b=9l50;9l5dc=831vn?jm:187>5<7s-;h>7?:6:J7=7=O<1=0e9750;9j17<722c:no4?::m2e`<722wi>h750;194?6|,8i9697>;I6:6>N30>1b844?::k20g<722e:mh4?::a6a?=83>1<7>t$0a1>4313A>2>6F;869j0<<722c>>7>5;h3af?6=3f;ji7>5;|`053<72<0;6=u+1b09b3=O<080D968;%33<?7<a=<1<75f4683>>o3k3:17d;?:188k4d22900qo=>5;291?6=8r.:o?4i6:J7=7=O<1=0(<>7:09j03<722c?;7>5;h6`>5<<a<:1<75`1c794?=zj:;?6=4::183!7d:3l=7E:62:J7<2=#9921=6g;6;29?l202900e9m50;9j15<722e:n84?::a745=83?1<7>t$0a1>c0<@=397E:77:&24=<63`>=6=44i5594?=n<j0;66g:0;29?j7e=3:17pl<1383>0<729q/=n<5f79K0<4<@=2<7)??8;38m10=831b8:4?::k7g?6=3`?;6=44o0`6>5<<uk9:=7>55;294~"6k;0m:6F;939K0=1<,8:36<5f4783>>o3?3:17d:l:188m06=831d=o;50;9~f677290>6=4?{%3`6?`13A>2>6F;869'55>=92c?:7>5;h64>5<<a=i1<75f5183>>i6j<0;66sm31d94?3=83:p(<m=:g48L1?53A>3;6*>0982?l212900e9950;9j0f<722c><7>5;n3a1?6=3th8<h4?:483>5}#9j81j;5G4808L1>03-;;47?4i5494?=n<>0;66g;c;29?l372900c<l::188yg4f93:187>50z&2g7<a?2B?5?5G4958 46?2<1b8;4?::k64?6=3`;i87>5;n3a1?6=3th9m?4?:583>5}#9j81j:5G4808L1>03-;;47;4i5494?=n=90;66g>b583>>i6j<0;66sm28a94?2=83:p(<m=:g78L1?53A>3;6*>0982?l212900e9m50;9j15<722e:n84?::a6<d=83>1<7>t$0a1>c3<@=397E:77:&24=<63`>=6=44i5a94?=n=90;66a>b483>>{e;::1<7=50;2x 4e52=3:7E:62:J7<2=n<00;66g>4c83>>i6il0;66sm33d94?5=83:p(<m=:5;2?M2>:2B?4:5f4883>>o6<k0;66a>ad83>>{e;;:1<7:50;2x 4e528?=7E:62:J7<2=n<00;66g:2;29?l7ej3:17b?ne;29?xd4:l0;6>4?:1y'5f4=<0;0D97=;I6;3>o313:17d?;b;29?j7fm3:17pl<1g83>1<729q/=n<51448L1?53A>3;6g;9;29?l352900e<lm:188k4gb2900qo==d;297?6=8r.:o?4;909K0<4<@=2<7d:6:188m42e2900c<oj:188yg56m3:187>50z&2g7<6=?1C84<4H5:4?l2>2900e8<50;9j5gd=831d=lk50;9~f64d29086=4?{%3`6?2>92B?5?5G4958m1?=831b=9l50;9l5dc=831vn>?k:187>5<7s-;h>7?:6:J7=7=O<1=0e9750;9j17<722c:no4?::m2e`<722wi??l50;194?6|,8i9697>;I6:6>N30>1b844?::k20g<722e:mh4?::a74e=83>1<7>t$0a1>4313A>2>6F;869j0<<722c>>7>5;h3af?6=3f;ji7>5;|`06d<72:0;6=u+1b090<7<@=397E:77:k7=?6=3`;?n7>5;n3ba?6=3th8=o4?:583>5}#9j81=884H5;1?M2??2c?57>5;h71>5<<a8hi6=44o0cf>5<<uk9:m7>54;294~"6k;0:9;5G4808L1>03`>26=44i4094?=n9kh1<75`1`g94?=zj:;26=4;:183!7d:3;>:6F;939K0=1<a=31<75f5383>>o6jk0;66a>ad83>>{e;821<7:50;2x 4e528?=7E:62:J7<2=n<00;66g:2;29?l7ej3:17b?ne;29?xd4;l0;694?:1y'5f4=n<1C84<4H5:4?!7703;0e9850;9j0f<722c><7>5;n3a1?6=3th8?i4?:583>5}#9j81j85G4808L1>03-;;47?4i5494?=n<j0;66g:0;29?j7e=3:17pl<3b83>1<729q/=n<5f49K0<4<@=2<7)??8;38m10=831b8n4?::k64?6=3f;i97>5;|`07g<72=0;6=u+1b09b0=O<080D968;%33<?7<a=<1<75f4b83>>o283:17b?m5;29?xd4;h0;694?:1y'5f4=n<1C84<4H5:4?!7703;0e9850;9j0f<722c><7>5;n3a1?6=3th8?44?:583>5}#9j81j85G4808L1>03-;;47?4i5494?=n<j0;66g:0;29?j7e=3:17pl<3983>1<729q/=n<5f49K0<4<@=2<7)??8;38m10=831b8n4?::k64?6=3f;i97>5;|`003<72<0;6=u+1b09b==O<080D968;%33<?3<a=<1<75f4683>>o283:17d?m4;29?j7e=3:17pl=c183>1<729q/=n<51448L1?53A>3;6g;9;29?l352900e<lm:188k4gb2900qo<mf;290?6=8r.:o?4>579K0<4<@=2<7d:6:188m04=831b=ol50;9l5dc=831vn?lj:187>5<7s-;h>7?:6:J7=7=O<1=0e9750;9j17<722c:no4?::m2e`<722wi>oj50;694?6|,8i96<;9;I6:6>N30>1b844?::k66?6=3`;in7>5;n3ba?6=3th9nn4?:583>5}#9j81=884H5;1?M2??2c?57>5;h71>5<<a8hi6=44o0cf>5<<uk8jh7>54;294~"6k;0:9;5G4808L1>03`>26=44i4094?=n9kh1<75`1`g94?=zj;kh6=4;:183!7d:3;>:6F;939K0=1<a=31<75f5383>>o6jk0;66a>ad83>>{e:hh1<7:50;2x 4e528?=7E:62:J7<2=n<00;66g:2;29?l7ej3:17b?ne;29?xd5ih0;694?:1y'5f4=9<<0D97=;I6;3>o313:17d;=:188m4de2900c<oj:188yg4f13:187>50z&2g7<6=?1C84<4H5:4?l2>2900e8<50;9j5gd=831d=lk50;9~f6b5290>6=4?{%3`6?`13A>2>6F;869'55>=92c?:7>5;h64>5<<a=i1<75f5183>>i6j<0;66sm3e294?3=83:p(<m=:g48L1?53A>3;6*>0982?l212900e9950;9j0f<722c><7>5;n3a1?6=3th8h<4?:483>5}#9j81j55G4808L1>03-;;47;4i5494?=n<>0;66g:0;29?l7e<3:17b?m5;29?xd4l:0;684?:1y'5f4=n?1C84<4H5:4?!7703;0e9850;9j02<722c?o7>5;h73>5<<g8h>6=44}c1g0?6==3:1<v*>c38e2>N31;1C8594$02;>4=n<?0;66g;7;29?l2d2900e8>50;9l5g3=831vn>j::186>5<7s-;h>7h9;I6:6>N30>1/==651:k72?6=3`><6=44i5a94?=n=90;66a>b483>>{e;m<1<7;50;2x 4e52o<0D97=;I6;3>"6810:7d:9:188m11=831b8n4?::k64?6=3f;i97>5;|`0`2<72<0;6=u+1b09b3=O<080D968;%33<?7<a=<1<75f4683>>o3k3:17d;?:188k4d22900qo=k8;291?6=8r.:o?4i6:J7=7=O<1=0(<>7:09j03<722c?;7>5;h6`>5<<a<:1<75`1c794?=zj:o?6=4::183!7d:3l=7E:62:J7<2=#9921=6g;6;29?l202900e9m50;9j15<722e:n84?::a7`4=83?1<7>t$0a1>c><@=397E:77:&24=<23`>=6=44i5594?=n=90;66g>b583>>i6j<0;66sm3d194?3=83:p(<m=:g48L1?53A>3;6*>0982?l212900e9950;9j0f<722c><7>5;n3a1?6=3th8i84?:483>5}#9j81j;5G4808L1>03-;;47?4i5494?=n<>0;66g;c;29?l372900c<l::188yg5b>3:197>50z&2g7<a>2B?5?5G4958 46?281b8;4?::k73?6=3`>h6=44i4294?=h9k?1<75rb2g4>5<2290;w)?l2;d5?M2>:2B?4:5+11:95>o3>3:17d:8:188m1e=831b9=4?::m2f0<722wi?h650;794?6|,8i96k84H5;1?M2??2.:<54>;h65>5<<a==1<75f4b83>>o283:17b?m5;29?xd4m00;684?:1y'5f4=n?1C84<4H5:4?!7703;0e9850;9j02<722c?o7>5;h73>5<<g8h>6=44}c1fe?6==3:1<v*>c38e2>N31;1C8594$02;>4=n<?0;66g;7;29?l2d2900e8>50;9l5g3=831vn>m9:186>5<7s-;h>7h9;I6:6>N30>1/==651:k72?6=3`><6=44i5a94?=n=90;66a>b483>>{e;j?1<7;50;2x 4e52o<0D97=;I6;3>"6810:7d:9:188m11=831b8n4?::k64?6=3f;i97>5;|`0g6<72<0;6=u+1b09b3=O<080D968;%33<?7<a=<1<75f4683>>o3k3:17d;?:188k4d22900qo=l2;291?6=8r.:o?4i6:J7=7=O<1=0(<>7:09j03<722c?;7>5;h6`>5<<a<:1<75`1c794?=zj:i?6=4::183!7d:3l=7E:62:J7<2=#9921=6g;6;29?l202900e9m50;9j15<722e:n84?::a7f6=83?1<7>t$0a1>c0<@=397E:77:&24=<63`>=6=44i5594?=n<j0;66g:0;29?j7e=3:17pl<bg83>0<729q/=n<5f99K0<4<@=2<7)??8;78m10=831b8:4?::k64?6=3`;i87>5;n3a1?6=3th8o<4?:483>5}#9j81j;5G4808L1>03-;;47?4i5494?=n<>0;66g;c;29?l372900c<l::188yg5em3:197>50z&2g7<a02B?5?5G4958 46?2<1b8;4?::k73?6=3`?;6=44i0`7>5<<g8h>6=44}c1a7?6=;3:1<v*>c387=4=O<080D968;h6:>5<<a8>i6=44o0cf>5<<uk9i>7>53;294~"6k;0?5<5G4808L1>03`>26=44i06a>5<<g8kn6=44}c1b=?6=<3:1<v*>c38213=O<080D968;h6:>5<<a<81<75f1c`94?=h9ho1<75rb2`2>5<4290;w)?l2;6:5>N31;1C8594i5;94?=n9=h1<75`1`g94?=zj:k<6=4;:183!7d:3;>:6F;939K0=1<a=31<75f5383>>o6jk0;66a>ad83>>{e;k:1<7=50;2x 4e52=3:7E:62:J7<2=n<00;66g>4c83>>i6il0;66sm3`794?2=83:p(<m=:075?M2>:2B?4:5f4883>>o2:3:17d?mb;29?j7fm3:17pl<ag83>6<729q/=n<54838L1?53A>3;6g;9;29?l73j3:17b?ne;29?xd4i:0;694?:1y'5f4=9<<0D97=;I6;3>o313:17d;=:188m4de2900c<oj:188yg5fm3:1?7>50z&2g7<3181C84<4H5:4?l2>2900e<:m:188k4gb2900qo=n1;290?6=8r.:o?4>579K0<4<@=2<7d:6:188m04=831b=ol50;9l5dc=831vn>ok:180>5<7s-;h>7:61:J7=7=O<1=0e9750;9j51d=831d=lk50;9~f6?a290?6=4?{%3`6?72>2B?5?5G4958m1?=831b9?4?::k2fg<722e:mh4?::a7de=8391<7>t$0a1>1?63A>2>6F;869j0<<722c:8o4?::m2e`<722wi?4j50;694?6|,8i96<;9;I6:6>N30>1b844?::k66?6=3`;in7>5;n3ba?6=3th8mo4?:283>5}#9j8184?4H5;1?M2??2c?57>5;h37f?6=3f;ji7>5;|`0=g<72=0;6=u+1b09500<@=397E:77:k7=?6=3`?96=44i0`a>5<<g8kn6=44}c1eg?6==3:1<v*>c38e2>N31;1C8594$02;>4=n<?0;66g;7;29?l2d2900e8>50;9l5g3=831vn>hm:186>5<7s-;h>7h9;I6:6>N30>1/==651:k72?6=3`><6=44i5a94?=n=90;66a>b483>>{e;ok1<7;50;2x 4e52o<0D97=;I6;3>"6810:7d:9:188m11=831b8n4?::k64?6=3f;i97>5;|`0b<<72<0;6=u+1b09b3=O<080D968;%33<?7<a=<1<75f4683>>o3k3:17d;?:188k4d22900qo=i8;291?6=8r.:o?4i6:J7=7=O<1=0(<>7:09j03<722c?;7>5;h6`>5<<a<:1<75`1c794?=zj:l<6=4::183!7d:3l=7E:62:J7<2=#9921=6g;6;29?l202900e9m50;9j15<722e:n84?::a7c0=83?1<7>t$0a1>c0<@=397E:77:&24=<63`>=6=44i5594?=n<j0;66g:0;29?j7e=3:17pl<f483>0<729q/=n<5f79K0<4<@=2<7)??8;38m10=831b8:4?::k7g?6=3`?;6=44o0`6>5<<uk9m87>55;294~"6k;0m:6F;939K0=1<,8:36<5f4783>>o3?3:17d:l:188m06=831d=o;50;9~f637290?6=4?{%3`6?72>2B?5?5G4958m1?=831b9?4?::k2fg<722e:mh4?::a707=83>1<7>t$0a1>4313A>2>6F;869j0<<722c>>7>5;h3af?6=3f;ji7>5;|`017<72=0;6=u+1b09500<@=397E:77:k7=?6=3`?96=44i0`a>5<<g8kn6=44}c167?6=<3:1<v*>c38213=O<080D968;h6:>5<<a<81<75f1c`94?=h9ho1<75rb277>5<3290;w)?l2;362>N31;1C8594i5;94?=n=;0;66g>bc83>>i6il0;66sm37194?2=83:p(<m=:075?M2>:2B?4:5f4883>>o2:3:17d?mb;29?j7fm3:17pl<6583>1<729q/=n<51448L1?53A>3;6g;9;29?l352900e<lm:188k4gb2900qo=95;290?6=8r.:o?4>579K0<4<@=2<7d:6:188m04=831b=ol50;9l5dc=831vn>89:187>5<7s-;h>7?:6:J7=7=O<1=0e9750;9j17<722c:no4?::m2e`<722wi?;950;694?6|,8i96<;9;I6:6>N30>1b844?::k66?6=3`;in7>5;n3ba?6=3th8;44?:583>5}#9j81=884H5;1?M2??2c?57>5;h71>5<<a8hi6=44o0cf>5<<uk9<m7>54;294~"6k;0:9;5G4808L1>03`>26=44i4094?=n9kh1<75`1`g94?=zj:=i6=4;:183!7d:3;>:6F;939K0=1<a=31<75f5383>>o6jk0;66a>ad83>>{e;>i1<7:50;2x 4e528?=7E:62:J7<2=n<00;66g:2;29?l7ej3:17b?ne;29?xd4?m0;694?:1y'5f4=9<<0D97=;I6;3>o313:17d;=:188m4de2900c<oj:188yg5?k3:187>50z&2g7<a?2B?5?5G4958 46?2<1b8;4?::k64?6=3`;i87>5;n3a1?6=3th84i4?:583>5}#9j81j:5G4808L1>03-;;47;4i5494?=n=90;66g>b583>>i6j<0;66sm39:94?3=83:p(<m=:g:8L1?53A>3;6*>0986?l212900e9950;9j15<722c:n94?::m2f0<722wi8>h50;794?6|,8i96k74H5;1?M2??2.:<54>;h65>5<<a==1<75f5183>>o6j?0;66a>b483>>{e<:o1<7;50;2x 4e52o30D97=;I6;3>"6810:7d:9:188m11=831b9=4?::k2f3<722e:n84?::a06b=83?1<7>t$0a1>c?<@=397E:77:&24=<63`>=6=44i5594?=n=90;66g>b783>>i6j<0;66sm42a94?3=83:p(<m=:g;8L1?53A>3;6*>0982?l212900e9950;9j15<722c:n;4?::m2f0<722wi8>l50;794?6|,8i96k74H5;1?M2??2.:<54>;h65>5<<a==1<75f5183>>o6j?0;66a>b483>>{e<:k1<7;50;2x 4e52o30D97=;I6;3>"6810:7d:9:188m11=831b9=4?::k2f3<722e:n84?::a06>=83?1<7>t$0a1>c?<@=397E:77:&24=<63`>=6=44i5594?=n=90;66g>b783>>i6j<0;66sm42594?3=83:p(<m=:g;8L1?53A>3;6*>0982?l212900e9950;9j15<722c:n;4?::m2f0<722wi8>850;794?6|,8i96k74H5;1?M2??2.:<54>;h65>5<<a==1<75f5183>>o6j?0;66a>b483>>{e<:?1<7;50;2x 4e52o30D97=;I6;3>"6810:7d:9:188m11=831b9=4?::k2f3<722e:n84?::a062=83?1<7>t$0a1>c?<@=397E:77:&24=<63`>=6=44i5594?=n=90;66g>b783>>i6j<0;66sm42194?3=83:p(<m=:g;8L1?53A>3;6*>0982?l212900e9950;9j15<722c:n;4?::m2f0<722wi8><50;794?6|,8i96k74H5;1?M2??2.:<54>;h65>5<<a==1<75f5183>>o6j?0;66a>b483>>{e<:;1<7;50;2x 4e52o30D97=;I6;3>"6810:7d:9:188m11=831b9=4?::k2f3<722e:n84?::a066=83?1<7>t$0a1>c?<@=397E:77:&24=<63`>=6=44i5594?=n=90;66g>b783>>i6j<0;66sm43d94?3=83:p(<m=:g;8L1?53A>3;6*>0982?l212900e9950;9j15<722c:n;4?::m2f0<722wi8?j50;794?6|,8i96k74H5;1?M2??2.:<54>;h65>5<<a==1<75f5183>>o6j?0;66a>b483>>{e<;i1<7;50;2x 4e52o30D97=;I6;3>"6810:7d:9:188m11=831b9=4?::k2f3<722e:n84?::a07d=83?1<7>t$0a1>c?<@=397E:77:&24=<63`>=6=44i5594?=n=90;66g>b783>>i6j<0;66sm43c94?3=83:p(<m=:g;8L1?53A>3;6*>0982?l212900e9950;9j15<722c:n;4?::m2f0<722wi8?750;794?6|,8i96k74H5;1?M2??2.:<54>;h65>5<<a==1<75f5183>>o6j?0;66a>b483>>{e<;21<7;50;2x 4e52o30D97=;I6;3>"6810:7d:9:188m11=831b9=4?::k2f3<722e:n84?::a071=83?1<7>t$0a1>c?<@=397E:77:&24=<63`>=6=44i5594?=n=90;66g>b783>>i6j<0;66sm43494?3=83:p(<m=:g;8L1?53A>3;6*>0982?l212900e9950;9j15<722c:n;4?::m2f0<722wi8?;50;794?6|,8i96k74H5;1?M2??2.:<54>;h65>5<<a==1<75f5183>>o6j?0;66a>b483>>{e<;>1<7;50;2x 4e52o30D97=;I6;3>"6810:7d:9:188m11=831b9=4?::k2f3<722e:n84?::a013=83?1<7>t$0a1>c?<@=397E:77:&24=<63`>=6=44i5594?=n=90;66g>b783>>i6j<0;66sm45694?3=83:p(<m=:g;8L1?53A>3;6*>0982?l212900e9950;9j15<722c:n;4?::m2f0<722wi89=50;794?6|,8i96k74H5;1?M2??2.:<54>;h65>5<<a==1<75f5183>>o6j?0;66a>b483>>{e<=81<7;50;2x 4e52o30D97=;I6;3>"6810:7d:9:188m11=831b9=4?::k2f3<722e:n84?::a017=83?1<7>t$0a1>c?<@=397E:77:&24=<63`>=6=44i5594?=n=90;66g>b783>>i6j<0;66sm45294?3=83:p(<m=:g;8L1?53A>3;6*>0982?l212900e9950;9j15<722c:n;4?::m2f0<722wi8>750;794?6|,8i96k74H5;1?M2??2.:<54>;h65>5<<a==1<75f5183>>o6j?0;66a>b483>>{e<;o1<7;50;2x 4e52o30D97=;I6;3>"6810:7d:9:188m11=831b9=4?::k2f3<722e:n84?::a075=83?1<7>t$0a1>c?<@=397E:77:&24=<63`>=6=44i5594?=n=90;66g>b783>>i6j<0;66sm43094?3=83:p(<m=:g;8L1?53A>3;6*>0982?l212900e9950;9j15<722c:n;4?::m2f0<722wi85?50;194?6|,8i96<;?;I6:6>N30>1/==65119jbf<722cmh7>5;n3ba?6=3th?;>4?:283>5}#9j81=8>4H5;1?M2??2.:<54>0:keg?6=3`lo6=44o0cf>5<<uk8?47>53;294~"6k;0:9=5G4808L1>03-;;47?8;hd`>5<<aon1<75`1`g94?=zj8o=6=4<:183!7d:3;><6F;939K0=1<,8:36<94iga94?=nnm0;66a>ad83>>{e9m81<7=50;2x 4e528?;7E:62:J7<2=#9921=:5ffb83>>oal3:17b?ne;29?xd6l80;6>4?:1y'5f4=9<:0D97=;I6;3>"6810:;6gic;29?l`c2900c<oj:188yg7c83:1?7>50z&2g7<6=91C84<4H5:4?!7703;<7dhl:188mcb=831d=lk50;9~f4ea29086=4?{%3`6?7282B?5?5G4958 46?28=0ekm50;9jba<722e:mh4?::a5fc=8391<7>t$0a1>4373A>2>6F;869'55>=9>1bjn4?::ke`?6=3f;ji7>5;|`2ga<72:0;6=u+1b09506<@=397E:77:&24=<6?2cmo7>5;hdg>5<<g8kn6=44}c3`g?6=;3:1<v*>c38215=O<080D968;%33<?703`lh6=44igf94?=h9ho1<75rb0aa>5<4290;w)?l2;364>N31;1C8594$02;>41<aoi1<75ffe83>>i6il0;66sm1bc94?5=83:p(<m=:073?M2>:2B?4:5+11:952=nnj0;66gid;29?j7fm3:17pl>c883>6<729q/=n<51428L1?53A>3;6*>09823>oak3:17dhk:188k4gb2900qo?l8;297?6=8r.:o?4>519K0<4<@=2<7)??8;34?l`d2900ekj50;9l5dc=831vn<m8:180>5<7s-;h>7?:0:J7=7=O<1=0(<>7:058mce=831bji4?::m2e`<722wi=n850;194?6|,8i96<;?;I6:6>N30>1/==65169jbf<722cmh7>5;n3ba?6=3th:o84?:283>5}#9j81=8>4H5;1?M2??2.:<54>7:keg?6=3`lo6=44o0cf>5<<uk;h87>53;294~"6k;0:9=5G4808L1>03-;;47?8;hd`>5<<aon1<75`1`g94?=zj8i86=4<:183!7d:3;><6F;939K0=1<,8:36<94iga94?=nnm0;66a>ad83>>{e:h:1<7:50;2x 4e528?:7E:62:J7<2=#9921j<5ffb83>>oal3:17dhj:188k4gb2900qo<;a;290?6=8r.:o?4>509K0<4<@=2<7)??8;3e?l`d2900ekj50;9jb`<722e:mh4?::a5`>=83>1<7>t$0a1>4363A>2>6F;869'55>=9o1bjn4?::ke`?6=3`ln6=44o0cf>5<<uk82i7>55;294~"6k;0:9?5G4808L1>03-;;47?>;hd`>5<<aon1<75ffd83>>oan3:17b?ne;29?xd5<j0;684?:1y'5f4=9<80D97=;I6;3>"6810:56gic;29?l`c2900ekk50;9jbc<722e:mh4?::a5`g=83?1<7>t$0a1>4353A>2>6F;869'55>=901bjn4?::ke`?6=3`ln6=44igd94?=h9ho1<75rb3c7>5<2290;w)?l2;366>N31;1C8594$02;>4e<aoi1<75ffe83>>oam3:17dhi:188k4gb2900qo=7b;297?6=8r.:o?4>519K0<4<@=2<7)??8;60?l`d2900ekj50;9l5dc=831vn?77:187>5<7s-;h>7?:1:J7=7=O<1=0(<>7:3a8mce=831bji4?::kea?6=3f;ji7>5;|`00=<72<0;6=u+1b09504<@=397E:77:&24=<6j2cmo7>5;hdg>5<<aoo1<75ffg83>>i6il0;66sm35;94?5=83:p(<m=:073?M2>:2B?4:5+11:95d=nnj0;66gid;29?j7fm3:17pl=4d83>6<729q/=n<51428L1?53A>3;6*>09823>oak3:17dhk:188k4gb2900qo?jc;297?6=8r.:o?4>519K0<4<@=2<7)??8;34?l`d2900ekj50;9l5dc=831vn?;?:187>5<7s-;h>7?:1:J7=7=O<1=0(<>7:0d8mce=831bji4?::kea?6=3f;ji7>5;|`2a`<72=0;6=u+1b09507<@=397E:77:&24=<6n2cmo7>5;hdg>5<<aoo1<75`1`g94?=zj;?96=4::183!7d:3;>>6F;939K0=1<,8:36<74iga94?=nnm0;66gie;29?l`a2900c<oj:188yg7a83:197>50z&2g7<6=;1C84<4H5:4?!7703;27dhl:188mcb=831bjh4?::keb?6=3f;ji7>5;|`72f<72=0;6=u+1b09507<@=397E:77:&24=<292cmo7>5;hdg>5<<aoo1<75`1`g94?=zj;3<6=4::183!7d:3;>>6F;939K0=1<,8:3655ffb83>>oal3:17dhj:188mc`=831d=lk50;9~f6>029086=4?{%3`6?7282B?5?5G4958 46?28n0ekm50;9jba<722e:mh4?::a727=8391<7>t$0a1>4373A>2>6F;869'55>=9m1bjn4?::ke`?6=3f;ji7>5;|`01`<72:0;6=u+1b09506<@=397E:77:&24=<6l2cmo7>5;hdg>5<<g8kn6=44}c0`e?6=;3:1<v*>c38215=O<080D968;%33<?7c3`lh6=44igf94?=h9ho1<75rb3`4>5<4290;w)?l2;364>N31;1C8594$02;>4b<aoi1<75ffe83>>i6il0;66sm39494?3=83:p(<m=:071?M2>:2B?4:5+11:95`=nnj0;66gid;29?l`b2900ekh50;9l5dc=831vn>9?:186>5<7s-;h>7?:2:J7=7=O<1=0(<>7:0g8mce=831bji4?::kea?6=3`lm6=44o0cf>5<<uk9>h7>55;294~"6k;0:9?5G4808L1>03-;;47?j;hd`>5<<aon1<75ffd83>>oan3:17b?ne;29?xd5k00;684?:1y'5f4=9<80D97=;I6;3>"6810:i6gic;29?l`c2900ekk50;9jbc<722e:mh4?::a6g0=83?1<7>t$0a1>4353A>2>6F;869'55>=9l1bjn4?::ke`?6=3`ln6=44igd94?=h9ho1<75rb2:6>5<2290;w)?l2;366>N31;1C8594$02;>4c<aoi1<75ffe83>>oam3:17dhi:188k4gb2900qo=9f;291?6=8r.:o?4>539K0<4<@=2<7)??8;3f?l`d2900ekj50;9jb`<722cmj7>5;n3ba?6=3th89n4?:483>5}#9j81=8<4H5;1?M2??2.:<54>e:keg?6=3`lo6=44igg94?=nno0;66a>ad83>>{e:j21<7;50;2x 4e528?97E:62:J7<2=#9921=h5ffb83>>oal3:17dhj:188mc`=831d=lk50;9~f7d2290>6=4?{%3`6?72:2B?5?5G4958 46?28o0ekm50;9jba<722cmi7>5;hde>5<<g8kn6=44}c1;0?6==3:1<v*>c38217=O<080D968;%33<?7b3`lh6=44igf94?=nnl0;66gif;29?j7fm3:17pl<6d83>0<729q/=n<51408L1?53A>3;6*>0982a>oak3:17dhk:188mcc=831bjk4?::m2e`<722wi?8l50;794?6|,8i96<;=;I6:6>N30>1/==651d9jbf<722cmh7>5;hdf>5<<aol1<75`1`g94?=zj;i<6=4::183!7d:3;>>6F;939K0=1<,8:36<k4iga94?=nnm0;66gie;29?l`a2900c<oj:188yg4e<3:197>50z&2g7<6=;1C84<4H5:4?!7703;n7dhl:188mcb=831bjh4?::keb?6=3f;ji7>5;|`1gc<72=0;6=u+1b09507<@=397E:77:&24=<a:2cmo7>5;hdg>5<<aoo1<75`1`g94?=zj:2m6=4::183!7d:3;>>6F;939K0=1<,8:36<84iga94?=nnm0;66gie;29?l`a2900c<oj:188yg5?i3:197>50z&2g7<6=;1C84<4H5:4?!7703;=7dhl:188mcb=831bjh4?::keb?6=3f;ji7>5;|`0<6<72<0;6=u+1b09504<@=397E:77:&24=<6m2cmo7>5;hdg>5<<aoo1<75ffg83>>i6il0;66sm37f94?3=83:p(<m=:071?M2>:2B?4:5+11:95`=nnj0;66gid;29?l`b2900ekh50;9l5dc=831vn>;n:186>5<7s-;h>7?:2:J7=7=O<1=0(<>7:0g8mce=831bji4?::kea?6=3`lm6=44o0cf>5<<uk8h:7>55;294~"6k;0:9?5G4808L1>03-;;47?j;hd`>5<<aon1<75ffd83>>oan3:17b?ne;29?xd5j:0;684?:1y'5f4=9<80D97=;I6;3>"6810:i6gic;29?l`c2900ekk50;9jbc<722e:mh4?::a603=8391<7>t$0a1>4373A>2>6F;869'55>=9m1bjn4?::ke`?6=3f;ji7>5;|`2b6<72:0;6=u+1b09506<@=397E:77:&24=<6l2cmo7>5;hdg>5<<g8kn6=44}c06<?6=<3:1<v*>c38214=O<080D968;%33<?7?3`lh6=44igf94?=nnl0;66a>ad83>>{e9o<1<7:50;2x 4e528?:7E:62:J7<2=#9921=55ffb83>>oal3:17dhj:188k4gb2900qo=60;297?6=8r.:o?4>519K0<4<@=2<7)??8;58mce=831bji4?::m2e`<722wi>h650;094?6|,8i96<:i;I6:6>N30>1/==657:keg?6=3f;ji7>5;|`1a3<72;0;6=u+1b0951`<@=397E:77:&24=<03`lh6=44o0cf>5<<uk8n87>52;294~"6k;0:8k5G4808L1>03-;;4794iga94?=h9ho1<75rb3g1>5<5290;w)?l2;37b>N31;1C8594$02;>2=nnj0;66a>ad83>>{e:l:1<7<50;2x 4e528>m7E:62:J7<2=#9921;6gic;29?j7fm3:17pl=dd83>7<729q/=n<515d8L1?53A>3;6*>0984?l`d2900c<oj:188yg4ck3:1>7>50z&2g7<6<o1C84<4H5:4?!7703=0ekm50;9l5dc=831vn?jn:181>5<7s-;h>7?;f:J7=7=O<1=0(<>7:69jbf<722e:mh4?::a7dg=8381<7>t$0a1>42a3A>2>6F;869'55>=?2cmo7>5;n3ba?6=3th8m54?:383>5}#9j81=9h4H5;1?M2??2.:<548;hd`>5<<g8kn6=44}c1b2?6=:3:1<v*>c3820c=O<080D968;%33<?1<aoi1<75`1`g94?=zj:k?6=4=:183!7d:3;?j6F;939K0=1<,8:36:5ffb83>>i6il0;66sm3`094?4=83:p(<m=:06e?M2>:2B?4:5+11:93>oak3:17b?ne;29?xd4i90;6?4?:1y'5f4=9=l0D97=;I6;3>"6810<7dhl:188k4gb2900qo=6e;296?6=8r.:o?4>4g9K0<4<@=2<7)??8;58mce=831d=lk50;9~f6?d29096=4?{%3`6?73n2B?5?5G4958 46?2>1bjn4?::m2e`<722wi>k<50;094?6|,8i96<:i;I6:6>N30>1/==657:keg?6=3f;ji7>5;|`0f1<72;0;6=u+1b0951`<@=397E:77:&24=<03`lh6=44o0cf>5<<uk99=7>53;294~"6k;0:9=5G4808L1>03-;;47?k;hd`>5<<aon1<75`1`g94?=zj:896=4<:183!7d:3;><6F;939K0=1<,8:36<j4iga94?=nnm0;66a>ad83>>{e;;91<7=50;2x 4e528?;7E:62:J7<2=#9921=i5ffb83>>oal3:17b?ne;29?xd4:=0;6>4?:1y'5f4=9<:0D97=;I6;3>"6810:h6gic;29?l`c2900c<oj:188yg55=3:1?7>50z&2g7<6=91C84<4H5:4?!7703;o7dhl:188mcb=831d=lk50;9~f64129086=4?{%3`6?7282B?5?5G4958 46?28n0ekm50;9jba<722e:mh4?::a771=8391<7>t$0a1>4373A>2>6F;869'55>=9m1bjn4?::ke`?6=3f;ji7>5;|`06=<72:0;6=u+1b09506<@=397E:77:&24=<6l2cmo7>5;hdg>5<<g8kn6=44}c11=?6=;3:1<v*>c38215=O<080D968;%33<?7c3`lh6=44igf94?=h9ho1<75rb2;2>5<4290;w)?l2;364>N31;1C8594$02;>2=nnj0;66gid;29?j7fm3:17pl<4`83>0<729q/=n<51468L1?53A>3;6*>0987?l`d2900ekj50;9jb`<722cmj7>5;n37g?6=3th9994?:783>5}#9j81=8=4H5;1?M2??2.:<54=0:keg?6=3`lo6=44igg94?=nno0;66a>4b83>>i6il0;66sm1g094?0=83:p(<m=:070?M2>:2B?4:5+11:965=nnj0;66gid;29?l`b2900ekh50;9l51e=831d=lk50;9~f10f290jm7>50zJ7<2=#9j81=o94Z579e~462;8157o513827?d=k3;?6<;5}%37e?4<,8:;6>5+11397>"68;087)??3;18 4632:1/==;53:&243<43-om6k=4$02:>6=#99k1?6*>0c80?!77k390(<>k:29'55c=;2.:<k4<;%324?5<,8;:6>5+10097>"69:087)?>4;18 4722:1/=<853:&252<43-;:47=4$03:>6=#98k1?6*>1c80?!76k390(<?k:29'54c=;2.:=k4<;%314?5<,88:6>5+13097>"6::087)?=4;18 4422:1/=?853:&262<43-;947=4$00:>6=#9;k1?6*>2c80?!75k390(<<k:29'57c=;2.:>k4<;%304?5<,89:6>5+12097>"6;:087)?<4;18 4522:1/=>853:&272<43-;847=4$01:>6=#9:k1?6*>3c80?!74k390(<=k:29'56c=;2.:?k4<;%374?5<,8>:6>5+15097>"6<:087)?;4;18 4222:1/=9853:&202<43-;?47=4$06:>7=#9ki18<5+11597>"6jl097):7c;3a<>"30m0:n55ac183?kc5291e=o75259m5gg=:=1e85k5259m0=`=:=1/j=4i3:&2fc<53`>j6=44i5`94?=n<1k1<75fed83>>o>i3:1(<l<:8f8j4d52:10e<m>:188m60=83.:n>4<5:l2f7<732c887>5$0`0>63<f8h96<54i2194?"6j:0896`>b381?>o4:3:1(<l<:278j4d52:10e>?50;&2f6<4=2d:n?4;;:k04?6=,8h86>;4n0`1>0=<a;l1<7*>b2801>h6j;0=76g=e;29 4d42:?0b<l=:698m7b=83.:n>4<5:l2f7<?32c?<7>5$0`0>6`<f8h96=54i2g94?"6j:08j6`>b382?>o4l3:1(<l<:2d8j4d52;10e>m50;&2f6<4n2d:n?4<;:k0f?6=,8h86>h4n0`1>1=<a:k1<7*>b280b>h6j;0>76g<9;29 4d42:l0b<l=:798m6>=83.:n>4<f:l2f7<032c8;7>5$0`0>6`<f8h96554i7a94?"6j:0=n6`>b383?>o1i3:1(<l<:7`8j4d52810e;650;&2f6<1j2d:n?4=;:k53?6=,8h86;l4n0`1>6=<a?<1<7*>b285f>h6j;0?76g95;29 4d42?h0b<l=:498m32=83.:n>49b:l2f7<132c=?7>5$0`0>3d<f8h96:54i7094?"6j:0=n6`>b38;?>o193:1(<l<:7`8j4d52010e;>50;&2f6<1j2d:n?4n;:k6b?6=,8h86;l4n0`1>g=<a<n1<7*>b285f>h6j;0h76g:c;29 4d42?h0b<l=:e98m0d=83.:n>49b:l2f7<b32c>m7>5$0`0>3d<f8h96k54i4;94?"6j:0=n6`>b3824>=n=10;6)?m3;4a?k7e:3;:76g:7;29 4d42?h0b<l=:008?l31290/=o=56c9m5g4=9:10e8;50;&2f6<1j2d:n?4>4:9j11<72-;i?78m;o3a6?7232c<?7>5$0`0>3d<f8h96<84;h51>5<#9k91:o5a1c0952=<a>;1<7*>b285f>h6j;0:465f7183>!7e;3<i7c?m2;3:?>o1n3:1(<l<:7`8j4d528k07d8j:18'5g5=>k1e=o<51c98m3b=83.:n>49b:l2f7<6k21b:44?:%3a7?0e3g;i>7?k;:k6a?6=,8h86;l4n0`1>4c<3`?86=4+1c192g=i9k81=k54i8;94?"6j:0246`>b383?>o>?3:1(<l<:8:8j4d52810e4850;&2f6<>02d:n?4=;:k:1?6=,8h86464n0`1>6=<gmk1<7*>b28g=>h6j;0;76ak8;29 4d42m30b<l=:098ka0=83.:n>4k9:l2f7<532eo97>5$0`0>a?<f8h96>54oe694?"6j:0o56`>b387?>ic;3:1(<l<:e;8j4d52<10ci<50;&2f6<c12d:n?49;:mg5?6=,8h86i74n0`1>2=<gm:1<7*>b28g=>h6j;0376alf;29 4d42m30b<l=:898kfc=83.:n>4k9:l2f7<f32ehh7>5$0`0>a?<f8h96o54ob`94?"6j:0o56`>b38`?>idi3:1(<l<:e;8j4d52m10cn750;&2f6<c12d:n?4j;:m`<?6=,8h86i74n0`1>c=<gj=1<7*>b28g=>h6j;0:<65`c783>!7e;3n27c?m2;32?>id=3:1(<l<:e;8j4d528807bm;:18'5g5=l01e=o<51298kf5=83.:n>4k9:l2f7<6<21do?4?:%3a7?b>3g;i>7?:;:mf5?6=,8h86i74n0`1>40<3fo;6=4+1c19`<=i9k81=:54oed94?"6j:0o56`>b382<>=hll0;6)?m3;f:?k7e:3;276akd;29 4d42m30b<l=:0c8?jbd290/=o=5d89m5g4=9k10cil50;&2f6<c12d:n?4>c:9l`2<72-;i?7j6;o3a6?7c32eho7>5$0`0>a?<f8h96<k4;na2>5<#9k91h45a1c095c=<gli1<7*>b28ff>h6j;0;76aja;29 4d42lh0b<l=:098k`?=83.:n>4jb:l2f7<532en47>5$0`0>`d<f8h96>54idf94?=n9j:1<75f49`94?=n0m0;6)?m3;:`?k7e:3:07d6m:18'5g5=0j1e=o<51:9j<<<72-;i?76l;o3a6?4<3`236=4+1c19<f=i9k81?65f8683>!7e;32h7c?m2;68?l>1290/=o=58b9m5g4==21b484?:%3a7?>d3g;i>784;h:7>5<#9k914n5a1c093>=n0:0;6)?m3;:`?k7e:3207d6=:18'5g5=0j1e=o<59:9j<4<72-;i?76l;o3a6?g<3`2;6=4+1c19<f=i9k81n65f7d83>!7e;32h7c?m2;a8?l1c290/=o=58b9m5g4=l21b;n4?:%3a7?>d3g;i>7k4;h5a>5<#9k914n5a1c09b>=n?h0;6)?m3;:`?k7e:3;;76g89;29 4d421i0b<l=:038?l1?290/=o=58b9m5g4=9;10e:950;&2f6<?k2d:n?4>3:9j33<72-;i?76l;o3a6?7332c<97>5$0`0>=e<f8h96<;4;h;7>5<#9k914n5a1c0953=<a091<7*>b28;g>h6j;0:;65f9383>!7e;32h7c?m2;3;?>o>93:1(<l<:9a8j4d528307d7?:18'5g5=0j1e=o<51`98m=`=83.:n>47c:l2f7<6j21b4h4?:%3a7?>d3g;i>7?l;:k;e?6=,8h865m4n0`1>4b<3`=m6=4+1c19<f=i9k81=h54i6694?"6j:03o6`>b382b>=n1l0;6)?m3;;g?k7e:3:07d7l:18'5g5=1m1e=o<51:9j=g<72-;i?77k;o3a6?4<3fh36=4+1c19f2=i9k81<65`b783>!7e;3h<7c?m2;38?jd3290/=o=5b69m5g4=:21dn>4?:%3a7?d03g;i>7=4;n`1>5<#9k91n:5a1c090>=hj80;6)?m3;`4?k7e:3?07bl?:18'5g5=j>1e=o<56:9lec<72-;i?7l8;o3a6?1<3fkn6=4+1c19f2=i9k81465`ae83>!7e;3h<7c?m2;;8?jgd290/=o=5b69m5g4=i21dmo4?:%3a7?d03g;i>7l4;nc:>5<#9k91n:5a1c09g>=hi10;6)?m3;`4?k7e:3n07bo8:18'5g5=j>1e=o<5e:9le3<72-;i?7l8;o3a6?`<3fk>6=4+1c19f2=i9k81==54o`694?"6j:0i;6`>b3825>=hi:0;6)?m3;`4?k7e:3;976an2;29 4d42k=0b<l=:018?jg6290/=o=5b69m5g4=9=10cl>50;&2f6<e?2d:n?4>5:9lfc<72-;i?7l8;o3a6?7132eii7>5$0`0>g1<f8h96<94;n`g>5<#9k91n:5a1c095==<gki1<7*>b28a3>h6j;0:565`bc83>!7e;3h<7c?m2;3b?>iei3:1(<l<:c58j4d528h07bl6:18'5g5=j>1e=o<51b98kg3=83.:n>4m7:l2f7<6l21dml4?:%3a7?d03g;i>7?j;:m:b?6=,8h86o94n0`1>4`<3fo<6=4+1c19a3=i9k81<65`e483>!7e;3o=7c?m2;38?jc3290/=o=5e79m5g4=:21di>4?:%3a7?c13g;i>7=4;|q6=6<72?qU94=4=3c3>cb<5;3n6km4=3c7>c`<5;336kk4=3;4>ce<uz?2=7>57by]0d?<V<3h7S;6a:\7=d=Y=0<0R8:7;_7:f>X2<01U8l94^5c5?[2f=2T?m95Q4`18Z1g53W>j=6P;a19]0<`<V<k=7S;n5:\6e1=Y=h90R8o=;_7b5>X2i91U94h4^4;f?[3>82T>4k5Q59g8Z0>c3W?3o6P:8c9]1=g<V<227S;78:?7=6<ai27?;i4:0:?72c<2827?;l4:0:?73<<2827?;54:0:?732<2827?484:0:?7<1<28279i:4:2:?1a0<2:279i>4:2:?1a4<2:279hk4:2:?1`a<2:279ho4:2:?1`<<2:278=54>bc9>6f6==;16>oh5539>6gc==;16>oj5539>6ge==;16>lj5539>6de==;16>ll5539>6dg==;16>l75539>7d?==;16?l95539>7d3==;16?l=5539>7d7==;16?4h5539>7<b==;16?4l5539>706==;16?8?5539>704==;16?8=5539>702==;16?;=5539>732==;16?;;5539>730==;16?;95539>72?==;16?:o5539>72d==;16?:m5539>72b==;168;o59`9>03g=9j:0198n:5:a?821i32o70:9a;:a?821i32270:9a;:;?821i32<70:9a;:5?821i32>70:9a;:7?821i32870:9a;:1?821i32:70:9a;:3?821i3=n70:9a;5g?821i3=h70:9a;5a?821i3=j70:9a;5:?821i3=370:9a;54?821i3==70:9a;56?821i33?70:9a;;0?821i33970:9a;;2?821i33;70:9a;:e?821i32n70:9a;:b?821i3=m70:9a;57?821i33n70:9a;;`?821i33i7p}<8983>7}Y<0h01>67:0`6?xu21<0;6:uQ5878910b2=i0199l:0`7?820j3;i863;7e82f1=:<?l1=o:4=55b>4d33ty9m?4?:3y]16b<5;k96<l:;|q6e=<72:qU9l64=2;3>ce<5:3:6km4}r7;3?6=>>qU9594=3ag>10<5==:6984=553>10<5=<m6984=55:>10<5==36984=554>10<5;>=6984=366>10<5;>?6984=360>10<5;>96984=362>10<5;>;6984=31e>10<5;9n6984=3:f>10<5;2o6984=3:`>10<5;2i6984=3:b>10<5;226984=3:;>10<5;2<6984=3:5>10<5;=h6984=35a>10<5;=j6984=35:>10<5;=36984=354>10<5;==6984=356>10<5;=?6984=32;>10<5;:<6984=325>10<5;:>6984=327>10<5;:86984=321>10<5;::6984=323>10<5::?6984=220>10<5::96984=222>10<5::;6984=3de>10<5;lo6984=3d`>10<5;ln6984=235>10<5:;>6984=237>10<5:;86984=231>10<5:;:6984=233>10<5::m6984=22f>10<5;k:6984=3c1>10<5;3h6984=3;a>10<5=9m6984=51f>10<5=9o6984=51`>10<5=9i6984=51b>10<5=936984=514>10<5=9=6984=516>10<5=9?6984=510>10<5=996984=512>10<5=9;6984=50e>10<5=8o6984=50`>10<5=8i6984=50b>10<5=826984=50;>10<5=8<6984=505>10<5=8>6984=507>10<5=>>6984=567>10<5=>86984=561>10<5=>:6984=563>10<5=926984=50f>10<5=886984=501>10<5=<j69l4}r1;`?6=:rT>8>5239f95g3<uz?2h7>55dy]1<b<5=<n6984=55`>10<5==m6984=55a>10<5==o6984=55f>10<5==j6984=5:6>10<5=2?6984=0g7>10<58o86984=0g1>10<58o:6984=0g3>10<58nm6984=0ff>10<58no6984=0f`>10<5;8h6984=30a>10<5;8j6984=30:>10<5;836984=304>10<5;8=6984=306>10<5;8?6984=33b>10<5;;26984=33;>10<5;;<6984=335>10<5;;>6984=337>10<5;;86984=331>10<5;<j6984=34:>10<5;<36984=344>10<5;<=6984=346>10<5;<?6984=340>10<5;<96984=21f>10<5:9o6984=21`>10<5:9i6984=21b>10<5:926984=21;>10<5:>=6984=2f1>10<5:n;6984=2f2>10<5:n86984=2f7>10<5:n>6984=2f5>10<5:n<6984=2f;>10<5:o?6984=2g1>10<5:o86984=2g6>10<5:o=6984=2g4>10<5:o36984=2g:>10<5:oj6984=2a5>10<5:i>6984=2a0>10<5:i96984=2a7>10<5:i;6984=2`e>10<5:i:6984=2`f>10<5:lh6984=2da>10<5:lj6984=2d:>10<5:l36984=2d4>10<5:l=6984=2d6>10<5:l?6984=2:`>10<5:2o6984=2:;>10<5=<j69o4}r172?6=:rT>:55235495g3<uz>:m7>52z\655=:<:l1=o;4}r62=?6=:rT><k5242g95g3<uz>:47>52z\64`=:<:n1=o;4}r623?6=:rT><i5242a95g3<uz>::7>52z\64f=:<:h1=o;4}r621?6=:rT><o5242c95g3<uz>:?7>52z\64<=:<:21=o;4}r626?6=:rT><55242595g3<uz>:=7>52z\642=:<:<1=o;4}r624?6=:rT><;5242795g3<uz>;j7>52z\640=:<:>1=o;4}r63a?6=:rT><95242195g3<uz>;h7>52z\646=:<:81=o;4}r63g?6=:rT><?5242395g3<uz>;n7>52z\644=:<::1=o;4}r63e?6=:rT><=5243d95g3<uz>;47>52z\7b`=:<;n1=o;4}r633?6=:rT?ji5243a95g3<uz>;:7>52z\7bf=:<;h1=o;4}r631?6=:rT?jo5243c95g3<uz>;87>52z\7bd=:<;31=o;4}r637?6=:rT?j45243:95g3<uz>;>7>52z\7b==:<;=1=o;4}r635?6=:rT?j:5243495g3<uz>;<7>52z\7b3=:<;?1=o;4}r1eb?6=:rT?j85243695g3<uz>9=7>52z\653=:<=?1=o;4}r614?6=:rT>=85245695g3<uz>:j7>52z\651=:<=91=o;4}r62a?6=:rT>=>5245095g3<uz>:h7>52z\657=:<=;1=o;4}r62g?6=:rT>=<5245295g3<uz>:n7>52z\64d=:<:31=o;4}r620?6=:rT?jk5243g95g3<uz>;57>52z\7b1=:<;91=o;4}r1ea?6=:rT?j>5243095g3<uz>nn7>52z\7g2=:<?k1545rs5g:>5<5sW>h:63;6`85g>{t<l21<7<t^5a6?821i3<j7p};e683>7}Y<j>0198n:7:8yv2b>3:1>vP;c29>03g=>>1v9k::181[2d:27?:l496:p0`5=838pR9m?;<65e?023ty?i?4?:3y]0g`<5=<j6;:4}r6f5?6=:rT?nh5247c926=z{=o;6=4={_6a`>;3>h02;6s|4ed94?4|V=hh70:9a;41?xu3ll0;6?uQ4c`8910f2?;0q~:kd;296~X3jh168;o5619~w1bd2909wS:m9:?72d<2n2wx8il50;0xZ1d?34>=m7;k;|q7`d<72;qU8o94=54b>0e<uz>o47>52z\7f0=:<?k19o5rs5f4>5<5sW>i863;6`86e>{t<m<1<7<t^5`0?821i33=7p};d483>7}Y<k80198n:4;8yv2c<3:1>vP;b09>03g==11v9j<:181[2e827?:l4:7:p0a4=838pR9oi;<65e?313ty?h<4?:3y]0dc<5=<j68;4}r6g4?6=:rT?mi5247c911=z{=im6=4={_6bg>;3>h0<?6s|4g094?4|V=io70:9a;51?xu3n80;6?uQ4ba8910f20?0q~:i0;296~X3kk168;o5709~w1ca2909wS:la:?72d<082wx8hk50;0xZ1e>34>=m78i;|q7aa<72;qU8n64=54b>3c<uz>no7>52z\7g4=:<?k1:i5rs5g7>5<5sW>i:63;6`85=>{t<m31<7<t^5ca?821i3?n7p};cd83>7}Y<hk0198n:418yv72i3:1nv3;9582f5=::l3184522e;90<=:;82184522ca90<=::h3184523``90<=:;0h1845234290<=:;?91845236;90<=z{;in6=4={<0``?37348hj7?ne:p020=83;3w0<ld;3a0>;3?00:n85231690f=:;9918n5231090f=:;9;18n5231290f=::ol18n522gf90f=::oi1=o:4=3df>1e<5:;=69m4=236>1e<5:;?69m4=230>1e<5:;969m4=232>1e<5:;;69m4=22e>1e<5::n69m4=3c2>4d3348j>7?m4:?1=f<3k2795o4;c:p6fb=83>p1?mk:0`6?84>m3lm70:9c;d`?84>?3lo7p};7b83>7}:<?o19=5246a95g3<uz>=i7>55z?72`<6j<16?5l5fb9>7=`=nj16?5o5fb9>71g=nl1v99m:185820k3?;70:8b;3a1>;4<?0:n95239a95g2<5:2o6<l;;<1;<?7e<2wx8:>50;1x91162<:0199?:0`6?821n3><7p};7083>7}:<>;1=o;4=550>ce<uz><i7>53z?73c<2827?;i4;7:?73`<6j<1v99i:181820n3;i963;808eg>{t<>k1<7<t=55a>06<5==j6<l:;|q72c<72:q68:>5519>03`=9k?0199<:gf8yv20l3:1?v3;7e82f0=:<>o19=524939ba=z{==96=4;{<64=?7e<27?;54>b59>021=9k>0199<:0cf?xu3?<0;6?;t=55;>4d2348?:7:l;<071?2d348?87:l;<077?2d348?>7:l;<075?2d348?<7:l;<00b?2d3488i7:l;<0;a?2d3483h7:l;<0;g?2d3483n7:l;<0;e?2d348357:l;<0;<?2d3483;7:l;<0;2?2d348<o7:l;<04f?2d348<m7:l;<04=?2d348<47:l;<043?2d348<:7:l;<041?2d348<87:l;<03<?2d348;;7:l;<032?2d348;97:l;<030?2d348;?7:l;<036?2d348;=7:l;<034?2d3ty?;94?:35x911028h>70:<f;3a2>;3;l0:n;5242f95g0<5=9h6<l9;<60f?7e>27??l4>b79>06>=9k<019=8:0`5?824>3;i:63;3482f3=:<:>1=o84=510>4d134>8>7?m6:?774<6j?168>>51c48914a28h=70:=d;3a2>;3:j0:n;5243`95g0<5=8j6<l9;<61=?7e>27?>54>b79>071=9k<019<9:0`5?825=3;i:63;2582f3=:<=?1=o84=567>4d134>??7?m6:?707<6j?1689?51c48912728h=70:<9;3a2>;3:l0:n;5243195g0<5=896<l9;<65g?`c34>=m7?l1:p0=6=839p196::0`7?82?<3;i863;8082e`=z{=286=4=cz?7<0<6j<16?>k54b9>76b=<j16?>m54b9>76d=<j16?>o54b9>76?=<j16?>654b9>7a4=<j16?i>54b9>7a7=9k>01>j<:5a896b32=i01>j::5a896b12=i01>j8:5a896b?2=i01>k;:5a896c528h?70=j3;6`?85b=3>h70=j6;6`?85b?3>h70=j8;6`?85b13>h70=ja;6`?85d>3>h70=l5;6`?85d;3>h70=l2;6`?85d<3>h70=l0;6`?85en3;i863<c087g>;4jl0:n9523ga90f=:;oh18n523gc90f=:;o318n523g:90f=:;o=18n523g490f=:;o?18n523g690f=z{=296=4=5z?7<1<6j<16=h:54b9>5`5=<j16=h<54b9>5`7=<j16=h>54b9>5a`=<j16=ik54b9>5ab=<j16=im54b9>67e=<j16>?l54b9>67g=<j16>?754b9>67>=<j16>?954b9>670=<j16>?;54b9>672=<j16><o54b9>64?=<j16><654b9>641=<j16><854b9>643=<j16><:54b9>645=<j16><<54b9>63g=<j16>;754b9>63>=<j16>;954b9>630=<j16>;;54b9>632=<j16>;=54b9>634=<j1v?<<:18687b<3?;70<=c;3a1>;6m?0mh63>e98eg>;6mh0mj6s|1e`94?3|58o?6<l:;<1;3?`c349<=7hk;<16a?`c349957hk;|q2a0<72;q6=h=5519>5`0=9ho0q~?ka;291~;6m:0:n8523949bf=:;>:1jn5234f9bf=:;;21ji5rs0g4>5<5s4;n>7;?;<3f<?7fm2wx=i750;7x94c528h>70=76;df?85083ln70=:d;df?855?3lo7p}>e883>3}:9l;19=521dc95dc<58oh6kj4=0gf>ce<58l;6kk4=0d1>c`<uz;o47>55z?2a4<6j<16?5;5fb9>73`=nj16?8m5fb9>770=nm1v<km:18187b83?;70?jc;3ba>{t9m=1<7;t=0g3>4d2349397hj;<15b?`b349>o7hj;<111?`c3ty:ii4?:3y>5a`==916=hk51`g8yv7c>3:19v3>dg82f0=:;1>1jn5237g9bf=:;<h1jn523369ba=z{8om6=4={<3ga?3734;m<7?ne:p5a3=83?p1<jj:0`6?85?<3ln70=9e;df?852j3ln70==3;dg?xu6n80;6?u21ef915=:9o91=lk4}r3g0?6==r7:hi4>b49>7=5=nj16?;j5fb9>70g=nj16??<5fe9~w4`22909w0?kc;73?87a>3;ji6s|1e194?3|58nh6<l:;<1;7?`b349=h7hj;<16e?`b3499=7hk;|q1<0<72<q6>985519>6=c=9k?01?:7:gf8972f2oi01?:l:gd8yv44l3:1?v3=4782f0=::jk1jn522c59bf=z{;><6=4={<071?37348?47?ne:p66e=839p1?:::0`6?84d13lo70<m6;dg?xu5<00;6?u2256915=::=k1=lk4}r00f?6=;r79894>b49>6f?=no16>o85fg9~w72e290=w0<;3;73?843k3;ji63=4d8e`>;5=90mo63=538ea>;5==0mj6s|22c94?5|5;>86<l:;<0`<?`c348i97hk;|q10a<72;q6>9<5519>61c=9ho0q~<<9;297~;5<;0:n8522b:9bc=::k?1jk5rs36e>5<5s48?=7;?;<064?7fm2wx>>650;1x972628h>70<l7;dg?84e<3lo7p}=5083>7}::=:19=5224095dc<uz88;7>53z?105<6j<16>n95fg9>6g2=no1v?;<:181844n3?;70<:5;3ba>{t::<1<7=t=31e>4d2348h:7hk;<0a7?`c3ty99:4?:3y>66c==916>8651`g8yv44=3:1?v3=3d82f0=::j<1jk522c19bc=z{;=86=4={<0;a?37348<o7?m5:p624=838p1?6k:428971e28h>7p}=8583>1}::1n1=o;4=36;>ce<5;>j6kj4=36`>cc<uz8<=7>52z?1<f<28279;l4>b49~w7>42908w0<7c;3a1>;5<h0mi63=4b8e`>{t:>:1<7<t=3:a>06<5;=26<l:;|q1<7<72;q6>5l51c78972d2oi0q~<9f;296~;50h0><63=7982f0=z{;2:6=4:{<0;e?7e=2798h4ic:?115<al2799?4if:?111<am2wx>;k50;0x97>>2<:01?98:0`6?xu5090;69u229;95g3<5;?;6kk4=371>ce<5;??6kj4}r05`?6=:r79454:0:?133<6j<1v?9i:18084?03;i963=538e`>;5==0mo6s|27a94?4|5;2<68>4=356>4d23ty9;h4?:2y>6=1=9k?01?;::ga8973?2on0q~<9b;296~;50?0><63=7582f0=z{;=o6=4={<0;2?7e=279954ic:p647=838p1?<l:428977f28h>7p}=1183>7}::;h19=5220;95g3<uz89>7>54z?16g<6j<16=h85fb9>5`>=nm16=ho5fd9~w76a2909w0<=a;73?84603;i96s|23394?5|5;8j6<l:;<3f<?`b34;nm7hk;|q14`<72;q6>?75519>641=9k?0q~<=0;296~;5:00:n8521dc9bf=z{;:o6=4={<01<?37348::7?m5:p64`=83?p1?<7:0`6?87bk3lh70?je;dg?87a83lm70?i2;df?xu58j0;6?u2235915=::8?1=o;4}r02a?6=<r79>:4>b49>5`c=nl16=k>5fb9>5c4=nm1v?>m:181845>3?;70<>4;3a1>{t:8n1<7=t=305>4d234;m<7hk;<3e6?`d3ty9<l4?:3y>673==916><=51c78yv46k3:1?v3=2482f0=:9o91jn521g49ba=z{;:26=4={<010?37348:>7?m5:p64d=838p1?<;:0`6?87a>3lh7p}=6083>7}::>i19=5227c95g3<uz8=<7>52z?13g<28279:44>b49~w73a2909w0<8a;73?84103;i96s|24g94?4|5;=268>4=344>4d23ty99i4?:3y>62>==916>;851c78yv42k3:1>v3=76864>;5><0:n85rs37a>5<5s48<:7;?;<050?7e=2wx>8o50;0x97122<:01?8<:0`6?xu5=00;6?u2266915=::?81=o;4}r3eb?6=:r79=l4:0:?14=<6j<1v<hj:18184613?;70<?7;3a1>{t9on1<7<t=33;>06<5;:=6<l:;|q2bf<72;q6><95519>653=9k?0q~?ib;296~;59?0><63=0582f0=z{8lj6=4={<021?37348;?7?m5:p5c?=838p1??;:428976528h>7p}>f983>7}::8919=5221395g3<uz;m;7>52z?157<28279<=4>b49~w66c290>w0<?8;73?856>3;i963>c28eg>;5j>0mh63;6`874>{t:;n1<7<t=324>06<58i86<oj;|q16`<72;q6>=85519>5f2=9ho0q~<=f;296~;58<0><63>c482e`=z{;9;6=4={<030?3734;h:7?ne:p667=838p1?><:42894e028kn7p}=3383>7}::9819=521b:95dc<uz88?7>52z?144<2827:o44>ad9~w7532909w0<?0;73?87di3;ji6s|3g194?2|5;<j68>4=2d`>4d234;hn7hl;<65e?513ty94k4?:3y>63?==916=nl51`g8yv4>83:1>v3=69864>;6kj0:mh5rs3;2>5<5s48=;7;?;<3``?7fm2wx>4<50;0x97012<:01<mj:0cf?xu51:0;6?u2277915=:9jl1=lk4}r0:0?6=:r79:94:0:?2`5<6il1v?7::181841;3?;70?k1;3ba>{t:0<1<7<t=341>06<58n96<oj;|q052<728?p1>>;:55896642==01>>=:55896662==01>>?:55897`a2==01?hk:55897`d2==01?hj:55896712==01>?::55896732==01>?<:55896752==01>?>:55896772==01>>i:558966b2==0198l:gg897?028kn70<lf;dg?xu5l10;6?u2316915=::o;1=lk4}r0ef?6=<r78<94>b49>740==916>no5fe9>6c4=nj1v?j8:181857;3?;70<i0;3ba>{t:ok1<7:t=220>4d2349:97;?;<0`=?`d348n47hl;|q1`3<72;q6?=<5519>6``=9ho0q~<i9;290~;48;0:n852306915=::j31jh522d49bf=z{;n>6=4={<135?37348ni7?ne:p6c>=83>p1>>>:0`6?856;3?;70<l8;d`?84b<3lh7p}=d583>7}:;9:19=522df95dc<uz8m;7>54z?045<6j<16?<<5519>6f>=nl16>h<5fb9~w7b42909w0<if;73?84bk3;ji6s|2g494?2|5;lm6<l:;<125?37348h;7hl;<0f4?`d3ty9h<4?:3y>6cb==916>ho51`g8yv4a<3:18v3=fe82f0=:;9l19=522b49bf=::mi1jn5rs3f3>5<5s48mo7;?;<0f=?7fm2wx>k=50;6x97`d28h>70=?e;73?84d>3ln70<ka;d`?xu5l;0;6?u22gg915=::lh1=lk4}r0e1?6=<r79jh4>b49>746==916>n95fd9>6ac=nj1v?k8:18184a93>270<j7;3ba>{t:o81<7<t=3d2>42e348m>7?ne:p6`3=839p1?h?:5;897c02=301?k::0cf?xu5m10;6>u22g2951d<5;o<6<lm;<0f<?7fm2wx>h=50;1x97ca2=301?k::5;897c428kn7p}=e783>6}::ll1=9l4=3g6>4de348n:7?ne:p6`7=839p1?kj:5;897c42=301?k>:0cf?xu5m=0;6>u22dg951d<5;o86<lm;<0f0?7fm2wx>ih50;1x97cc2=301?k>:5;897ba28kn7p}=e383>6}::ln1=9l4=3g2>4de348n>7?ne:p6ab=839p1?kl:5;897ba2=301?jk:0cf?xu5m90;6>u22da951d<5;nm6<lm;<0f4?7fm2wx>il50;1x97ce2=301?jk:5;897be28kn7p}=dd83>6}::lh1=9l4=3fg>4de348oi7?ne:p6a?=839p1?kn:5;897be2=301?j6:0cf?xu5lj0;6>u22dc951d<5;ni6<lm;<0gg?7fm2wx>io50;1x97c>28>i70<k9;3af>;5lh0:mh5rs22`>5<2s49:97?m5:?2g1<ak27:o>4id:?1f3<ak27?:l4<e:p75d=83?p1>?;:0`6?87d=3lh70?l4;dg?84e>3ln70:9a;1g?xu48h0;68u230195g3<58i=6km4=0a6>cb<5;h>6km4=54b>6e<uz9;57>55z?057<6j<16=n95fb9>5f0=nm16>o;5fd9>03g=;k1v>>7:18685693;i963>c98eg>;6k>0mh63=b58eg>;3>h08m6s|31594?3|5:;;6<l:;<3`=?`d34;h47hk;<0a0?`b34>=m7=6;|q043<72<q6?=h51c7894ef2oi01<m6:gf897d42oi0198n:2:8yv57=3:18v3<0d82f0=:9jk1ji522c19b`=:<?k1?:5rs3c0>5<4s48j=7;?;<0b6?37348j87?ne:p6d7=838p1?o>:0`6?84f<3lh7p}=9e83>7}::0i19=5228g95dc<uz82m7>56z?1=f<6j<16>l>5fd9>6<c=nl16>l:5fd9>6<>=nj16>495fg9~w7?a2909w0<6b;73?84f83;ji6s|28;94?0|5;3i6<l:;<0b4?`d3482i7hk;<0b0?`c348247hk;<0:3?`b3ty8>=4?:3y>766=<016??>51`g8yv5513:1>v3<31820g=:;;31=lk4}r171?6=:r78?=4>ad9>76c==91v>?i:180855n3>270==0;6:?856n3;ji6s|33:94?5|5:8m6<:m;<114?7ej278>54>ad9~w6232909w0==f;3ba>;4;m0><6s|3d294?3|5:8;68<4=2g:>4d2349mn7;?;<16`?`c349947hl;|q05`<72:q6??k5489>74`=<016?<k51`g8yv55?3:1?v3<2d820g=:;8l1=ol4=204>4gb3ty88>4?:3y>77c=9ho01>=l:428yv5cn3:19v3<1g866>;4m10:n8523gc915=:;<n1jk523359bf=z{:;o6=4<{<11`?2>349:i7:6;<12`?7fm2wx??850;1x964c28>i70=>e;3af>;4:?0:mh5rs261>5<5s499h7?ne:?07g<282wx?ik50;7x967b2<801>k8:0`6?85a13?;70=:c;dg?855>3lh7p}<1b83>6}:;;i1845230f90<=:;8i1=lk4}r111?6=;r78>n4>4c9>74b=9kh01><::0cf?xu4<80;6?u233a95dc<5:9j68>4}r1g`?6==r78=i4:2:?0a3<6j<16?k65519>70e=no16??;5fb9~w67e2908w0==b;6:?856k3>270=>b;3ba>{t;;>1<7=t=20a>42e349:o7?mb:?061<6il1v>:?:181855j3;ji63<38864>{t;mi1<7;t=23`>04<5:o>6<l:;<1e3?37349>n7hk;<110?`d3ty8=l4?:2y>77g=<016?<l5489>74g=9ho0q~==3;297~;4:h0:8o5230`95gd<5:886<oj;|q07c<72;q6??o51`g8965?2<:0q~=kb;291~;49k0>>63<e582f0=:;o<19=5234`9bc=:;;91jn5rs23:>5<5s49:m7:6;<12=?7fm2wx?io50;7x967f2<801>k<:0`6?85a=3?;70=:a;dg?855:3lh7p}<2383>7}:;8k1=ol4=201>4gb3ty8=54?:3y>74?=<016?<651`g8yv5c13:19v3<18866>;4m;0:n8523g6915=:;<k1jk523339bf=z{:8:6=4={<12=?7ej278><4>ad9~w6?72909:v3<19866>;4l;0?;63<d1873>;4l80?;63<d2873>;4l=0?;63<d4873>;4l?0?;63<d6873>;4l10?;63<e5873>;4m;0?;63<e2873>;4m<0?;63<e7873>;4m>0?;63<e9873>;4m00?;63<e`873>;4k?0?;63<c4873>;4k:0?;63<c3873>;4k=0?;63<c1873>;4jo0?;63<c0873>;4jl0?;63<fb873>;4nk0?;63<f`873>;4n00?;63<f9873>;4n>0?;63<f7873>;4n<0?;63<f5873>;4180:mh5rs214>5<5s498i7?m5:?00d<al2wx?>850;0x965c28h>70=;8;de?xu4;<0;6?u232a95g3<5:>36kk4}r100?6=:r78?o4>b49>71>=nj1v>=<:181854i3;i963<498e`>{t;:81<7<t=21:>4d2349?m7hl;|q074<72;q6?>651c78962f2ol0q~=;b;297~;4<?0?;63<89873>;40k0:mh5rs264>5<5s49?:7;?;<17=?7fm2wx>ol50;0x97e72=301?li:0cf?xu5k<0;6?u22b295gd<5;ij6<oj;|q1gf<72;q6>n>51`g897ea2oi0q~<ma;296~;5jo0?563=bd82e`=z{;i?6=4={<0ab?7ej279o44>ad9~w7d>2909w0<me;6:?84el3;ji6s|2b194?4|5;hn6<lm;<0`<?7fm2wx>o650;0x97dc2=301?ll:0cf?xu5k;0;6?u22cf95gd<5;i<6<oj;|q1g4<72;q6>om51c`897e128kn7p}=a983>7}::hn184522`a95dc<uz8i>7>52z?1ea<6jk16>o951`g8yv4dj3:1>v3=ae82e`=::jl1jh5rs3c4>5<5s48jo7:6;<0bf?7fm2wx>o?50;0x97gd28hi70<m6;3ba>{t:h<1<7<t=3ca>1?<5;kj6<oj;|q1f5<72;q6>ll51c`897d228kn7p}=a483>7}::hk184522`;95dc<uz8jj7>52z?1ed<6jk16>o:51`g8yv4fm3:1>v3=a882fg=::k91=lk4}r1a3?6=<r78h?4:0:?0g5<6j<16?5:5fg9>7d6=nj1v>m6:18085c:3;i963<e5864>;4>l0mj6s|3c794?2|5:n;68>4=2`f>4d23493?7hi;<1:g?`d3ty8o:4?:2y>7a6=9k?01>k=:428960c2ol0q~=m6;290~;4l80><63<bg82f0=:;191ji5238g9bf=z{:i36=4<{<1g5?7e=278i>4:0:?02a<al2wx?o650;6x96b42<:01>m>:0`6?85?<3lo70=n2;d`?xu4kh0;6>u23e195g3<5:o>68>4=24f>cb<uz9i57>54z?0`1<28278o?4>b49>7=3=no16?l:5fb9~w6ee2908w0=k4;3a1>;4m?0><63<6g8eb>{t;kk1<7:t=2f6>06<5:i86<l:;<1;1?`c349j:7hl;|q0gf<72:q6?i;51c7896c02<:01>8i:gf8yv5ej3:18v3<d7864>;4k=0:n8523949bc=:;h21jn5rs2ag>5<4s49o:7?m5:?0a=<28278;=4if:p7ge=83>p1>j8:42896e228h>70=76;dg?85fi3lh7p}<cd83>6}:;m=1=o;4=2g:>06<5:=;6kj4}r1a`?6=<r78h54:0:?0g3<6j<16?595fb9>7g2=nj1v>mi:18085c03;i963<e`864>;4?80mo6s|3d394?2|5:oj6<l:;<1eg?37349>i7hl;<11=?`d3ty85l4?:3y>7f0==916?o=51`g8yv5>13:1>v3<c4864>;4j;0:mh5rs2;4>5<5s49h?7;?;<1a4?7fm2wx?4850;0x96e52<:01>oi:0cf?xu4110;6?u23b6915=:;k;1=lk4}r1:0?6=:r78o=4:0:?0ea<6il1v>7<:18185en3?;70=nc;3ba>{t;0?1<7<t=2a2>06<5:kn6<oj;|q0=7<72;q6?ok5519>7dd=9ho0q~=n9;296~;4j:0?563<a882e`=z{:h?6=4={<1a7?73j278n94>ad9~w6g02908w0=m2;6:?85f13>270=n7;3ba>{t;hk1<7=t=2`1>42e349j57?mb:?0ed<6il1v>o::18085e93>270=n7;6:?85f=3;ji6s|3`:94?5|5:h:6<:m;<1b3?7ej278m54>ad9~w6g42908w0=m0;6:?85f=3>270=n3;3ba>{t;h<1<7=t=2`3>42e349j97?mb:?0e3<6il1v>o>:18085fn3>270=n3;6:?85f93;ji6s|3`694?5|5:km6<:m;<1b7?7ej278m94>ad9~w6?a2908w0=ne;6:?85f93>270=6f;3ba>{t;h81<7=t=2cf>42e349j=7?mb:?0e7<6il1v>7k:18085fl3>270=6f;6:?85>l3;ji6s|3`294?5|5:ko6<:m;<1:b?7ej278m=4>ad9~w6?e2908w0=nc;6:?85>l3>270=6b;3ba>{t;0o1<7=t=2c`>42e3492h7?mb:?0=`<6il1v>7l:18085fj3;?n63<9c82fg=:;0i1=lk4}r1e6?6=<r78jo4>b49>5fe=nj16=nl5fe9>03g=;=1v>h>:18785ai3;i963>ce8eg>;6kj0mh63;6`807>{t;o:1<7:t=2d:>4d234;hi7hl;<3``?`c34>=m7==;|q0ac<72=q6?k651c7894ea2oi01<mj:gf8910f2:;0q~=je;290~;4n>0:n8521e29bf=:9jl1ji5247c975=z{:oo6=4;{<1e2?7e=27:h<4ic:?2`5<al27?:l4=f:p7`e=83>p1>h::0`6?87c:3lh70?k1;dg?821i38n7p}<ec83>6}:;o>1=o;4=0f1>cb<5=<j6?j4}r161?6=:r789=4>bc9>70g=9ho0q~=;c;296~;4=90:mh5234390<=z{:?=6=4={<165?7ej2789o4>ad9~w62c2909w0=:1;3ba>;4=;0?56s|34594?4|5:?96<lm;<16g?7fm2wx?9k50;0x963528kn70=:3;6:?xu4=10;6?u234195gd<5:?o6<oj;|q00c<72;q6?8=51`g896332=30q~=:9;296~;4==0:no5234g95dc<uz9<>7>52z?011<6il16?5h5fg9~w60?2909w0=93;3af>;4>m0:mh5rs27e>5<5s49=?7?ne:?021<312wx?;750;0x960328hi70=9e;3ba>{t;?:1<7<t=247>4gb349=97:6;|q02d<72;q6?;;51c`8960a28kn7p}<6083>7}:;??1=lk4=245>1?<uz9=n7>52z?023<6jk16?:>51`g8yv51:3:1>v3<6782e`=:;?=1845rs24`>5<5s49=;7?mb:?034<6il1v>9<:180851?3;ji63<8g8e`>;40h0mj6s|36g94?4|5:=26<lm;<1;7?7fm2wx?:;50;0x961>28kn70=8a;6:?xu4?o0;6?u236c95gd<5:2?6<oj;|q033<72;q6?:o51`g8961e2=30q~=70;296~;4?k0:no5239795dc<uz9<;7>52z?03g<6il16?:m5489~w6>62909w0=8c;3af>;40?0:mh5rs25;>5<5s49<o7?ne:?03a<312wx?5<50;0x961c28hi70=77;3ba>{t;>>1<7<t=25g>4gb3493m7hk;|q0<`<72:q6?5m5519>7=b==916?5h51`g8yv5?k3:18v3<8b82f0=:;1h1ji523829ba=:;0;1ji5rs2::>5<5s49347;?;<1;e?7fm2wx8;j50;06824n3><70:<e;64?824l3><70:<c;64?824j3><70:<a;64?82403><70:<7;64?824>3><70:<5;64?824<3><70:<3;64?824:3><70:<1;64?82483><70:=f;64?825l3><70:=c;64?825j3><70:=a;64?82513><70:=8;64?825?3><70:=6;64?825=3><70:=4;64?823=3><70:;4;64?823;3><70:;2;64?82393><70:;0;64?82413><70:=e;64?825;3><70:=2;64?84>03;ji6s|47094?4|5=9m68>4=54b>`e<uz>==7>52z?77`<2827?:l4ka:p036=838p19=k:428910f2m20q~::f;296~;3;j0><63;6`8g2>{t<<o1<7<t=51a>06<5=<j6i;4}r66`?6=:r7??l4:0:?72d<c<2wx88l50;0x915?2<:0198n:e18yv22i3:1>v3;36864>;3>h0o>6s|44;94?4|5=9=68>4=54b>a7<uz>>47>52z?770<2827?:l4ja:p001=838p19=;:428910f2m:0q~::6;296~;3;:0><63;6`8`b>{t<<?1<7<t=511>06<5=<j6nk4}r660?6=:r7??<4:0:?72d<dl2wx88=50;0x91572<:0198n:b`8yv22:3:1>v3;2g864>;3>h0hm6s|44294?4|5=8o68>4=54b>f?<uz>?j7>52z?76f<2827?:l4l8:p01c=838p19<m:428910f2l30q~:;d;296~;3:h0><63;6`8`3>{t<=i1<7<t=50:>06<5=<j6n84}r67f?6=:r7?>54:0:?72d<d=2wx89o50;0x91402<:0198n:b68yv2313:1>v3;27864>;3>h0h?6s|45:94?4|5=8>68>4=54b>f4<uz>?;7>52z?761<2827?:l4j1:p03?=838p19:::428910f2l:0q~:98;296~;3<=0><63;6`8f<>{t<?=1<7<t=560>06<5=<j6ih4}r652?6=:r7?8?4:0:?72d<cm2wx8;;50;0x91262<:0198n:ef8yv21<3:1>v3;41864>;3>h0oo6s|47194?4|5=9268>4=54b>ad<uz>>o7>52z?76`<2827?:l4k7:p007=838p19<<:428910f2ji0q~:;6;296~;3:;0><63;6`8`5>{t;=21<7<t=26;>4gb349?57hk;|q00d<72;q6?975fb9>71g=9=i0q~:9b;296~;3>j0:mh5247c9a`=z{:lo6=4:{<1;b?`b3493m7hj;<1:4?7fm27?:l4;8`9>03g=mm1v<;6:181842=3lo70<:4;37g>{t9<l1<7<t=0d0>cb<58l96<:l;|q113<72;q6>865fd9>602=9ho0q~?i4;296~;6n?0mi63>f382e`=zuz?297>52z\6=0=:<=0>585+49495d?<uz?2h7>52z\6=a=:<=0>5i5+49495dg<uz?3;7>52z\6<2=:<=0>4:5+49495dd<uz>nn7>52z\7g2=:<=0?o:5+494950`<uz>n57>52z\7g3=:<=0?o;5+494953g<uz>n47>52z\7g0=:<=0?o85+4949523<uz>n;7>52z\7g1=:<=0?o95+49495=6<uz>n:7>52z\7g6=:<=0?o>5+49495=0<uz>n97>52z\7g7=:<=0?o?5+49495=1<uz>n?7>52z\7g5=:<=0?o=5+49495=><uz>n>7>52z\7fc=:<=0?nk5+49495=g<uz>n=7>52z\7f`=:<=0?nh5+49495=d<uz>n<7>52z\7fa=:<=0?ni5+49495=e<uz>oj7>52z\7ff=:<=0?nn5+49495=b<uz>oi7>52z\7fg=:<=0?no5+49495=c<uz>oh7>52z\7fd=:<=0?nl5+49495=`<uz>oo7>52z\7f<=:<=0?n45+49495<6<uz>on7>52z\7f==:<=0?n55+49495<7<uz>om7>52z\7f2=:<=0?n:5+49495<4<uz>o47>52z\7f0=:<=0?n85+49495<5<uz>o;7>52z\7f1=:<=0?n95+49495<2<uz>o:7>52z\7f6=:<=0?n>5+49495<3<uz>o97>52z\7f7=:<=0?n?5+49495<0<uz>o87>52z\7f4=:<=0?n<5+49495<1<uz>o?7>52z\7f5=:<=0?n=5+49495<><uz>o>7>52z\7ec=:<=0?mk5+49495<?<uz>o=7>52z\7e`=:<=0?mh5+49495<g<uz>o<7>52z\7ea=:<=0?mi5+49495<d<uz>hj7>52z\7ef=:<=0?mn5+49495<e<uz>m>7>52z\7ga=:<=0?oi5+49495<b<uz>m=7>52z\7gf=:<=0?on5+49495<c<uz>m<7>52z\7gg=:<=0?oo5+49495<`<uz>nj7>52z\7gd=:<=0?ol5+49495d6<uz>ni7>52z\7g<=:<=0?o45+49495d7<uz>nh7>52z\7g==:<=0?o55+49495d4<uz>no7>52z\7g4=:<=0?o<5+49495d5<uz>n87>52z\7f3=:<=0?n;5+49495d2<uz>o57>52z\7eg=:<=0?mo5+49495d3<uz>hi7>52z\7ed=:<=0?ml5+49495d0<uz?j47>52z\6e==:<=0>m55+49495d1<uz?2?7>52z\6=6=:<=0>5>5+49495d><uz?887>52z\655=:<=0>==5+494950d<uz?8>7>52z\64c=:<=0><k5+494950e<uz?8=7>52z\64`=:<=0><h5+494950b<uz?8<7>52z\64a=:<=0><i5+494950c<uz?9j7>52z\64f=:<=0><n5+4949536<uz?9i7>52z\64g=:<=0><o5+4949537<uz?9o7>52z\64<=:<=0><45+4949534<uz?9n7>52z\64==:<=0><55+4949535<uz?9m7>52z\642=:<=0><:5+4949532<uz?957>52z\643=:<=0><;5+4949533<uz?947>52z\640=:<=0><85+4949530<uz?9;7>52z\641=:<=0><95+4949531<uz?9:7>52z\646=:<=0><>5+494953><uz?997>52z\647=:<=0><?5+494953?<uz?987>52z\644=:<=0><<5+494953d<uz?9?7>52z\645=:<=0><=5+494953e<uz?9=7>52z\7b`=:<=0?jh5+494953b<uz?9<7>52z\7ba=:<=0?ji5+494953c<uz?:j7>52z\7bf=:<=0?jn5+494953`<uz?:i7>52z\7bg=:<=0?jo5+4949526<uz?:h7>52z\7bd=:<=0?jl5+4949527<uz?:o7>52z\7b<=:<=0?j45+4949524<uz?:n7>52z\7b==:<=0?j55+4949525<uz?:m7>52z\7b2=:<=0?j:5+4949522<uz?:57>52z\7b3=:<=0?j;5+4949520<uz?:47>52z\7b0=:<=0?j85+4949521<uz?8n7>52z\653=:<=0>=;5+494952><uz?8m7>52z\650=:<=0>=85+494952?<uz?857>52z\651=:<=0>=95+494952g<uz?847>52z\656=:<=0>=>5+494952d<uz?8;7>52z\657=:<=0>=?5+494952e<uz?8:7>52z\654=:<=0>=<5+494952b<uz?897>52z\64d=:<=0><l5+494952c<uz?9h7>52z\7bc=:<=0?jk5+494952`<uz?9>7>52z\7b1=:<=0?j95+49495=7<uz?:;7>52z\7b6=:<=0?j>5+49495=4<uz???7>52z\606=:<=0>8>5+49495=5<uz>2n7>52z\7=g=:<=0?5o5+49495=2<uz?8h7>52z\67a=:<=0>?i5+49495=3<uz?=47>52z\62==:<=0>:55+49495=?<utdjhn4?:3yK0=1<ugkoh7>52zJ7<2=zfhnn6=4={I6;3>{iiml1<7<tH5:4?xhfm90;6?uG4958ykgb93:1>vF;869~jdc52909wE:77:me`5=838pD968;|lba1<72;qC8594}ocf1?6=:rB?4:5rn`g5>5<5sA>3;6saad594?4|@=2<7p`ne983>7}O<1=0qcoj9;296~N30>1vblkn:181M2??2wemhl50;0xL1>03tdjin4?:3yK0=1<ugknh7>52zJ7<2=zfhon6=4={I6;3>{iill1<7<tH5:4?xhfn90;6?uG4958ykga93:1>vF;869~jd`52909wE:77:mec5=838pD968;|lbb1<72;qC8594}oce1?6=:rB?4:5rn`d5>5<5sA>3;6saag594?4|@=2<7p`nf983>7}O<1=0qcoi9;296~N30>1vblhn:181M2??2wemkl50;0xL1>03tdjjn4?:3yK0=1<ugkmh7>52zJ7<2=zfhln6=4={I6;3>{iiol1<7<tH5:4?xhe890;6?uG4958ykd793:1>vF;869~jg652909wE:77:mf55=838pD968;|la41<72;qC8594}o`31?6=:rB?4:5rnc25>5<5sA>3;6sab1594?4|@=2<7p`m0983>7}O<1=0qcl?9;296~N30>1vbo>n:181M2??2wen=l50;0xL1>03tdi<n4?:3yK0=1<ugh;h7>52zJ7<2=zfk:n6=4={I6;3>{ij9l1<7<tH5:4?xhe990;6?uG4958ykd693:1>vF;869~jg752909wE:77:mf45=838pD968;|la51<72;qC8594}o`21?6=:rB?4:5rnc35>5<5sA>3;6sab0594?4|@=2<7p`m1983>7}O<1=0qcl>9;296~N30>1vbo?n:181M2??2wen<l50;0xL1>03tdi=n4?:3yK0=1<ugh:h7>52zJ7<2=zfk;n6=4={I6;3>{ij8l1<7<tH5:4?xhe:90;6?uG4958ykd593:1>vF;869~jg452909wE:77:mf75=838pD968;|la61<72;qC8594}o`11?6=:rB?4:5rnc05>5<5sA>3;6sab3594?4|@=2<7p`m2983>7}O<1=0qcl=9;296~N30>1vbo<n:181M2??2wen?l50;0xL1>03tdi>n4?:3yK0=1<ug3:57>51zJ7<2=zf0<j6=4>{I6;3>{i1?h1<7?tH5:4?xh>>j0;6<uG4958yk?1l3:1=vF;869~j<0b290:wE:77:m=3`=83;pD968;|l:35<728qC8594}o;45?6=9rB?4:5rn851>5<6sA>3;6sa96194?7|@=2<7p`67583>4}O<1=0qc785;295~N30>1vb499:182M2??2we5:950;3xL1>03td2;54?:0yK0=1<ug3<57>51zJ7<2=zf0=j6=4>{I6;3>{i1>h1<7?tH5:4?xh>?j0;6<uG4958yk?0l3:1=vF;869~j<1b290:wE:77:m=2`=83;pD968;|l:<5<728qC8594}o;;5?6=9rB?4:5rn8:1>5<6sA>3;6sa99194?7|@=2<7p`68583>4}O<1=0qc775;295~N30>1vb469:182M2??2we55950;3xL1>03td2454?:0yK0=1<ug3357>51zJ7<2=zf02j6=4>{I6;3>{i11h1<7?tH5:4?xh>0j0;6<uG4958yk??l3:1=vF;869~j<>b290:wE:77:m==`=83;pD968;|l:=5<728qC8594}o;:5?6=9rB?4:5rn8;1>5<6sA>3;6sa98194?7|@=2<7p`69583>4}O<1=0qc765;295~N30>1vb479:182M2??2we54950;3xL1>03td2554?:0yK0=1<ug3257>51zJ7<2=zf03j6=4>{I6;3>{i10h1<7?tH5:4?xh>1j0;6<uG4958yk?>l3:1=vF;869~j<?b290:wE:77:m=<`=83;pD968;|l:e5<728qC8594}o;b5?6=9rB?4:5rn8c1>5<6sA>3;6sa9`194?7|@=2<7p`6a583>4}O<1=0qc7n5;295~N30>1vb4o9:182M2??2we5l950;3xL1>03td2m54?:0yK0=1<ug3j57>51zJ7<2=zf0kj6=4>{I6;3>{i1hh1<7?tH5:4?xh>ij0;6<uG4958yk?fl3:1=vF;869~j<gb290:wE:77:m=d`=83;pD968;|l:f5<728qC8594}o;a5?6=9rB?4:5rn8`1>5<6sA>3;6sa9c194?7|@=2<7p`6b583>4}O<1=0qc7m5;295~N30>1vb4l9:182M2??2we5o950;3xL1>03td2n54?:0yK0=1<ug3i57>51zJ7<2=zf0hj6=4>{I6;3>{i1kh1<7?tH5:4?xh>jj0;6<uG4958yk?el3:1=vF;869~j<db290:wE:77:m=g`=83;pD968;|l:g5<728qC8594}o;`5?6=9rB?4:5rn8a1>5<6sA>3;6sa9b194?7|@=2<7p`6c583>4}O<1=0qc7l5;295~N30>1vb4m9:182M2??2we5n950;3xL1>03td2o54?:0yK0=1<ug3h57>51zJ7<2=zf0ij6=4>{I6;3>{i1jh1<7?tH5:4?xh>kj0;6<uG4958yk?dl3:1=vF;869~j<eb290:wE:77:m=f`=83;pD968;|l:`5<728qC8594}o;g5?6=9rB?4:5rn8f1>5<6sA>3;6sa9e194?7|@=2<7p`6d583>4}O<1=0qc7k5;295~N30>1vb4j9:182M2??2we5i950;3xL1>03td2h54?:0yK0=1<ug3o57>51zJ7<2=zf0nj6=4>{I6;3>{i1mh1<7?tH5:4?xh>lj0;6<uG4958yk?cl3:1=vF;869~j<bb290:wE:77:m=a`=83;pD968;|l:a5<728qC8594}o;f5?6=9rB?4:5rn8g1>5<6sA>3;6sa9d194?7|@=2<7p`6e583>4}O<1=0qc7j5;295~N30>1vb4k9:182M2??2we5h950;3xL1>03td2i54?:0yK0=1<ug3n57>51zJ7<2=zf0oj6=4>{I6;3>{i1lh1<7?tH5:4?xh>mj0;6<uG4958yk?bl3:1=vF;869~j<cb290:wE:77:m=``=83;pD968;|l:b5<728qC8594}o;e5?6=9rB?4:5rn8d1>5<6sA>3;6sa9g194?7|@=2<7p`6f583>4}O<1=0qc7i5;295~N30>1vb4h9:182M2??2we5k950;3xL1>03td2j54?:0yK0=1<ug3m57>51zJ7<2=zf0lj6=4>{I6;3>{i1oh1<7?tH5:4?xh>nj0;6<uG4958yk?al3:1=vF;869~j<`b290:wE:77:m=c`=83;pD968;|lb45<728qC8594}oc35?6=9rB?4:5rn`21>5<6sA>3;6saa1194?7|@=2<7p`n0583>4}O<1=0qco?5;295~N30>1vbl>9:182M2??2wem=950;3xL1>03tdj<54?:0yK0=1<ugk;57>51zJ7<2=zfh:j6=4>{I6;3>{ii9h1<7?tH5:4?xhf8j0;6<uG4958ykg7l3:1=vF;869~jd6b290:wE:77:me5`=83;pD968;|lb55<728qC8594}oc25?6=9rB?4:5rn`31>5<6sA>3;6saa0194?7|@=2<7p`n1583>4}O<1=0qco>5;295~N30>1vbl?9:182M2??2wem<950;3xL1>03tdj=54?:0yK0=1<ugk:57>51zJ7<2=zfh;j6=4>{I6;3>{ii8h1<7?tH5:4?xhf9j0;6<uG4958ykg6l3:1=vF;869~jd7b290:wE:77:me4`=83;pD968;|lb65<728qC8594}oc15?6=9rB?4:5rn`01>5<6sA>3;6saa3194?7|@=2<7p`n2583>4}O<1=0qco=5;295~N30>1vbl<9:182M2??2wem?950;3xL1>03tdj>54?:0yK0=1<ugk957>51zJ7<2=zfh8j6=4>{I6;3>{ii;h1<7?tH5:4?xhf:j0;6<uG4958ykg5l3:1=vF;869~jd4b290:wE:77:me7`=83;pD968;|lb75<728qC8594}oc05?6=9rB?4:5rn`11>5<6sA>3;6saa2194?7|@=2<7p`n3583>4}O<1=0qco<5;295~N30>1vbl=9:182M2??2wem>950;3xL1>03tdj?54?:0yK0=1<ugk857>51zJ7<2=zfh9j6=4>{I6;3>{ii:h1<7?tH5:4?xhf;j0;6<uG4958ykg4l3:1=vF;869~jd5b290:wE:77:me6`=83;pD968;|lb05<728qC8594}oc75?6=9rB?4:5rn`61>5<6sA>3;6saa5194?7|@=2<7p`n4583>4}O<1=0qco;5;295~N30>1vbl:9:182M2??2wem9950;3xL1>03tdj854?:0yK0=1<ugk?57>51zJ7<2=zfh>j6=4>{I6;3>{ii=h1<7?tH5:4?xhf<j0;6<uG4958ykg3l3:1=vF;869~jd2b290:wE:77:me1`=83;pD968;|lb15<728qC8594}oc65?6=9rB?4:5rn`71>5<6sA>3;6saa4194?7|@=2<7p`n5583>4}O<1=0qco:5;295~N30>1vbl;9:182M2??2wem8950;3xL1>03tdj954?:0yK0=1<ugk>57>51zJ7<2=zfh?j6=4>{I6;3>{ii<h1<7?tH5:4?xhf=j0;6<uG4958ykg2l3:1=vF;869~jd3b290:wE:77:me0`=83;pD968;|lb25<728qC8594}oc55?6=9rB?4:5rn`41>5<6sA>3;6saa7194?7|@=2<7p`n6583>4}O<1=0qco95;295~N30>1vbl89:182M2??2wem;950;3xL1>03tdj:54?:0yK0=1<ugk=57>51zJ7<2=zfh<j6=4>{I6;3>{ii?h1<7?tH5:4?xhf>j0;6<uG4958ykg1l3:1=vF;869~jd0b290:wE:77:me3`=83;pD968;|lb35<728qC8594}oc45?6=9rB?4:5rn`51>5<6sA>3;6saa6194?7|@=2<7p`n7583>4}O<1=0qco85;295~N30>1vbl99:182M2??2wem:950;3xL1>03tdj;54?:0yK0=1<ugk<57>51zJ7<2=zfh=j6=4>{I6;3>{ii>h1<7?tH5:4?xhf?j0;6<uG4958ykg0l3:1=vF;869~jd1b290:wE:77:me2`=83;pD968;|lb<5<728qC8594}oc;5?6=9rB?4:5rn`:1>5<6sA>3;6saa9194?7|@=2<7p`n8583>4}O<1=0qco75;295~N30>1vbl69:182M2??2wem5950;3xL1>03tdj454?:0yK0=1<ugk357>51zJ7<2=zfh2j6=4>{I6;3>{ii1h1<7?tH5:4?xhf0j0;6<uG4958ykg?l3:1=vF;869~jd>b290:wE:77:me=`=83;pD968;|lb=5<728qC8594}oc:5?6=9rB?4:5rn`;1>5<6sA>3;6saa8194?7|@=2<7p`n9583>4}O<1=0qco65;295~N30>1vbl79:182M2??2wem4950;3xL1>03tdj554?:0yK0=1<ugk257>51zJ7<2=zfh3j6=4>{I6;3>{ii0h1<7?tH5:4?xhf1j0;6<uG4958ykg>l3:1=vF;869~jd?b290:wE:77:me<`=83;pD968;|lbe5<728qC8594}ocb5?6=9rB?4:5rn`c1>5<6sA>3;6saa`194?7|@=2<7p`na583>4}O<1=0qcon5;295~N30>1vblo9:182M2??2weml950;3xL1>03tdjm54?:0yK0=1<ugkj57>51zJ7<2=zfhkj6=4>{I6;3>{iihh1<7?tH5:4?xhfij0;6<uG4958ykgfl3:1=vF;869~jdgb290:wE:77:med`=83;pD968;|lbf5<728qC8594}oca5?6=9rB?4:5rn``1>5<6sA>3;6saac194?7|@=2<7p`nb583>4}O<1=0qcom5;295~N30>1vbll9:182M2??2wemo950;3xL1>03tdjn54?:0yK0=1<ugki57>51zJ7<2=zfhhj6=4>{I6;3>{iikh1<7?tH5:4?xhfjj0;6<uG4958ykgel3:1=vF;869~jddb290:wE:77:meg`=83;pD968;|lbg5<728qC8594}oc`5?6=9rB?4:5rn`a1>5<6sA>3;6saab194?7|@=2<7p`nc583>4}O<1=0qcol5;295~N30>1vblm9:182M2??2wemn950;3xL1>03tdjo54?:0yK0=1<ugkh57>51zJ7<2=zfhij6=4>{I6;3>{iijh1<7?tH5:4?xhfkj0;6<uG4958ykgdl3:1=vF;869~jdeb290:wE:77:mef`=83;pD968;|lb`5<728qC8594}ocg5?6=9rB?4:5rn`f1>5<6sA>3;6saae194?7|@=2<7p`nd583>4}O<1=0qcok5;295~N30>1vblj9:182M2??2wemi950;3xL1>03tdjh54?:0yK0=1<ugko57>51zJ7<2=zfhnj6=4>{I6;3>{iimh1<7?tH5:4?x{zuIJHwnh>:85;ac640tJKNv>r@ARxyEF
\ No newline at end of file diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v new file mode 100644 index 000000000..6ec1e3f88 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v @@ -0,0 +1,173 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_prog_full.v when simulating +// the core, fifo_xlnx_512x36_2clk_prog_full. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_512x36_2clk_prog_full( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + almost_full, + empty, + prog_full); + + +input rst; +input wr_clk; +input rd_clk; +input [35 : 0] din; +input wr_en; +input rd_en; +output [35 : 0] dout; +output full; +output almost_full; +output empty; +output prog_full; + +// synthesis translate_off + + FIFO_GENERATOR_V6_1 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(9), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(1), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(0), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(500), + .C_PROG_FULL_THRESH_NEGATE_VAL(499), + .C_PROG_FULL_TYPE(1), + .C_RD_DATA_COUNT_WIDTH(9), + .C_RD_DEPTH(512), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(9), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(9), + .C_WR_DEPTH(512), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .ALMOST_FULL(almost_full), + .EMPTY(empty), + .PROG_FULL(prog_full), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .RD_DATA_COUNT(), + .WR_DATA_COUNT(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo new file mode 100644 index 000000000..64e6769d6 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_512x36_2clk_prog_full YourInstanceName ( + .rst(rst), + .wr_clk(wr_clk), + .rd_clk(rd_clk), + .din(din), // Bus [35 : 0] + .wr_en(wr_en), + .rd_en(rd_en), + .dout(dout), // Bus [35 : 0] + .full(full), + .almost_full(almost_full), + .empty(empty), + .prog_full(prog_full)); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_512x36_2clk_prog_full.v when simulating +// the core, fifo_xlnx_512x36_2clk_prog_full. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco new file mode 100644 index 000000000..f99c3c6fb --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco @@ -0,0 +1,84 @@ +############################################################## +# +# Xilinx Core Generator version 12.2 +# Date: Thu Nov 11 17:27:10 2010 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=true +CSET component_name=fifo_xlnx_512x36_2clk_prog_full +CSET data_count=false +CSET data_count_width=9 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=500 +CSET full_threshold_negate_value=499 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=36 +CSET input_depth=512 +CSET output_data_width=36 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=9 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=9 +# END Parameters +GENERATE +# CRC: 6b9f6232 diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise new file mode 100644 index 000000000..91dbf5819 --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise @@ -0,0 +1,72 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation"/> + <association xil_pn:name="Implementation"/> + </file> + <file xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation"/> + <association xil_pn:name="Implementation"/> + <association xil_pn:name="PostMapSimulation"/> + <association xil_pn:name="PostRouteSimulation"/> + <association xil_pn:name="PostTranslateSimulation"/> + </file> + </files> + + <properties> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_512x36_2clk_prog_full" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_512x36_2clk_prog_full.ngc" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_512x36_2clk_prog_full" xil_pn:valueState="non-default"/> + <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_512x36_2clk_prog_full" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-11-11T09:27:12" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="96435AE73456681FC0EF5839C85C4C97" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt new file mode 100644 index 000000000..2eb837a3f --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt @@ -0,0 +1,12 @@ +# Output products list for <fifo_xlnx_512x36_2clk_prog_full> +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_512x36_2clk_prog_full.gise +fifo_xlnx_512x36_2clk_prog_full.ngc +fifo_xlnx_512x36_2clk_prog_full.v +fifo_xlnx_512x36_2clk_prog_full.veo +fifo_xlnx_512x36_2clk_prog_full.xco +fifo_xlnx_512x36_2clk_prog_full.xise +fifo_xlnx_512x36_2clk_prog_full_flist.txt +fifo_xlnx_512x36_2clk_prog_full_readme.txt +fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt new file mode 100644 index 000000000..33d50a91d --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt @@ -0,0 +1,47 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk_prog_full' in directory +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_prog_full.gise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_512x36_2clk_prog_full.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk_prog_full.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk_prog_full.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk_prog_full.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_prog_full.xise: + ISE Project Navigator support file. This is a generated file and should + not be edited directly. + +fifo_xlnx_512x36_2clk_prog_full_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + +fifo_xlnx_512x36_2clk_prog_full_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl new file mode 100644 index 000000000..e1aecccff --- /dev/null +++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl @@ -0,0 +1,68 @@ +# The package naming convention is <core_name>_xmdf +package provide fifo_xlnx_512x36_2clk_prog_full_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::fifo_xlnx_512x36_2clk_prog_full_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_prog_full +} +# ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_prog_full +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp2/extramfifo/ext_fifo.v b/fpga/usrp2/extramfifo/ext_fifo.v index 6888617a7..80f82fc63 100644 --- a/fpga/usrp2/extramfifo/ext_fifo.v +++ b/fpga/usrp2/extramfifo/ext_fifo.v @@ -45,9 +45,7 @@ module ext_fifo wire [EXT_WIDTH-1:0] write_data; wire [EXT_WIDTH-1:0] read_data; wire full1, empty1; - wire almost_full2, full2, empty2; - wire [INT_WIDTH-1:0] data_to_fifo; - wire [INT_WIDTH-1:0] data_from_fifo; + wire almost_full2, almost_full2_spread, full2, empty2; wire [FIFO_DEPTH-1:0] capacity; wire space_avail; wire data_avail; @@ -134,17 +132,17 @@ module ext_fifo .empty(empty1)); // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP. - fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i2 ( - .rst(rst), - .wr_clk(ext_clk), - .rd_clk(int_clk), - .din(read_data), // Bus [35 : 0] - .wr_en(write_output_fifo), - .rd_en(dst_rdy_i), - .dout(dataout), // Bus [35 : 0] - .full(full2), - .empty(empty2), - .prog_full(almost_full2)); + fifo_xlnx_512x36_2clk_prog_full fifo_xlnx_32x36_2clk_prog_full_i1 ( + .rst(rst), + .wr_clk(ext_clk), + .rd_clk(int_clk), + .din(read_data), // Bus [35 : 0] + .wr_en(write_output_fifo), + .rd_en(dst_rdy_i), + .dout(dataout), // Bus [35 : 0] + .full(full2), + .empty(empty2), + .prog_full(almost_full2)); end endgenerate @@ -158,13 +156,14 @@ module ext_fifo .full_out(almost_full2_spread) ); - - always @ (posedge int_clk) - debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i }; +// always @ (posedge int_clk) +// debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i }; always @ (posedge ext_clk) - debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 }; - + // debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 }; + debug[31:0] <= {7'h0,src_rdy_i,read_input_fifo,write_output_fifo,dst_rdy_i,full2,almost_full2,empty2,full1,empty1,write_data[7:0],read_data[7:0]}; + + always@ (posedge ext_clk) // debug2[31:0] <= {write_data[15:0],read_data[15:0]}; debug2[31:0] <= 0; diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.sh b/fpga/usrp2/extramfifo/ext_fifo_tb.sh index dcfede37a..dcfede37a 100644..100755 --- a/fpga/usrp2/extramfifo/ext_fifo_tb.sh +++ b/fpga/usrp2/extramfifo/ext_fifo_tb.sh diff --git a/fpga/usrp2/extramfifo/nobl_fifo.v b/fpga/usrp2/extramfifo/nobl_fifo.v index 4c009d980..0b63768fc 100644 --- a/fpga/usrp2/extramfifo/nobl_fifo.v +++ b/fpga/usrp2/extramfifo/nobl_fifo.v @@ -70,26 +70,27 @@ module nobl_fifo // Simple NoBL SRAM interface, 4 cycle read latency. // Read/Write arbitration via temprary application of empty/full flags. // - nobl_if nobl_if_i1 - ( - .clk(clk), - .rst(rst), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .address(address), - .data_out(write_data), - .data_in(read_data), - .data_in_valid(data_avail), - .write(write), - .enable(enable) - ); + nobl_if #(.WIDTH(WIDTH),.DEPTH(RAM_DEPTH)) + nobl_if_i1 + ( + .clk(clk), + .rst(rst), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .address(address), + .data_out(write_data), + .data_in(read_data), + .data_in_valid(data_avail), + .write(write), + .enable(enable) + ); diff --git a/fpga/usrp2/extramfifo/nobl_if.v b/fpga/usrp2/extramfifo/nobl_if.v index adf9f165b..b5ebe9c6b 100644 --- a/fpga/usrp2/extramfifo/nobl_if.v +++ b/fpga/usrp2/extramfifo/nobl_if.v @@ -56,18 +56,21 @@ module nobl_if address_pipe1 <= 0; write_pipe1 <= 0; data_out_pipe1 <= 0; + RAM_WEn <= 1; + RAM_CE1n <= 1; + end else begin enable_pipe1 <= enable; - RAM_CE1n <= ~enable; // Creates IOB flob - + RAM_CE1n <= ~enable; // Creates IOB flop + RAM_WEn <= ~write; // Creates IOB flop if (enable) begin address_pipe1 <= address_gray; write_pipe1 <= write; - RAM_WEn <= ~write; // Creates IOB flob +// RAM_WEn <= ~write; // Creates IOB flop if (write) diff --git a/fpga/usrp2/fifo/.gitignore b/fpga/usrp2/fifo/.gitignore index cba7efc8e..866f1faad 100644 --- a/fpga/usrp2/fifo/.gitignore +++ b/fpga/usrp2/fifo/.gitignore @@ -1 +1,3 @@ +*.vcd +*.lxt a.out diff --git a/fpga/usrp2/fifo/fifo19_to_fifo36.v b/fpga/usrp2/fifo/fifo19_to_fifo36.v index 5f9aeff9b..2f530109f 100644 --- a/fpga/usrp2/fifo/fifo19_to_fifo36.v +++ b/fpga/usrp2/fifo/fifo19_to_fifo36.v @@ -1,26 +1,32 @@ +// Parameter LE tells us if we are little-endian. +// Little-endian means send lower 16 bits first. +// Default is big endian (network order), send upper bits first. + module fifo19_to_fifo36 - (input clk, input reset, input clear, - input [18:0] f19_datain, - input f19_src_rdy_i, - output f19_dst_rdy_o, + #(parameter LE=0) + (input clk, input reset, input clear, + input [18:0] f19_datain, + input f19_src_rdy_i, + output f19_dst_rdy_o, - output [35:0] f36_dataout, - output f36_src_rdy_o, - input f36_dst_rdy_i, - output [31:0] debug - ); + output [35:0] f36_dataout, + output f36_src_rdy_o, + input f36_dst_rdy_i, + output [31:0] debug + ); - reg f36_sof, f36_eof, f36_occ; + reg f36_sof, f36_eof; + reg [1:0] f36_occ; - reg [1:0] state; - reg [15:0] dat0, dat1; + reg [1:0] state; + reg [15:0] dat0, dat1; - wire f19_sof = f19_datain[16]; - wire f19_eof = f19_datain[17]; - wire f19_occ = f19_datain[18]; + wire f19_sof = f19_datain[16]; + wire f19_eof = f19_datain[17]; + wire f19_occ = f19_datain[18]; - wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i; + wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i; always @(posedge clk) if(f19_src_rdy_i & ((state==0)|xfer_out)) @@ -68,7 +74,8 @@ module fifo19_to_fifo36 dat0 <= f19_datain; assign f19_dst_rdy_o = xfer_out | (state != 2); - assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1}; + assign f36_dataout = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} : + {f36_occ,f36_eof,f36_sof,dat0,dat1}; assign f36_src_rdy_o = (state == 2); assign debug = state; diff --git a/fpga/usrp2/fifo/fifo36_to_fifo18.v b/fpga/usrp2/fifo/fifo36_to_fifo18.v deleted file mode 100644 index b636ab9ca..000000000 --- a/fpga/usrp2/fifo/fifo36_to_fifo18.v +++ /dev/null @@ -1,40 +0,0 @@ - -module fifo36_to_fifo18 - (input clk, input reset, input clear, - input [35:0] f36_datain, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output [17:0] f18_dataout, - output f18_src_rdy_o, - input f18_dst_rdy_i ); - - wire f36_sof = f36_datain[32]; - wire f36_eof = f36_datain[33]; - wire f36_occ = f36_datain[35:34]; - - reg phase; - - wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); - - assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; - assign f18_dataout[16] = phase ? 0 : f36_sof; - assign f18_dataout[17] = phase ? f36_eof : half_line; - - assign f18_src_rdy_o = f36_src_rdy_i; - assign f36_dst_rdy_o = (phase | half_line) & f18_dst_rdy_i; - - wire f18_xfer = f18_src_rdy_o & f18_dst_rdy_i; - wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; - - always @(posedge clk) - if(reset) - phase <= 0; - else if(f36_xfer) - phase <= 0; - else if(f18_xfer) - phase <= 1; - - -endmodule // fifo36_to_fifo18 - diff --git a/fpga/usrp2/fifo/fifo36_to_fifo19.v b/fpga/usrp2/fifo/fifo36_to_fifo19.v index de249aaeb..517a2a476 100644 --- a/fpga/usrp2/fifo/fifo36_to_fifo19.v +++ b/fpga/usrp2/fifo/fifo36_to_fifo19.v @@ -1,33 +1,38 @@ -module fifo36_to_fifo19 - (input clk, input reset, input clear, - input [35:0] f36_datain, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output [18:0] f19_dataout, - output f19_src_rdy_o, - input f19_dst_rdy_i ); +// Parameter LE tells us if we are little-endian. +// Little-endian means send lower 16 bits first. +// Default is big endian (network order), send upper bits first. +module fifo36_to_fifo19 + #(parameter LE=0) + (input clk, input reset, input clear, + input [35:0] f36_datain, + input f36_src_rdy_i, + output f36_dst_rdy_o, + + output [18:0] f19_dataout, + output f19_src_rdy_o, + input f19_dst_rdy_i ); + wire f36_sof = f36_datain[32]; wire f36_eof = f36_datain[33]; wire f36_occ = f36_datain[35:34]; - - reg phase; - - wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); - assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; + reg phase; + + wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); + + assign f19_dataout[15:0] = (LE ^ phase) ? f36_datain[15:0] : f36_datain[31:16]; assign f19_dataout[16] = phase ? 0 : f36_sof; assign f19_dataout[17] = phase ? f36_eof : half_line; assign f19_dataout[18] = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3)); assign f19_src_rdy_o = f36_src_rdy_i; assign f36_dst_rdy_o = (phase | half_line) & f19_dst_rdy_i; - - wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; - wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; - + + wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; + wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; + always @(posedge clk) if(reset) phase <= 0; @@ -36,6 +41,5 @@ module fifo36_to_fifo19 else if(f19_xfer) phase <= 1; - + endmodule // fifo36_to_fifo19 - diff --git a/fpga/usrp2/fifo/fifo36_to_ll8.v b/fpga/usrp2/fifo/fifo36_to_ll8.v index 0dee1dfc6..9604d0e38 100644 --- a/fpga/usrp2/fifo/fifo36_to_ll8.v +++ b/fpga/usrp2/fifo/fifo36_to_ll8.v @@ -55,6 +55,5 @@ module fifo36_to_ll8 assign advance = ll_src_rdy & ll_dst_rdy; assign f36_dst_rdy_o = advance & ((state==3)|ll_eof); - assign debug = state; endmodule // ll8_to_fifo36 diff --git a/fpga/usrp2/gpmc/.gitignore b/fpga/usrp2/gpmc/.gitignore new file mode 100644 index 000000000..3e14fa4f7 --- /dev/null +++ b/fpga/usrp2/gpmc/.gitignore @@ -0,0 +1,2 @@ +*.gif + diff --git a/fpga/usrp2/gpmc/Makefile.srcs b/fpga/usrp2/gpmc/Makefile.srcs new file mode 100644 index 000000000..bff6ae3e0 --- /dev/null +++ b/fpga/usrp2/gpmc/Makefile.srcs @@ -0,0 +1,20 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# SERDES Sources +################################################## +GPMC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpmc/, \ +dbsm.v \ +edge_sync.v \ +fifo_to_gpmc_async.v \ +fifo_to_gpmc_sync.v \ +fifo_watcher.v \ +gpmc_async.v \ +gpmc_sync.v \ +gpmc_to_fifo_async.v \ +gpmc_to_fifo_sync.v \ +gpmc_wb.v \ +ram_to_fifo.v \ +)) diff --git a/fpga/usrp2/gpmc/burst_data_write.txt b/fpga/usrp2/gpmc/burst_data_write.txt new file mode 100644 index 000000000..3b5dfc785 --- /dev/null +++ b/fpga/usrp2/gpmc/burst_data_write.txt @@ -0,0 +1,16 @@ +# OMAP burst writes to FPGA + +CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA1. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA2. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA3. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA4. +CLK=1. +CLK=0,nWE=1,nCS=1,DATA=Z. +CLK=1. + + diff --git a/fpga/usrp2/gpmc/dbsm.v b/fpga/usrp2/gpmc/dbsm.v new file mode 100644 index 000000000..530af7205 --- /dev/null +++ b/fpga/usrp2/gpmc/dbsm.v @@ -0,0 +1,80 @@ + +module bsm + (input clk, input reset, input clear, + input write_done, + input read_done, + output readable, + output writeable); + + reg state; + localparam ST_WRITEABLE = 0; + localparam ST_READABLE = 1; + + always @(posedge clk) + if(reset | clear) + state <= ST_WRITEABLE; + else + case(state) + ST_WRITEABLE : + if(write_done) + state <= ST_READABLE; + ST_READABLE : + if(read_done) + state <= ST_WRITEABLE; + endcase // case (state) + + assign readable = (state == ST_READABLE); + assign writeable = (state == ST_WRITEABLE); + +endmodule // bsm + +module dbsm + (input clk, input reset, input clear, + output reg read_sel, output read_ready, input read_done, + output reg write_sel, output write_ready, input write_done); + + localparam NUM_BUFS = 2; + + wire [NUM_BUFS-1:0] readable, writeable, read_done_buf, write_done_buf; + + // Two of these buffer state machines + genvar i; + generate + for(i=0;i<NUM_BUFS;i=i+1) + begin : BSMS + bsm bsm(.clk(clk), .reset(reset), .clear(clear), + .write_done((write_sel == i) & write_done), + .read_done((read_sel == i) & read_done), + .readable(readable[i]), .writeable(writeable[i])); + end + endgenerate + + reg full; + + always @(posedge clk) + if(reset | clear) + begin + write_sel <= 0; + full <= 0; + end + else + if(write_done & writeable[write_sel]) + if(write_sel ==(NUM_BUFS-1)) + write_sel <= 0; + else + write_sel <= write_sel + 1; + + always @(posedge clk) + if(reset | clear) + read_sel <= 0; + else + if(read_done & readable[read_sel]) + if(read_sel==(NUM_BUFS-1)) + read_sel <= 0; + else + read_sel <= read_sel + 1; + + assign write_ready = writeable[write_sel]; + assign read_ready = readable[read_sel]; + +endmodule // dbsm diff --git a/fpga/usrp2/gpmc/edge_sync.v b/fpga/usrp2/gpmc/edge_sync.v new file mode 100644 index 000000000..5d9417c08 --- /dev/null +++ b/fpga/usrp2/gpmc/edge_sync.v @@ -0,0 +1,22 @@ + + +module edge_sync + #(parameter POSEDGE = 1) + (input clk, + input rst, + input sig, + output trig); + + reg [1:0] delay; + + always @(posedge clk) + if(rst) + delay <= 2'b00; + else + delay <= {delay[0],sig}; + + assign trig = POSEDGE ? (delay==2'b01) : (delay==2'b10); + +endmodule // edge_sync + + diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc_async.v b/fpga/usrp2/gpmc/fifo_to_gpmc_async.v new file mode 100644 index 000000000..cf8b6e861 --- /dev/null +++ b/fpga/usrp2/gpmc/fifo_to_gpmc_async.v @@ -0,0 +1,37 @@ + +// Assumes an asynchronous GPMC cycle +// If a packet bigger or smaller than we are told is sent, behavior is undefined. +// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. +// If there is a bus error, we should be reset + +module fifo_to_gpmc_async + (input clk, input reset, input clear, + input [17:0] data_i, input src_rdy_i, output dst_rdy_o, + output [15:0] EM_D, input EM_NCS, input EM_NOE, + input [15:0] frame_len); + + // Synchronize the async control signals + reg [2:0] cs_del, oe_del; + reg [15:0] counter; + + always @(posedge clk) + if(reset) + begin + cs_del <= 3'b11; + oe_del <= 3'b11; + end + else + begin + cs_del <= { cs_del[1:0], EM_NCS }; + oe_del <= { oe_del[1:0], EM_NOE }; + end + + wire do_read = ( (~cs_del[1] | ~cs_del[2]) & (oe_del[1:0] == 2'b01)); // change output on trailing edge + wire first_read = (counter == 0); + wire last_read = ((counter+1) == frame_len); + + assign EM_D = data_i[15:0]; + + assign dst_rdy_o = do_read; + +endmodule // fifo_to_gpmc_async diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v b/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v new file mode 100644 index 000000000..ef59d7137 --- /dev/null +++ b/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v @@ -0,0 +1,26 @@ + +// Assumes a GPMC cycle with GPMC clock, as in the timing diagrams +// If a packet bigger or smaller than we are told is sent, behavior is undefined. +// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. +// If there is a bus error, we should be reset + +module fifo_to_gpmc_sync + (input arst, + input [17:0] data_i, input src_rdy_i, output dst_rdy_o, + input EM_CLK, output [15:0] EM_D, input EM_NCS, input EM_NOE, + output fifo_ready, + output reg bus_error); + + assign EM_D = data_i[15:0]; + wire read_access = ~EM_NCS & ~EM_NOE; + + assign dst_rdy_o = read_access; + + always @(posedge EM_CLK or posedge arst) + if(arst) + bus_error <= 0; + else if(dst_rdy_o & ~src_rdy_i) + bus_error <= 1; + + +endmodule // fifo_to_gpmc_sync diff --git a/fpga/usrp2/gpmc/fifo_watcher.v b/fpga/usrp2/gpmc/fifo_watcher.v new file mode 100644 index 000000000..fe4e35de3 --- /dev/null +++ b/fpga/usrp2/gpmc/fifo_watcher.v @@ -0,0 +1,56 @@ + + +module fifo_watcher + (input clk, input reset, input clear, + input src_rdy1, input dst_rdy1, input sof1, input eof1, + input src_rdy2, input dst_rdy2, input sof2, input eof2, + output reg have_packet, output [15:0] length, output reg bus_error, + output [31:0] debug); + + wire write = src_rdy1 & dst_rdy1 & eof1; + wire read = src_rdy2 & dst_rdy2 & eof2; + wire have_packet_int; + reg [15:0] counter; + wire [4:0] pkt_count; + assign debug = pkt_count; + + fifo_short #(.WIDTH(16)) frame_lengths + (.clk(clk), .reset(reset), .clear(clear), + .datain(counter), .src_rdy_i(write), .dst_rdy_o(), + .dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read), + .occupied(pkt_count), .space()); + + always @(posedge clk) + if(reset | clear) + counter <= 1; // Start at 1 + else if(src_rdy1 & dst_rdy1) + if(eof1) + counter <= 1; + else + counter <= counter + 1; + + always @(posedge clk) + if(reset | clear) + bus_error <= 0; + else if(dst_rdy2 & ~src_rdy2) + bus_error <= 1; + else if(read & ~have_packet_int) + bus_error <= 1; + + reg in_packet; + always @(posedge clk) + if(reset | clear) + have_packet <= 0; + else + have_packet <= (have_packet_int & ~in_packet) | (pkt_count>1) ; + + always @(posedge clk) + if(reset | clear) + in_packet <= 0; + else if(src_rdy2 & dst_rdy2) + if(eof2) + in_packet <= 0; + else + in_packet <= 1; + +endmodule // fifo_watcher diff --git a/fpga/usrp2/gpmc/gpmc_async.v b/fpga/usrp2/gpmc/gpmc_async.v new file mode 100644 index 000000000..23bad56ae --- /dev/null +++ b/fpga/usrp2/gpmc/gpmc_async.v @@ -0,0 +1,130 @@ +////////////////////////////////////////////////////////////////////////////////// + +module gpmc_async + #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11) + (// GPMC signals + input arst, + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + // GPIOs for FIFO signalling + output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset, + + // Wishbone signals + input wb_clk, input wb_rst, + output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + + // FIFO interface + input fifo_clk, input fifo_rst, input clear_tx, input clear_rx, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + + input [15:0] tx_frame_len, output [15:0] rx_frame_len, + + output [31:0] debug + ); + + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_fifo; + wire [15:0] EM_D_wb; + + assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; + + wire bus_error_tx, bus_error_rx; + + always @(posedge fifo_clk) + if(fifo_rst | clear_tx | clear_rx) + bus_error <= 0; + else + bus_error <= bus_error_tx | bus_error_rx; + + // CS4 is RAM_2PORT for DATA PATH (high-speed data) + // Writes go into one RAM, reads come from the other + // CS6 is for CONTROL PATH (wishbone) + + // //////////////////////////////////////////// + // TX Data Path + + wire [17:0] tx18_data, tx18b_data; + wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; + wire [15:0] tx_fifo_space; + wire [35:0] tx36_data; + wire tx36_src_rdy, tx36_dst_rdy; + + gpmc_to_fifo_async gpmc_to_fifo_async + (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), + .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .clear(clear_tx), + .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), + .bus_error(bus_error_tx) ); + + fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), + .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied()); + + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), + .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); + + fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), + .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), + .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i)); + + // //////////////////////////////////////////// + // RX Data Path + + wire [17:0] rx18_data, rx18b_data; + wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; + wire [15:0] rx_fifo_space; + wire [35:0] rx36_data; + wire rx36_src_rdy, rx36_dst_rdy; + wire dummy; + + fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), + .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), + .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); + + fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), + .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied()); + + fifo_to_gpmc_async fifo_to_gpmc_async + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), + .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), + .frame_len(rx_frame_len) ); + + wire [31:0] pkt_count; + + fifo_watcher fifo_watcher + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]), + .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]), + .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx), + .debug(pkt_count)); + + // //////////////////////////////////////////// + // Control path on CS6 + + gpmc_wb gpmc_wb + (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), + .wb_ack_i(wb_ack_i) ); + + assign debug = pkt_count; + +endmodule // gpmc_async diff --git a/fpga/usrp2/gpmc/gpmc_sync.v b/fpga/usrp2/gpmc/gpmc_sync.v new file mode 100644 index 000000000..61c54a793 --- /dev/null +++ b/fpga/usrp2/gpmc/gpmc_sync.v @@ -0,0 +1,108 @@ +////////////////////////////////////////////////////////////////////////////////// + +module gpmc_sync + (// GPMC signals + input arst, + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + // GPIOs for FIFO signalling + output rx_have_data, output tx_have_space, output bus_error, input bus_reset, + + // Wishbone signals + input wb_clk, input wb_rst, + output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + + // FIFO interface + input fifo_clk, input fifo_rst, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + + output [31:0] debug + ); + + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_fifo; + wire [15:0] EM_D_wb; + + assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; + + wire bus_error_tx, bus_error_rx; + assign bus_error = bus_error_tx | bus_error_rx; + + // CS4 is RAM_2PORT for DATA PATH (high-speed data) + // Writes go into one RAM, reads come from the other + // CS6 is for CONTROL PATH (wishbone) + + // //////////////////////////////////////////// + // TX Data Path + + wire [17:0] tx18_data, tx18b_data; + wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; + wire [15:0] tx_fifo_space, tx_frame_len; + + assign tx_frame_len = 10; + + gpmc_to_fifo_sync gpmc_to_fifo_sync + (.arst(arst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), + .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), + .bus_error(bus_error_tx) ); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) tx_fifo + (.wclk(EM_CLK), .datain(tx18_data), + .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), + .rclk(fifo_clk), .dataout(tx18b_data), + .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst)); + + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), + .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i)); + + // //////////////////////////////////////////// + // RX Data Path + + wire [17:0] rx18_data, rx18b_data; + wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; + wire [15:0] rx_fifo_space, rx_frame_len; + wire dummy; + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), + .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo + (.wclk(fifo_clk), .datain(rx18_data), + .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), + .rclk(EM_CLK), .dataout(rx18b_data), + .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied(), .arst(arst)); + + fifo_to_gpmc_sync fifo_to_gpmc_sync + (.arst(arst), + .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), + .EM_CLK(EM_CLK), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), + .fifo_ready(rx_have_data) ); + + fifo_watcher fifo_watcher + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .src_rdy(rx18_src_rdy), .dst_rdy(rx18_dst_rdy), .sof(rx18_data[16]), .eof(rx18_data[17]), + .have_packet(), .length(), .next() ); + + // //////////////////////////////////////////// + // Control path on CS6 + + gpmc_wb gpmc_wb + (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), + .wb_ack_i(wb_ack_i) ); + + assign debug = 0; + +endmodule // gpmc_sync diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo_async.v b/fpga/usrp2/gpmc/gpmc_to_fifo_async.v new file mode 100644 index 000000000..55c0cef50 --- /dev/null +++ b/fpga/usrp2/gpmc/gpmc_to_fifo_async.v @@ -0,0 +1,68 @@ + +module gpmc_to_fifo_async + (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE, + + input fifo_clk, input fifo_rst, input clear, + output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, + + input [15:0] frame_len, input [15:0] fifo_space, output reg fifo_ready, + output reg bus_error ); + + reg [15:0] counter; + // Synchronize the async control signals + reg [1:0] cs_del, we_del; + always @(posedge fifo_clk) + if(fifo_rst) + begin + cs_del <= 2'b11; + we_del <= 2'b11; + end + else + begin + cs_del <= { cs_del[0], EM_NCS }; + we_del <= { we_del[0], EM_NWE }; + end + + wire do_write = (~cs_del[0] & (we_del == 2'b10)); + wire first_write = (counter == 0); + wire last_write = ((counter+1) == frame_len); + + always @(posedge fifo_clk) + if(do_write) + begin + data_o[15:0] <= EM_D; + data_o[16] <= first_write; + data_o[17] <= last_write; + // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME + end + + always @(posedge fifo_clk) + if(fifo_rst | clear) + src_rdy_o <= 0; + else if(do_write) + src_rdy_o <= 1; + else + src_rdy_o <= 0; // Assume it was taken + + always @(posedge fifo_clk) + if(fifo_rst | clear) + counter <= 0; + else if(do_write) + if(last_write) + counter <= 0; + else + counter <= counter + 1; + + always @(posedge fifo_clk) + if(fifo_rst | clear) + fifo_ready <= 0; + else + fifo_ready <= /* first_write & */ (fifo_space > 16'd1023); + + always @(posedge fifo_clk) + if(fifo_rst | clear) + bus_error <= 0; + else if(src_rdy_o & ~dst_rdy_i) + bus_error <= 1; + +endmodule // gpmc_to_fifo_async diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v b/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v new file mode 100644 index 000000000..688de0e17 --- /dev/null +++ b/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v @@ -0,0 +1,57 @@ + +// Assumes a GPMC cycle with GPMC clock, as in the timing diagrams +// If a packet bigger or smaller than we are told is sent, behavior is undefined. +// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. +// If there is a bus error, we should be reset + +module gpmc_to_fifo_sync + (input arst, + input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE, + input EM_NCS, input EM_NWE, + output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, + input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready, + output reg bus_error); + + reg [10:0] counter; + wire first_write = (counter == 0); + wire last_write = ((counter+1) == frame_len); + wire do_write = ~EM_NCS & ~EM_NWE; + + always @(posedge EM_CLK or posedge arst) + if(arst) + data_o <= 0; + else if(do_write) + begin + data_o[15:0] <= EM_D; + data_o[16] <= first_write; + data_o[17] <= last_write; + // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME + end + + always @(posedge EM_CLK or posedge arst) + if(arst) + src_rdy_o <= 0; + else if(do_write & ~bus_error) // Don't put junk in if there is a bus error + src_rdy_o <= 1; + else + src_rdy_o <= 0; // Assume it was taken, ignore dst_rdy_i + + always @(posedge EM_CLK or posedge arst) + if(arst) + counter <= 0; + else if(do_write) + if(last_write) + counter <= 0; + else + counter <= counter + 1; + + assign fifo_ready = first_write & (fifo_space > frame_len); + + always @(posedge EM_CLK or posedge arst) + if(arst) + bus_error <= 0; + else if(src_rdy_o & ~dst_rdy_i) + bus_error <= 1; + // must be reset to make the error go away + +endmodule // gpmc_to_fifo_sync diff --git a/fpga/usrp2/gpmc/gpmc_wb.v b/fpga/usrp2/gpmc/gpmc_wb.v new file mode 100644 index 000000000..db6fbc6e9 --- /dev/null +++ b/fpga/usrp2/gpmc/gpmc_wb.v @@ -0,0 +1,57 @@ + + +module gpmc_wb + (input EM_CLK, input [15:0] EM_D_in, output [15:0] EM_D_out, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_NCS, input EM_NWE, input EM_NOE, + + input wb_clk, input wb_rst, + output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i); + + // //////////////////////////////////////////// + // Control Path, Wishbone bus bridge (wb master) + reg [1:0] cs_del, we_del, oe_del; + + // Synchronize the async control signals + always @(posedge wb_clk) + begin + cs_del <= { cs_del[0], EM_NCS }; + we_del <= { we_del[0], EM_NWE }; + oe_del <= { oe_del[0], EM_NOE }; + end + + always @(posedge wb_clk) + if(cs_del == 2'b10) // Falling Edge + wb_adr_o <= { EM_A, 1'b0 }; + + always @(posedge wb_clk) + if(we_del == 2'b10) // Falling Edge + begin + wb_dat_mosi <= EM_D_in; + wb_sel_o <= ~EM_NBE; + end + + reg [15:0] EM_D_hold; + + always @(posedge wb_clk) + if(wb_ack_i) + EM_D_hold <= wb_dat_miso; + + assign EM_D_out = wb_ack_i ? wb_dat_miso : EM_D_hold; + + assign wb_cyc_o = wb_stb_o; + + always @(posedge wb_clk) + if(~cs_del[0] & (we_del == 2'b10) ) + wb_we_o <= 1; + else if(wb_ack_i) // Turn off we when done. Could also use we_del[0], others... + wb_we_o <= 0; + + // FIXME should this look at cs_del[1]? + always @(posedge wb_clk) + if(~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10))) + wb_stb_o <= 1; + else if(wb_ack_i) + wb_stb_o <= 0; + +endmodule // gpmc_wb diff --git a/fpga/usrp2/gpmc/make_timing_diag b/fpga/usrp2/gpmc/make_timing_diag new file mode 100755 index 000000000..03166ad35 --- /dev/null +++ b/fpga/usrp2/gpmc/make_timing_diag @@ -0,0 +1,6 @@ +#!/bin/sh +drawtiming -o single_data_write.gif single_data_write.txt +drawtiming -o single_data_read.gif single_data_read.txt +drawtiming -o burst_data_write.gif burst_data_write.txt +#drawtiming -o burst_data_read.gif burst_data_read.txt + diff --git a/fpga/usrp2/gpmc/ram_to_fifo.v b/fpga/usrp2/gpmc/ram_to_fifo.v new file mode 100644 index 000000000..8549dcc35 --- /dev/null +++ b/fpga/usrp2/gpmc/ram_to_fifo.v @@ -0,0 +1,46 @@ + + +module ram_to_fifo + (input clk, input reset, + input [10:0] read_length, // From the dbsm (?) + output read_en, output reg [8:0] read_addr, input [31:0] read_data, input read_ready, output read_done, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + // read_length/2 = number of 32 bit lines, numbered 0 through read_length/2-1 + wire [8:0] last_line = (read_length[10:1]-1); + + reg read_phase, sop; + + assign read_en = (read_phase == 0) | dst_rdy_i; + assign src_rdy_o = (read_phase == 1); + + always @(posedge clk) + if(reset) + begin + read_addr <= 0; + read_phase <= 0; + sop <= 1; + end + else + if(read_phase == 0) + begin + read_addr <= read_ready; + read_phase <= read_ready; + end + else if(dst_rdy_i) + begin + sop <= 0; + if(read_addr == last_line) + begin + read_addr <= 0; + read_phase <= 0; + end + else + read_addr <= read_addr + 1; + end + + assign read_done = (read_phase == 1) & (read_addr == last_line) & dst_rdy_i; + wire eop = (read_addr == last_line); + assign data_o = { 2'b00, eop, sop, read_data }; + +endmodule // ram_to_fifo diff --git a/fpga/usrp2/gpmc/single_data_read.txt b/fpga/usrp2/gpmc/single_data_read.txt new file mode 100644 index 000000000..1dc0e3a78 --- /dev/null +++ b/fpga/usrp2/gpmc/single_data_read.txt @@ -0,0 +1,12 @@ +# OMAP writes to FPGA +# initialize the signals +CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z. +CLK=1. +CLK=0,nOE=0,nCS=0,DATA=RD_DATA. +CLK=1. +CLK=0. +CLK=1. +CLK=0,nOE=1,nCS=1,DATA=Z. +CLK=1. + + diff --git a/fpga/usrp2/gpmc/single_data_write.txt b/fpga/usrp2/gpmc/single_data_write.txt new file mode 100644 index 000000000..287e3e2c1 --- /dev/null +++ b/fpga/usrp2/gpmc/single_data_write.txt @@ -0,0 +1,10 @@ +# OMAP writes to FPGA +# initialize the signals +CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA. +CLK=1. +CLK=0,nWE=1,nCS=1,DATA=Z. +CLK=1. + + diff --git a/fpga/usrp2/models/gpmc_model_async.v b/fpga/usrp2/models/gpmc_model_async.v new file mode 100644 index 000000000..beeaee028 --- /dev/null +++ b/fpga/usrp2/models/gpmc_model_async.v @@ -0,0 +1,130 @@ +`timescale 1ps/1ps + +module gpmc_model_async + (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, + output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, + output reg EM_NWE, output reg EM_NOE ); + + assign EM_CLK = 0; + reg [15:0] EM_D_int; + assign EM_D = EM_D_int; + + initial + begin + EM_A <= 10'bz; + EM_NBE <= 2'b11; + EM_NWE <= 1; + EM_NOE <= 1; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + EM_D_int <= 16'bz; + EM_WAIT0 <= 0; // FIXME this is actually an input + end + + task GPMC_Write; + input ctrl; + input [10:0] addr; + input [15:0] data; + begin + #23000; + EM_A <= addr[10:1]; + EM_D_int <= data; + #20100; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + #14000; + EM_NWE <= 0; + #77500; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + //#1.5; + EM_NWE <= 1; + #60000; + EM_A <= 10'bz; + EM_D_int <= 16'bz; + end + endtask // GPMC_Write + + task GPMC_Read; + input ctrl; + input [10:0] addr; + begin + #13000; + EM_A <= addr[10:1]; + #3000; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + #14000; + EM_NOE <= 0; + #77500; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + //#1.5; + $display("Data Read from GPMC: %X",EM_D); + EM_NOE <= 1; + #254000; + EM_A <= 10'bz; + end + endtask // GPMC_Read + + initial + begin + #1000000; + GPMC_Write(1,36,16'hF00D); + #1000000; + GPMC_Read(1,36); + #1000000; + GPMC_Write(0,0,16'h1234); + GPMC_Write(0,0,16'h5678); + GPMC_Write(0,0,16'h9abc); + GPMC_Write(0,0,16'hF00D); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + #1000000; + GPMC_Write(0,0,16'h1234); + GPMC_Write(0,0,16'h5678); + GPMC_Write(0,0,16'h9abc); + GPMC_Write(0,0,16'hF00D); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'h9876); + #1000000; + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + #1000000; + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + #1000000; + GPMC_Read(0,0); + #100000000; + $finish; + end + +endmodule // gpmc_model_async diff --git a/fpga/usrp2/models/gpmc_model_sync.v b/fpga/usrp2/models/gpmc_model_sync.v new file mode 100644 index 000000000..641720c15 --- /dev/null +++ b/fpga/usrp2/models/gpmc_model_sync.v @@ -0,0 +1,97 @@ + + +module gpmc_model_sync + (output reg EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, + output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, + output reg EM_NWE, output reg EM_NOE ); + + reg [15:0] EM_D_int; + assign EM_D = EM_D_int; + + initial + begin + EM_CLK <= 0; + EM_A <= 10'bz; + EM_NBE <= 2'b11; + EM_NWE <= 1; + EM_NOE <= 1; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + EM_D_int <= 16'bz; + EM_WAIT0 <= 0; // FIXME this is actually an input + end + + task GPMC_Write; + input ctrl; + input [10:0] addr; + input [15:0] data; + begin + EM_CLK <= 1; + #10; + EM_CLK <= 0; + EM_NWE <= 0; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + EM_A <= addr[10:1]; + EM_D_int <= data; + #10; + EM_CLK <= 1; + #10; + EM_CLK <= 0; + EM_NWE <= 1; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + EM_A <= 10'bz; + EM_D_int <= 16'bz; + #100; + end + endtask // GPMC_Write + + task GPMC_Read; + input ctrl; + input [10:0] addr; + begin + #1.3; + EM_A <= addr[10:1]; + #3; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + #14; + EM_NOE <= 0; + #77.5; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + //#1.5; + $display("Data Read from GPMC: %X",EM_D); + EM_NOE <= 1; + #254; + EM_A <= 10'bz; + end + endtask // GPMC_Read + + initial + begin + #1000; + GPMC_Write(1,36,16'hF00D); + #1000; + GPMC_Read(1,36); + #1000; + GPMC_Write(0,36,16'h1234); + GPMC_Write(0,38,16'h5678); + GPMC_Write(0,40,16'h9abc); + GPMC_Write(0,11'h2F4,16'hF00D); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + #100000; + $finish; + end + +endmodule // gpmc_model diff --git a/fpga/usrp2/opencores/Makefile.srcs b/fpga/usrp2/opencores/Makefile.srcs index 30360a17d..284578b39 100644 --- a/fpga/usrp2/opencores/Makefile.srcs +++ b/fpga/usrp2/opencores/Makefile.srcs @@ -24,5 +24,5 @@ spi/rtl/verilog/spi_clgen.v \ spi/rtl/verilog/spi_defines.v \ spi/rtl/verilog/spi_shift.v \ spi/rtl/verilog/spi_top.v \ -spi/rtl/verilog/timescale.v \ +spi/rtl/verilog/spi_top16.v \ )) diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v index 38ca3a023..6c066d5d9 100644 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v +++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v @@ -11,7 +11,7 @@ module aeMB_core_BE (input sys_clk_i, input sys_rst_i, // Instruction port - output [14:0] if_adr, + output [ISIZ-1:0] if_adr, input [31:0] if_dat, // Data port output dwb_we_o, @@ -34,7 +34,7 @@ module aeMB_core_BE assign dwb_cyc_o = dwb_stb_o; assign iwb_ack_i = 1'b1; - assign if_adr = iwb_adr_o[14:0]; + assign if_adr = iwb_adr_o[ISIZ-1:0]; assign iwb_dat_i = if_dat; // Note some "wishbone" instruction fetch signals pruned on external interface diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v index 7bc4f6e5e..2d9c34f40 100644 --- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v +++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v @@ -39,12 +39,9 @@ ////////////////////////////////////////////////////////////////////// `include "spi_defines.v" -`include "timescale.v" module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); - parameter Tp = 1; - input clk_in; // input clock (system clock) input rst; // reset input enable; // clock enable @@ -68,40 +65,40 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, assign cnt_one = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; // Counter counts half period - always @(posedge clk_in or posedge rst) + always @(posedge clk_in) begin if(rst) - cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}}; + cnt <= {`SPI_DIVIDER_LEN{1'b1}}; else begin if(!enable || cnt_zero) - cnt <= #Tp divider; + cnt <= divider; else - cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; + cnt <= cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; end end // clk_out is asserted every other half period - always @(posedge clk_in or posedge rst) + always @(posedge clk_in) begin if(rst) - clk_out <= #Tp 1'b0; + clk_out <= 1'b0; else - clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; + clk_out <= (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; end // Pos and neg edge signals - always @(posedge clk_in or posedge rst) + always @(posedge clk_in) begin if(rst) begin - pos_edge <= #Tp 1'b0; - neg_edge <= #Tp 1'b0; + pos_edge <= 1'b0; + neg_edge <= 1'b0; end else begin - pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); - neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); + pos_edge <= (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); + neg_edge <= (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); end end endmodule diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v index a6925918e..3e4dd0e3c 100644 --- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v +++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v @@ -43,8 +43,8 @@ // low frequency of system clock this can be reduced. // Use SPI_DIVIDER_LEN for fine tuning theexact number. // -//`define SPI_DIVIDER_LEN_8 -`define SPI_DIVIDER_LEN_16 +`define SPI_DIVIDER_LEN_8 +//`define SPI_DIVIDER_LEN_16 //`define SPI_DIVIDER_LEN_24 //`define SPI_DIVIDER_LEN_32 @@ -102,8 +102,8 @@ // Number of device select signals. Use SPI_SS_NB for fine tuning the // exact number. // -`define SPI_SS_NB_8 -//`define SPI_SS_NB_16 +//`define SPI_SS_NB_8 +`define SPI_SS_NB_16 //`define SPI_SS_NB_24 //`define SPI_SS_NB_32 @@ -137,7 +137,7 @@ `define SPI_TX_2 2 `define SPI_TX_3 3 `define SPI_CTRL 4 -`define SPI_DEVIDE 5 +`define SPI_DIVIDE 5 `define SPI_SS 6 // diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v index b17ac8b1f..ac3bb3f48 100644 --- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v +++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v @@ -39,15 +39,12 @@ ////////////////////////////////////////////////////////////////////// `include "spi_defines.v" -`include "timescale.v" module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, pos_edge, neg_edge, rx_negedge, tx_negedge, tip, last, p_in, p_out, s_clk, s_in, s_out); - parameter Tp = 1; - input clk; // system clock input rst; // reset input [3:0] latch; // latch signal for storing the data in shift register @@ -89,149 +86,149 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last; // Character bit counter - always @(posedge clk or posedge rst) + always @(posedge clk) begin if(rst) - cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}}; + cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}}; else begin if(tip) - cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; + cnt <= pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; else - cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; + cnt <= !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; end end // Transfer in progress - always @(posedge clk or posedge rst) + always @(posedge clk) begin if(rst) - tip <= #Tp 1'b0; + tip <= 1'b0; else if(go && ~tip) - tip <= #Tp 1'b1; + tip <= 1'b1; else if(tip && last && pos_edge) - tip <= #Tp 1'b0; + tip <= 1'b0; end // Sending bits to the line - always @(posedge clk or posedge rst) + always @(posedge clk) begin if (rst) - s_out <= #Tp 1'b0; + s_out <= 1'b0; else - s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; + s_out <= (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; end // Receiving bits from the line - always @(posedge clk or posedge rst) + always @(posedge clk) begin if (rst) - data <= #Tp {`SPI_MAX_CHAR{1'b0}}; + data <= {`SPI_MAX_CHAR{1'b0}}; `ifdef SPI_MAX_CHAR_128 else if (latch[0] && !tip) begin if (byte_sel[3]) - data[31:24] <= #Tp p_in[31:24]; + data[31:24] <= p_in[31:24]; if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; + data[23:16] <= p_in[23:16]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; end else if (latch[1] && !tip) begin if (byte_sel[3]) - data[63:56] <= #Tp p_in[31:24]; + data[63:56] <= p_in[31:24]; if (byte_sel[2]) - data[55:48] <= #Tp p_in[23:16]; + data[55:48] <= p_in[23:16]; if (byte_sel[1]) - data[47:40] <= #Tp p_in[15:8]; + data[47:40] <= p_in[15:8]; if (byte_sel[0]) - data[39:32] <= #Tp p_in[7:0]; + data[39:32] <= p_in[7:0]; end else if (latch[2] && !tip) begin if (byte_sel[3]) - data[95:88] <= #Tp p_in[31:24]; + data[95:88] <= p_in[31:24]; if (byte_sel[2]) - data[87:80] <= #Tp p_in[23:16]; + data[87:80] <= p_in[23:16]; if (byte_sel[1]) - data[79:72] <= #Tp p_in[15:8]; + data[79:72] <= p_in[15:8]; if (byte_sel[0]) - data[71:64] <= #Tp p_in[7:0]; + data[71:64] <= p_in[7:0]; end else if (latch[3] && !tip) begin if (byte_sel[3]) - data[127:120] <= #Tp p_in[31:24]; + data[127:120] <= p_in[31:24]; if (byte_sel[2]) - data[119:112] <= #Tp p_in[23:16]; + data[119:112] <= p_in[23:16]; if (byte_sel[1]) - data[111:104] <= #Tp p_in[15:8]; + data[111:104] <= p_in[15:8]; if (byte_sel[0]) - data[103:96] <= #Tp p_in[7:0]; + data[103:96] <= p_in[7:0]; end `else `ifdef SPI_MAX_CHAR_64 else if (latch[0] && !tip) begin if (byte_sel[3]) - data[31:24] <= #Tp p_in[31:24]; + data[31:24] <= p_in[31:24]; if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; + data[23:16] <= p_in[23:16]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; end else if (latch[1] && !tip) begin if (byte_sel[3]) - data[63:56] <= #Tp p_in[31:24]; + data[63:56] <= p_in[31:24]; if (byte_sel[2]) - data[55:48] <= #Tp p_in[23:16]; + data[55:48] <= p_in[23:16]; if (byte_sel[1]) - data[47:40] <= #Tp p_in[15:8]; + data[47:40] <= p_in[15:8]; if (byte_sel[0]) - data[39:32] <= #Tp p_in[7:0]; + data[39:32] <= p_in[7:0]; end `else else if (latch[0] && !tip) begin `ifdef SPI_MAX_CHAR_8 if (byte_sel[0]) - data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0]; + data[`SPI_MAX_CHAR-1:0] <= p_in[`SPI_MAX_CHAR-1:0]; `endif `ifdef SPI_MAX_CHAR_16 if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; if (byte_sel[1]) - data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8]; + data[`SPI_MAX_CHAR-1:8] <= p_in[`SPI_MAX_CHAR-1:8]; `endif `ifdef SPI_MAX_CHAR_24 if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[2]) - data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16]; + data[`SPI_MAX_CHAR-1:16] <= p_in[`SPI_MAX_CHAR-1:16]; `endif `ifdef SPI_MAX_CHAR_32 if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; + data[23:16] <= p_in[23:16]; if (byte_sel[3]) - data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24]; + data[`SPI_MAX_CHAR-1:24] <= p_in[`SPI_MAX_CHAR-1:24]; `endif end `endif `endif else - data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; + data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; end endmodule diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v index 09b2e50e1..8289449a9 100644 --- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v +++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v @@ -1,3 +1,6 @@ + +// Modified 2010 by Matt Ettus to remove old verilog style + ////////////////////////////////////////////////////////////////////// //// //// //// spi_top.v //// @@ -40,7 +43,6 @@ `include "spi_defines.v" -`include "timescale.v" module spi_top ( @@ -52,8 +54,6 @@ module spi_top ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i ); - parameter Tp = 1; - // Wishbone signals input wb_clk_i; // master clock input input wb_rst_i; // synchronous active high reset @@ -101,7 +101,7 @@ module spi_top wire last_bit; // marks last character bit // Address decoder - assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DEVIDE); + assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DIVIDE); assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL); assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0); assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1); @@ -132,96 +132,96 @@ module spi_top `endif `endif `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl}; - `SPI_DEVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider}; + `SPI_DIVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider}; `SPI_SS: wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss}; default: wb_dat = 32'bx; endcase end // Wb data out - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) - wb_dat_o <= #Tp 32'b0; + wb_dat_o <= 32'b0; else - wb_dat_o <= #Tp wb_dat; + wb_dat_o <= wb_dat; end // Wb acknowledge - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) - wb_ack_o <= #Tp 1'b0; + wb_ack_o <= 1'b0; else - wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o; + wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o; end // Wb error assign wb_err_o = 1'b0; // Interrupt - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) - wb_int_o <= #Tp 1'b0; + wb_int_o <= 1'b0; else if (ie && tip && last_bit && pos_edge) - wb_int_o <= #Tp 1'b1; + wb_int_o <= 1'b1; else if (wb_ack_o) - wb_int_o <= #Tp 1'b0; + wb_int_o <= 1'b0; end // Divider register - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) - divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}}; + divider <= {`SPI_DIVIDER_LEN{1'b0}}; else if (spi_divider_sel && wb_we_i && !tip) begin `ifdef SPI_DIVIDER_LEN_8 if (wb_sel_i[0]) - divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0]; + divider <= wb_dat_i[`SPI_DIVIDER_LEN-1:0]; `endif `ifdef SPI_DIVIDER_LEN_16 if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; + divider[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8]; + divider[`SPI_DIVIDER_LEN-1:8] <= wb_dat_i[`SPI_DIVIDER_LEN-1:8]; `endif `ifdef SPI_DIVIDER_LEN_24 if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; + divider[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - divider[15:8] <= #Tp wb_dat_i[15:8]; + divider[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16]; + divider[`SPI_DIVIDER_LEN-1:16] <= wb_dat_i[`SPI_DIVIDER_LEN-1:16]; `endif `ifdef SPI_DIVIDER_LEN_32 if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; + divider[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - divider[15:8] <= #Tp wb_dat_i[15:8]; + divider[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - divider[23:16] <= #Tp wb_dat_i[23:16]; + divider[23:16] <= wb_dat_i[23:16]; if (wb_sel_i[3]) - divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24]; + divider[`SPI_DIVIDER_LEN-1:24] <= wb_dat_i[`SPI_DIVIDER_LEN-1:24]; `endif end end // Ctrl register - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) - ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}}; + ctrl <= {`SPI_CTRL_BIT_NB{1'b0}}; else if(spi_ctrl_sel && wb_we_i && !tip) begin if (wb_sel_i[0]) - ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]}; + ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]}; if (wb_sel_i[1]) - ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; + ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; end else if(tip && last_bit && pos_edge) - ctrl[`SPI_CTRL_GO] <= #Tp 1'b0; + ctrl[`SPI_CTRL_GO] <= 1'b0; end assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE]; @@ -233,39 +233,39 @@ module spi_top assign ass = ctrl[`SPI_CTRL_ASS]; // Slave select register - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) - ss <= #Tp {`SPI_SS_NB{1'b0}}; + ss <= {`SPI_SS_NB{1'b0}}; else if(spi_ss_sel && wb_we_i && !tip) begin `ifdef SPI_SS_NB_8 if (wb_sel_i[0]) - ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0]; + ss <= wb_dat_i[`SPI_SS_NB-1:0]; `endif `ifdef SPI_SS_NB_16 if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; + ss[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8]; + ss[`SPI_SS_NB-1:8] <= wb_dat_i[`SPI_SS_NB-1:8]; `endif `ifdef SPI_SS_NB_24 if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; + ss[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - ss[15:8] <= #Tp wb_dat_i[15:8]; + ss[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16]; + ss[`SPI_SS_NB-1:16] <= wb_dat_i[`SPI_SS_NB-1:16]; `endif `ifdef SPI_SS_NB_32 if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; + ss[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - ss[15:8] <= #Tp wb_dat_i[15:8]; + ss[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - ss[23:16] <= #Tp wb_dat_i[23:16]; + ss[23:16] <= wb_dat_i[23:16]; if (wb_sel_i[3]) - ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24]; + ss[`SPI_SS_NB-1:24] <= wb_dat_i[`SPI_SS_NB-1:24]; `endif end end diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v new file mode 100644 index 000000000..ee808a8ab --- /dev/null +++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v @@ -0,0 +1,182 @@ + +// Modified 2010 by Matt Ettus to remove old verilog style and +// allow 16-bit operation + +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_top.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "spi_defines.v" + +module spi_top16 + (input wb_clk_i, input wb_rst_i, + input [4:0] wb_adr_i, + input [15:0] wb_dat_i, + output reg [15:0] wb_dat_o, + input [1:0] wb_sel_i, + input wb_we_i, input wb_stb_i, input wb_cyc_i, + output reg wb_ack_o, output wb_err_o, output reg wb_int_o, + + // SPI signals + output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i); + + // Internal signals + reg [15:0] divider; // Divider register + reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register + reg [15:0] ss; // Slave select register + reg [31:0] wb_dat; // wb data out + wire [31:0] rx; // Rx register + wire rx_negedge; // miso is sampled on negative edge + wire tx_negedge; // mosi is driven on negative edge + wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len + wire go; // go + wire lsb; // lsb first on line + wire ie; // interrupt enable + wire ass; // automatic slave select + wire spi_divider_sel; // divider register select + wire spi_ctrl_sel; // ctrl register select + wire [3:0] spi_tx_sel; // tx_l register select + wire spi_ss_sel; // ss register select + wire tip; // transfer in progress + wire pos_edge; // recognize posedge of sclk + wire neg_edge; // recognize negedge of sclk + wire last_bit; // marks last character bit + + // Address decoder + assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_DIVIDE); + assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_CTRL); + assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_0); + assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_1); + assign spi_tx_sel[2] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_2); + assign spi_tx_sel[3] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_3); + assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS); + + always @(wb_adr_i or rx or ctrl or divider or ss) + case (wb_adr_i[4:2]) + `SPI_RX_0: wb_dat = rx[31:0]; + `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl}; + `SPI_DIVIDE: wb_dat = {16'b0, divider}; + `SPI_SS: wb_dat = {16'b0, ss}; + default : wb_dat = 32'd0; + endcase // case (wb_adr_i[4:2]) + + always @(posedge wb_clk_i) + if (wb_rst_i) + wb_dat_o <= 32'b0; + else + wb_dat_o <= wb_adr_i[1] ? wb_dat[31:16] : wb_dat[15:0]; + + always @(posedge wb_clk_i) + if (wb_rst_i) + wb_ack_o <= 1'b0; + else + wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o; + + assign wb_err_o = 1'b0; + + // Interrupt + always @(posedge wb_clk_i) + if (wb_rst_i) + wb_int_o <= 1'b0; + else if (ie && tip && last_bit && pos_edge) + wb_int_o <= 1'b1; + else if (wb_ack_o) + wb_int_o <= 1'b0; + + // Divider register + always @(posedge wb_clk_i) + if (wb_rst_i) + divider <= 16'b0; + else if (spi_divider_sel && wb_we_i && !tip && ~wb_adr_i[1]) + divider <= wb_dat_i; + + // Ctrl register + always @(posedge wb_clk_i) + if (wb_rst_i) + ctrl <= {`SPI_CTRL_BIT_NB{1'b0}}; + else if(spi_ctrl_sel && wb_we_i && !tip && ~wb_adr_i[1]) + begin + if (wb_sel_i[0]) + ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]}; + if (wb_sel_i[1]) + ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; + end + else if(tip && last_bit && pos_edge) + ctrl[`SPI_CTRL_GO] <= 1'b0; + + assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE]; + assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE]; + assign go = ctrl[`SPI_CTRL_GO]; + assign char_len = ctrl[`SPI_CTRL_CHAR_LEN]; + assign lsb = ctrl[`SPI_CTRL_LSB]; + assign ie = ctrl[`SPI_CTRL_IE]; + assign ass = ctrl[`SPI_CTRL_ASS]; + + // Slave select register + always @(posedge wb_clk_i) + if (wb_rst_i) + ss <= 16'b0; + else if(spi_ss_sel && wb_we_i && !tip & ~wb_adr_i[1]) + begin + if (wb_sel_i[0]) + ss[7:0] <= wb_dat_i[7:0]; + if (wb_sel_i[1]) + ss[15:8] <= wb_dat_i[15:8]; + end + + assign ss_pad_o = ~((ss & {16{tip & ass}}) | (ss & {16{!ass}})); + + spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit), + .divider(divider[`SPI_DIVIDER_LEN-1:0]), .clk_out(sclk_pad_o), .pos_edge(pos_edge), + .neg_edge(neg_edge)); + + wire [3:0] new_sels = { (wb_adr_i[1] & wb_sel_i[1]), (wb_adr_i[1] & wb_sel_i[0]), + (~wb_adr_i[1] & wb_sel_i[1]), (~wb_adr_i[1] & wb_sel_i[0]) }; + + + spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]), + .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(new_sels), .lsb(lsb), + .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), + .rx_negedge(rx_negedge), .tx_negedge(tx_negedge), + .tip(tip), .last(last_bit), + .p_in({wb_dat_i,wb_dat_i}), .p_out(rx), + .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o)); + +endmodule // spi_top16 diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v b/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v deleted file mode 100644 index 60d4ecbd1..000000000 --- a/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v +++ /dev/null @@ -1,2 +0,0 @@ -`timescale 1ns / 10ps - diff --git a/fpga/usrp2/timing/time_compare.v b/fpga/usrp2/timing/time_compare.v index a21c9f8e0..cb2b6d860 100644 --- a/fpga/usrp2/timing/time_compare.v +++ b/fpga/usrp2/timing/time_compare.v @@ -14,10 +14,34 @@ module time_compare wire tick_match = (time_now[31:0] == trigger_time[31:0]); wire tick_late = (time_now[31:0] > trigger_time[31:0]); - +/* assign now = sec_match & tick_match; assign late = sec_late | (sec_match & tick_late); assign early = ~now & ~late; +*/ + + /* + assign now = (time_now == trigger_time); + assign late = (time_now > trigger_time); + assign early = (time_now < trigger_time); + */ + + // Compare fewer bits instead of 64 to speed up logic + // Unused bits are not significant + // Top bit of seconds would put us in year 2038, long after + // the warranty has run out :) + // Top 5 bits of ticks are always zero for clocks less than 134MHz + // "late" can drop bottom few bits of ticks, and just delay signaling + // of late. + // "now" cannot drop those bits, it needs to be exact. + + wire [57:0] short_now = {time_now[62:32],time_now[26:0]}; + wire [57:0] short_trig = {trigger_time[62:32],trigger_time[26:0]}; + + assign now = (short_now == short_trig); + assign late = (short_now[57:5] > short_trig[57:5]); + assign early = (short_now < short_trig); + assign too_early = (trigger_time[63:32] > (time_now[63:32] + 4)); // Don't wait too long endmodule // time_compare diff --git a/fpga/usrp2/top/.gitignore b/fpga/usrp2/top/.gitignore index bf1b77066..0d90f1698 100644 --- a/fpga/usrp2/top/.gitignore +++ b/fpga/usrp2/top/.gitignore @@ -1 +1,2 @@ /*.sav +build* diff --git a/fpga/usrp2/top/Makefile.common b/fpga/usrp2/top/Makefile.common index 9a180d10e..6f855a070 100644 --- a/fpga/usrp2/top/Makefile.common +++ b/fpga/usrp2/top/Makefile.common @@ -13,8 +13,10 @@ else endif BASE_DIR = $(abspath ..) ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl +SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT) BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin +BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs ################################################## @@ -25,12 +27,13 @@ all: bin proj: $(ISE_FILE) check: $(ISE_FILE) + $(SANITY_CHECKER) $(TOP_MODULE).v $(TOP_MODULE).ucf $(ISE_HELPER) "Check Syntax" synth: $(ISE_FILE) $(ISE_HELPER) "Synthesize - XST" -bin: $(BIN_FILE) +bin: check $(BIN_FILE) $(ISE_HELPER) "Generate Programming File" mcs: $(MCS_FILE) @@ -54,6 +57,6 @@ $(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST) touch $@ $(MCS_FILE): $(BIN_FILE) - promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIN_FILE) + promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIT_FILE) .EXPORT_ALL_VARIABLES: diff --git a/fpga/usrp2/top/python/check_inout.py b/fpga/usrp2/top/python/check_inout.py new file mode 100755 index 000000000..ff371d378 --- /dev/null +++ b/fpga/usrp2/top/python/check_inout.py @@ -0,0 +1,62 @@ +#!/usr/bin/env python +# +# Copyright 2010 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +# Description: +# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf. +# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes + +import sys +import re + +if __name__=='__main__': + if len(sys.argv) == 2: + print "Usage: %s <top level Verilog file> <pin definition UCF>" + sys.exit(-1) + + verilog_filename = sys.argv[1] + ucf_filename = sys.argv[2] + + verilog_file = open(verilog_filename, 'r') + ucf_file = open(ucf_filename, 'r') + + verilog_iolist = list() + ucf_iolist = list() + + #read in all input, inout, and output declarations and compile a list + for line in verilog_file: + for match in re.findall(r"(?:input|inout|output) (?:reg )*(?:\[.*\] )*(\w+)", line.split("//")[0]): + verilog_iolist.append(match) + + for line in ucf_file: + m = re.search(r"""NET "(\w+).*" """, line.split("#")[0]) + if m is not None: + ucf_iolist.append(m.group(1)) + + #now find corresponding matches and error when you don't find one + #we search for .v defs without matching .ucf defs since the reverse isn't necessarily a problem + err = False + + for item in verilog_iolist: + if item not in ucf_iolist: + print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item + err = True + + if err: + sys.exit(-1) + + print "No errors found." + sys.exit(0) diff --git a/fpga/usrp2/top/safe_u2plus/.gitignore b/fpga/usrp2/top/safe_u2plus/.gitignore new file mode 100644 index 000000000..a96f0be92 --- /dev/null +++ b/fpga/usrp2/top/safe_u2plus/.gitignore @@ -0,0 +1,2 @@ +build* +*impact* diff --git a/fpga/usrp2/top/safe_u2plus/Makefile b/fpga/usrp2/top/safe_u2plus/Makefile new file mode 100644 index 000000000..62a02ff40 --- /dev/null +++ b/fpga/usrp2/top/safe_u2plus/Makefile @@ -0,0 +1,246 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := safe_u2plus +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ +simple_gemac/address_filter.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +simple_gemac/miim/eth_miim.v \ +simple_gemac/miim/eth_clockgen.v \ +simple_gemac/miim/eth_outputcontrol.v \ +simple_gemac/miim/eth_shiftreg.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/u2plus/capture_ddrlvds.v \ +top/safe_u2plus/u2plus.ucf \ +top/safe_u2plus/safe_u2plus.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/fpga/usrp2/top/safe_u2plus/safe_u2plus.v b/fpga/usrp2/top/safe_u2plus/safe_u2plus.v new file mode 100644 index 000000000..dca9688c5 --- /dev/null +++ b/fpga/usrp2/top/safe_u2plus/safe_u2plus.v @@ -0,0 +1,23 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module safe_u2plus + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [5:1] leds, // LED4 is shared w/INIT_B + output ETH_LED + ); + + wire clk_fpga; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + reg [31:0] ctr; + + always @(posedge clk_fpga) + ctr <= ctr + 1; + + assign {leds,ETH_LED} = ~ctr[29:24]; + +endmodule // safe_u2plus diff --git a/fpga/usrp2/top/safe_u2plus/u2plus.ucf b/fpga/usrp2/top/safe_u2plus/u2plus.ucf new file mode 100755 index 000000000..0a9460d86 --- /dev/null +++ b/fpga/usrp2/top/safe_u2plus/u2plus.ucf @@ -0,0 +1,401 @@ +## Main 100 MHz Clock +NET "CLK_FPGA_P" LOC = "AA13" ; +NET "CLK_FPGA_N" LOC = "Y13" ; + +## ADC +#NET "ADC_clkout_p" LOC = "P1" ; +#NET "ADC_clkout_n" LOC = "P2" ; +#NET "ADCA_12_p" LOC = "Y1" ; +#NET "ADCA_12_n" LOC = "Y2" ; +#NET "ADCA_10_p" LOC = "W3" ; +#NET "ADCA_10_n" LOC = "W4" ; +#NET "ADCA_8_p" LOC = "T7" ; +#NET "ADCA_8_n" LOC = "U6" ; +#NET "ADCA_6_p" LOC = "U5" ; +#NET "ADCA_6_n" LOC = "V5" ; +#NET "ADCA_4_p" LOC = "T10" ; +#NET "ADCA_4_n" LOC = "T9" ; +#NET "ADCA_2_p" LOC = "V1" ; +#NET "ADCA_2_n" LOC = "V2" ; +#NET "ADCA_0_p" LOC = "R8" ; +#NET "ADCA_0_n" LOC = "R7" ; +#NET "ADCB_2_p" LOC = "U7" ; +#NET "ADCB_2_n" LOC = "U8" ; +#NET "ADCB_0_p" LOC = "AA2" ; +#NET "ADCB_0_n" LOC = "AA3" ; +#NET "ADCB_4_p" LOC = "AE1" ; +#NET "ADCB_4_n" LOC = "AE2" ; +#NET "ADCB_6_p" LOC = "W1" ; +#NET "ADCB_6_n" LOC = "W2" ; +#NET "ADCB_8_p" LOC = "U3" ; +#NET "ADCB_8_n" LOC = "V4" ; +#NET "ADCB_10_p" LOC = "J1" ; +#NET "ADCB_10_n" LOC = "K1" ; +#NET "ADCB_12_p" LOC = "J3" ; +#NET "ADCB_12_n" LOC = "J2" ; + +## DAC +#NET "DAC_LOCK" LOC = "P4" ; +#NET "DACA<0>" LOC = "P8" ; +#NET "DACA<1>" LOC = "P9" ; +#NET "DACA<2>" LOC = "R5" ; +#NET "DACA<3>" LOC = "R6" ; +#NET "DACA<4>" LOC = "P7" ; +#NET "DACA<5>" LOC = "P6" ; +#NET "DACA<6>" LOC = "T3" ; +#NET "DACA<7>" LOC = "T4" ; +#NET "DACA<8>" LOC = "R3" ; +#NET "DACA<9>" LOC = "R4" ; +#NET "DACA<10>" LOC = "R2" ; +#NET "DACA<11>" LOC = "N1" ; +#NET "DACA<12>" LOC = "N2" ; +#NET "DACA<13>" LOC = "N5" ; +#NET "DACA<14>" LOC = "N4" ; +#NET "DACA<15>" LOC = "M2" ; +#NET "DACB<0>" LOC = "M5" ; +#NET "DACB<1>" LOC = "M6" ; +#NET "DACB<2>" LOC = "M4" ; +#NET "DACB<3>" LOC = "M3" ; +#NET "DACB<4>" LOC = "M8" ; +#NET "DACB<5>" LOC = "M7" ; +#NET "DACB<6>" LOC = "L4" ; +#NET "DACB<7>" LOC = "L3" ; +#NET "DACB<8>" LOC = "K3" ; +#NET "DACB<9>" LOC = "K2" ; +#NET "DACB<10>" LOC = "K5" ; +#NET "DACB<11>" LOC = "K4" ; +#NET "DACB<12>" LOC = "M10" ; +#NET "DACB<13>" LOC = "M9" ; +#NET "DACB<14>" LOC = "J5" ; +#NET "DACB<15>" LOC = "J4" ; + +## TX DB GPIO +#NET "io_tx<15>" LOC = "K6" ; +#NET "io_tx<14>" LOC = "L7" ; +#NET "io_tx<13>" LOC = "H2" ; +#NET "io_tx<12>" LOC = "H1" ; +#NET "io_tx<11>" LOC = "L10" ; +#NET "io_tx<10>" LOC = "L9" ; +#NET "io_tx<9>" LOC = "G3" ; +#NET "io_tx<8>" LOC = "F3" ; +#NET "io_tx<7>" LOC = "K7" ; +#NET "io_tx<6>" LOC = "J6" ; +#NET "io_tx<5>" LOC = "E1" ; +#NET "io_tx<4>" LOC = "F2" ; +#NET "io_tx<3>" LOC = "J7" ; +#NET "io_tx<2>" LOC = "H6" ; +#NET "io_tx<1>" LOC = "F5" ; +#NET "io_tx<0>" LOC = "G4" ; + +## RX DB GPIO +#NET "io_rx<15>" LOC = "AD1" ; +#NET "io_rx<14>" LOC = "AD2" ; +#NET "io_rx<13>" LOC = "AC2" ; +#NET "io_rx<12>" LOC = "AC3" ; +#NET "io_rx<11>" LOC = "W7" ; +#NET "io_rx<10>" LOC = "W6" ; +#NET "io_rx<9>" LOC = "U9" ; +#NET "io_rx<8>" LOC = "V8" ; +#NET "io_rx<7>" LOC = "AB1" ; +#NET "io_rx<6>" LOC = "AC1" ; +#NET "io_rx<5>" LOC = "V7" ; +#NET "io_rx<4>" LOC = "V6" ; +#NET "io_rx<3>" LOC = "Y5" ; +#NET "io_rx<2>" LOC = "R10" ; +#NET "io_rx<1>" LOC = "R1" ; +#NET "io_rx<0>" LOC = "M1" ; + +## MISC +NET "leds<5>" LOC = "AF25" ; +NET "leds<4>" LOC = "AE25" ; +NET "leds<3>" LOC = "AF23" ; +NET "leds<2>" LOC = "AE23" ; +NET "leds<1>" LOC = "AB18" ; +#NET "FPGA_RESET" LOC = "K24" ; + +## Debug +#NET "debug_clk<0>" LOC = "AA10" ; +#NET "debug_clk<1>" LOC = "AD11" ; +#NET "debug<0>" LOC = "AC19" ; +#NET "debug<1>" LOC = "AF20" ; +#NET "debug<2>" LOC = "AE20" ; +#NET "debug<3>" LOC = "AC16" ; +#NET "debug<4>" LOC = "AB16" ; +#NET "debug<5>" LOC = "AF19" ; +#NET "debug<6>" LOC = "AE19" ; +#NET "debug<7>" LOC = "V15" ; +#NET "debug<8>" LOC = "U15" ; +#NET "debug<9>" LOC = "AE17" ; +#NET "debug<10>" LOC = "AD17" ; +#NET "debug<11>" LOC = "V14" ; +#NET "debug<12>" LOC = "W15" ; +#NET "debug<13>" LOC = "AC15" ; +#NET "debug<14>" LOC = "AD14" ; +#NET "debug<15>" LOC = "AC14" ; +#NET "debug<16>" LOC = "AC11" ; +#NET "debug<17>" LOC = "AB12" ; +#NET "debug<18>" LOC = "AC12" ; +#NET "debug<19>" LOC = "V13" ; +#NET "debug<20>" LOC = "W13" ; +#NET "debug<21>" LOC = "AE8" ; +#NET "debug<22>" LOC = "AF8" ; +#NET "debug<23>" LOC = "V12" ; +#NET "debug<24>" LOC = "W12" ; +#NET "debug<25>" LOC = "AB9" ; +#NET "debug<26>" LOC = "AC9" ; +#NET "debug<27>" LOC = "AC8" ; +#NET "debug<28>" LOC = "AB7" ; +#NET "debug<29>" LOC = "V11" ; +#NET "debug<30>" LOC = "U11" ; +#NET "debug<31>" LOC = "Y10" ; + +## UARTS +#NET "TXD<3>" LOC = "AD20" ; +#NET "TXD<2>" LOC = "AC20" ; +#NET "TXD<1>" LOC = "AD19" ; +#NET "RXD<3>" LOC = "AF17" ; +#NET "RXD<2>" LOC = "AF15" ; +#NET "RXD<1>" LOC = "AD12" ; + +## AD9510 +#NET "CLK_STATUS" LOC = "AD22" ; +#NET "CLK_FUNC" LOC = "AC21" ; +#NET "clk_sel<0>" LOC = "AE21" ; +#NET "clk_sel<1>" LOC = "AD21" ; +#NET "clk_en<1>" LOC = "AA17" ; +#NET "clk_en<0>" LOC = "Y17" ; + +## I2C +#NET "SDA" LOC = "V16" ; +#NET "SCL" LOC = "U16" ; + +## Timing +#NET "PPS_IN" LOC = "AB6" ; +#NET "PPS2_IN" LOC = "AA20" ; + +## SPI +#NET "SEN_CLK" LOC = "AA18" ; +#NET "MOSI_CLK" LOC = "W17" ; +#NET "SCLK_CLK" LOC = "V17" ; +#NET "MISO_CLK" LOC = "AC10" ; + +#NET "SEN_DAC" LOC = "AE7" ; +#NET "SCLK_DAC" LOC = "AF5" ; +#NET "MOSI_DAC" LOC = "AE6" ; +#NET "MISO_DAC" LOC = "Y3" ; + +#NET "SCLK_ADC" LOC = "B1" ; +#NET "MOSI_ADC" LOC = "J8" ; +#NET "SEN_ADC" LOC = "J9" ; + +#NET "MOSI_TX_ADC" LOC = "V10" ; +#NET "SEN_TX_ADC" LOC = "W10" ; +#NET "SCLK_TX_ADC" LOC = "AC6" ; +#NET "MISO_TX_ADC" LOC = "G1" ; + +#NET "MOSI_TX_DAC" LOC = "AD6" ; +#NET "SEN_TX_DAC" LOC = "AE4" ; +#NET "SCLK_TX_DAC" LOC = "AF4" ; + +#NET "SCLK_TX_DB" LOC = "AE3" ; +#NET "MOSI_TX_DB" LOC = "AF3" ; +#NET "SEN_TX_DB" LOC = "W9" ; +#NET "MISO_TX_DB" LOC = "AA5" ; + +#NET "MOSI_RX_ADC" LOC = "E3" ; +#NET "SCLK_RX_ADC" LOC = "F4" ; +#NET "SEN_RX_ADC" LOC = "D3" ; +#NET "MISO_RX_ADC" LOC = "C1" ; + +#NET "SCLK_RX_DAC" LOC = "E4" ; +#NET "SEN_RX_DAC" LOC = "K9" ; +#NET "MOSI_RX_DAC" LOC = "K8" ; + +#NET "SCLK_RX_DB" LOC = "G6" ; +#NET "MOSI_RX_DB" LOC = "H7" ; +#NET "SEN_RX_DB" LOC = "B2" ; +#NET "MISO_RX_DB" LOC = "H4" ; + +## ETH PHY +#NET "CLK_TO_MAC" LOC = "P26" ; + +#NET "GMII_TXD<7>" LOC = "G21" ; +#NET "GMII_TXD<6>" LOC = "C26" ; +#NET "GMII_TXD<5>" LOC = "C25" ; +#NET "GMII_TXD<4>" LOC = "J21" ; +#NET "GMII_TXD<3>" LOC = "H21" ; +#NET "GMII_TXD<2>" LOC = "D25" ; +#NET "GMII_TXD<1>" LOC = "D24" ; +#NET "GMII_TXD<0>" LOC = "E26" ; +#NET "GMII_TX_EN" LOC = "D26" ; +#NET "GMII_TX_ER" LOC = "J19" ; +#NET "GMII_GTX_CLK" LOC = "J20" ; +#NET "GMII_TX_CLK" LOC = "P25" ; + +#NET "GMII_RX_CLK" LOC = "P21" ; +#NET "GMII_RXD<7>" LOC = "G22" ; +#NET "GMII_RXD<6>" LOC = "K19" ; +#NET "GMII_RXD<5>" LOC = "K18" ; +#NET "GMII_RXD<4>" LOC = "E24" ; +#NET "GMII_RXD<3>" LOC = "F23" ; +#NET "GMII_RXD<2>" LOC = "L18" ; +#NET "GMII_RXD<1>" LOC = "L17" ; +#NET "GMII_RXD<0>" LOC = "F25" ; +#NET "GMII_RX_DV" LOC = "F24" ; +#NET "GMII_RX_ER" LOC = "L20" ; +#NET "GMII_CRS" LOC = "K20" ; +#NET "GMII_COL" LOC = "G23" ; + +#NET "PHY_INTn" LOC = "L22" ; +#NET "MDIO" LOC = "K21" ; +#NET "MDC" LOC = "J23" ; +#NET "PHY_RESETn" LOC = "J22" ; +NET "ETH_LED" LOC = "H20" ; + +## MIMO Interface +#NET "exp_time_out_p" LOC = "Y14" ; +#NET "exp_time_out_n" LOC = "AA14" ; +#NET "exp_time_in_p" LOC = "N18" ; +#NET "exp_time_in_n" LOC = "N17" ; +#NET "exp_user_out_p" LOC = "AF14" ; +#NET "exp_user_out_n" LOC = "AE14" ; +#NET "exp_user_in_p" LOC = "L24" ; +#NET "exp_user_in_n" LOC = "M23" ; + +## SERDES +#NET "ser_enable" LOC = "R20" ; +#NET "ser_prbsen" LOC = "U23" ; +#NET "ser_loopen" LOC = "R19" ; +#NET "ser_rx_en" LOC = "Y21" ; +#NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK +#NET "ser_t<15>" LOC = "V23" ; +#NET "ser_t<14>" LOC = "U22" ; +#NET "ser_t<13>" LOC = "V24" ; +#NET "ser_t<12>" LOC = "V25" ; +#NET "ser_t<11>" LOC = "W23" ; +#NET "ser_t<10>" LOC = "V22" ; +#NET "ser_t<9>" LOC = "T18" ; +#NET "ser_t<8>" LOC = "T17" ; +#NET "ser_t<7>" LOC = "Y24" ; +#NET "ser_t<6>" LOC = "Y25" ; +#NET "ser_t<5>" LOC = "U21" ; +#NET "ser_t<4>" LOC = "T20" ; +#NET "ser_t<3>" LOC = "Y22" ; +#NET "ser_t<2>" LOC = "Y23" ; +#NET "ser_t<1>" LOC = "U19" ; +#NET "ser_t<0>" LOC = "U18" ; +#NET "ser_tkmsb" LOC = "AA24" ; +#NET "ser_tklsb" LOC = "AA25" ; +#NET "ser_rx_clk" LOC = "P18" ; +#NET "ser_r<15>" LOC = "V21" ; +#NET "ser_r<14>" LOC = "U20" ; +#NET "ser_r<13>" LOC = "AA22" ; +#NET "ser_r<12>" LOC = "AA23" ; +#NET "ser_r<11>" LOC = "V18" ; +#NET "ser_r<10>" LOC = "V19" ; +#NET "ser_r<9>" LOC = "AB23" ; +#NET "ser_r<8>" LOC = "AC26" ; +#NET "ser_r<7>" LOC = "AB26" ; +#NET "ser_r<6>" LOC = "AD26" ; +#NET "ser_r<5>" LOC = "AC25" ; +#NET "ser_r<4>" LOC = "W20" ; +#NET "ser_r<3>" LOC = "W21" ; +#NET "ser_r<2>" LOC = "AC23" ; +#NET "ser_r<1>" LOC = "AC24" ; +#NET "ser_r<0>" LOC = "AE26" ; +#NET "ser_rkmsb" LOC = "AD25" ; +#NET "ser_rklsb" LOC = "Y20" ; + +## SRAM +#NET "RAM_D<35>" LOC = "K16" ; +#NET "RAM_D<34>" LOC = "D20" ; +#NET "RAM_D<33>" LOC = "C20" ; +#NET "RAM_D<32>" LOC = "E21" ; +#NET "RAM_D<31>" LOC = "D21" ; +#NET "RAM_D<30>" LOC = "C21" ; +#NET "RAM_D<29>" LOC = "B21" ; +#NET "RAM_D<28>" LOC = "H17" ; +#NET "RAM_D<27>" LOC = "G17" ; +#NET "RAM_D<26>" LOC = "B23" ; +#NET "RAM_D<25>" LOC = "A22" ; +#NET "RAM_D<24>" LOC = "D23" ; +#NET "RAM_D<23>" LOC = "C23" ; +#NET "RAM_D<22>" LOC = "D22" ; +#NET "RAM_D<21>" LOC = "C22" ; +#NET "RAM_D<20>" LOC = "F19" ; +#NET "RAM_D<19>" LOC = "G20" ; +#NET "RAM_D<18>" LOC = "F20" ; +#NET "RAM_D<17>" LOC = "F7" ; +#NET "RAM_D<16>" LOC = "E7" ; +#NET "RAM_D<15>" LOC = "G9" ; +#NET "RAM_D<14>" LOC = "H9" ; +#NET "RAM_D<13>" LOC = "G10" ; +#NET "RAM_D<12>" LOC = "H10" ; +#NET "RAM_D<11>" LOC = "A4" ; +#NET "RAM_D<10>" LOC = "B4" ; +#NET "RAM_D<9>" LOC = "C5" ; +#NET "RAM_D<8>" LOC = "D6" ; +#NET "RAM_D<7>" LOC = "J11" ; +#NET "RAM_D<6>" LOC = "K11" ; +#NET "RAM_D<5>" LOC = "B7" ; +#NET "RAM_D<4>" LOC = "C7" ; +#NET "RAM_D<3>" LOC = "B6" ; +#NET "RAM_D<2>" LOC = "C6" ; +#NET "RAM_D<1>" LOC = "C8" ; +#NET "RAM_D<0>" LOC = "D8" ; +#NET "RAM_A<0>" LOC = "C11" ; +#NET "RAM_A<1>" LOC = "E12" ; +#NET "RAM_A<2>" LOC = "F12" ; +#NET "RAM_A<3>" LOC = "D13" ; +#NET "RAM_A<4>" LOC = "C12" ; +#NET "RAM_A<5>" LOC = "A12" ; +#NET "RAM_A<6>" LOC = "B12" ; +#NET "RAM_A<7>" LOC = "E14" ; +#NET "RAM_A<8>" LOC = "F14" ; +#NET "RAM_A<9>" LOC = "B15" ; +#NET "RAM_A<10>" LOC = "A15" ; +#NET "RAM_A<11>" LOC = "D16" ; +#NET "RAM_A<12>" LOC = "C15" ; +#NET "RAM_A<13>" LOC = "D17" ; +#NET "RAM_A<14>" LOC = "C16" ; +#NET "RAM_A<15>" LOC = "F15" ; +#NET "RAM_A<16>" LOC = "C17" ; +#NET "RAM_A<17>" LOC = "B17" ; +#NET "RAM_A<18>" LOC = "B18" ; +#NET "RAM_A<19>" LOC = "A18" ; +#NET "RAM_A<20>" LOC = "D18" ; +#NET "RAM_BWn<3>" LOC = "D9" ; +#NET "RAM_BWn<2>" LOC = "A9" ; +#NET "RAM_BWn<1>" LOC = "B9" ; +#NET "RAM_BWn<0>" LOC = "G12" ; +#NET "RAM_ZZ" LOC = "J12" ; +#NET "RAM_LDn" LOC = "H12" ; +#NET "RAM_OEn" LOC = "C10" ; +#NET "RAM_WEn" LOC = "D10" ; +#NET "RAM_CENn" LOC = "B10" ; +#NET "RAM_CLK" LOC = "A10" ; + +## SPI Flash +#NET "flash_miso" LOC = "AF24" ; +#NET "flash_clk" LOC = "AE24" ; +#NET "flash_mosi" LOC = "AB15" ; +#NET "flash_cs" LOC = "AA7" ; + +## MISC FPGA, unused for now +##NET "PROG_B" LOC = "A2" ; +##NET "PUDC_B" LOC = "G8" ; +##NET "DONE" LOC = "AB21" ; +##NET "INIT_B" LOC = "AA15" ; + + +##NET "unnamed_net19" LOC = "AE9" ; # VS1 +##NET "unnamed_net18" LOC = "AF9" ; # VS0 +##NET "unnamed_net17" LOC = "AA12" ; # VS2 +##NET "unnamed_net16" LOC = "Y7" ; # M2 +##NET "unnamed_net15" LOC = "AC4" ; # M1 +##NET "unnamed_net14" LOC = "AD4" ; # M0 +##NET "unnamed_net13" LOC = "D4" ; # TMS +##NET "unnamed_net12" LOC = "E23" ; # TDO +##NET "unnamed_net11" LOC = "G7" ; # TDI +##NET "unnamed_net10" LOC = "A25" ; # TCK +##NET "unnamed_net20" LOC = "V20" ; # SUSPEND diff --git a/fpga/usrp2/top/u1e/.gitignore b/fpga/usrp2/top/u1e/.gitignore new file mode 100644 index 000000000..8d872713e --- /dev/null +++ b/fpga/usrp2/top/u1e/.gitignore @@ -0,0 +1,6 @@ +*~ +build +*.log +*.cmd +tb_u1e +*.lxt diff --git a/fpga/usrp2/top/u1e/Makefile b/fpga/usrp2/top/u1e/Makefile new file mode 100644 index 000000000..3cb9fd8f3 --- /dev/null +++ b/fpga/usrp2/top/u1e/Makefile @@ -0,0 +1,101 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u1e +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs +include ../../gpmc/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u1e_core.v \ +u1e.v \ +u1e.ucf \ +timing.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPMC_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u1e/README b/fpga/usrp2/top/u1e/README new file mode 100644 index 000000000..14c7a4955 --- /dev/null +++ b/fpga/usrp2/top/u1e/README @@ -0,0 +1,4 @@ + +make clean +make sim +./tb_u1e -lxt2 diff --git a/fpga/usrp2/top/u1e/cmdfile b/fpga/usrp2/top/u1e/cmdfile new file mode 100644 index 000000000..291c723b8 --- /dev/null +++ b/fpga/usrp2/top/u1e/cmdfile @@ -0,0 +1,20 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims + +# Open Cores +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog + diff --git a/fpga/usrp2/top/u1e/make.sim b/fpga/usrp2/top/u1e/make.sim new file mode 100644 index 000000000..1c163884c --- /dev/null +++ b/fpga/usrp2/top/u1e/make.sim @@ -0,0 +1,7 @@ +all: sim + +sim: + iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e + +clean: + rm -f tb_u1e *.vcd *.lxt a.out diff --git a/fpga/usrp2/top/u1e/tb_u1e.v b/fpga/usrp2/top/u1e/tb_u1e.v new file mode 100644 index 000000000..5fc8134fb --- /dev/null +++ b/fpga/usrp2/top/u1e/tb_u1e.v @@ -0,0 +1,41 @@ +`timescale 1ps / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module tb_u1e(); + + wire [2:0] debug_led; + wire [31:0] debug; + wire [1:0] debug_clk; + + xlnx_glbl glbl (.GSR(),.GTS()); + + initial begin + $dumpfile("tb_u1e.lxt"); + $dumpvars(0,tb_u1e); + end + + // GPMC + wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; + wire [15:0] EM_D; + wire [10:1] EM_A; + wire [1:0] EM_NBE; + + reg clk_fpga = 0, rst_fpga = 1; + always #15625 clk_fpga = ~clk_fpga; + + initial #200000 + @(posedge clk_fpga) + rst_fpga <= 0; + + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + + gpmc_model_async gpmc_model_async + (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + +endmodule // tb_u1e diff --git a/fpga/usrp2/top/u1e/timing.ucf b/fpga/usrp2/top/u1e/timing.ucf new file mode 100644 index 000000000..8df28c9d3 --- /dev/null +++ b/fpga/usrp2/top/u1e/timing.ucf @@ -0,0 +1,13 @@ + +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + + + + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; diff --git a/fpga/usrp2/top/u1e/u1e.ucf b/fpga/usrp2/top/u1e/u1e.ucf new file mode 100644 index 000000000..0c487a601 --- /dev/null +++ b/fpga/usrp2/top/u1e/u1e.ucf @@ -0,0 +1,259 @@ + +NET "CLK_FPGA_P" LOC = "Y11" ; +NET "CLK_FPGA_N" LOC = "Y10" ; + +## GPMC +NET "EM_D<15>" LOC = "D13" ; +NET "EM_D<14>" LOC = "D15" ; +NET "EM_D<13>" LOC = "C16" ; +NET "EM_D<12>" LOC = "B20" ; +NET "EM_D<11>" LOC = "A19" ; +NET "EM_D<10>" LOC = "A17" ; +NET "EM_D<9>" LOC = "E15" ; +NET "EM_D<8>" LOC = "F15" ; +NET "EM_D<7>" LOC = "E16" ; +NET "EM_D<6>" LOC = "F16" ; +NET "EM_D<5>" LOC = "B17" ; +NET "EM_D<4>" LOC = "C17" ; +NET "EM_D<3>" LOC = "B19" ; +NET "EM_D<2>" LOC = "D19" ; +NET "EM_D<1>" LOC = "C19" ; +NET "EM_D<0>" LOC = "A20" ; + +NET "EM_A<10>" LOC = "C14" ; +NET "EM_A<9>" LOC = "C10" ; +NET "EM_A<8>" LOC = "C5" ; +NET "EM_A<7>" LOC = "A18" ; +NET "EM_A<6>" LOC = "A15" ; +NET "EM_A<5>" LOC = "A12" ; +NET "EM_A<4>" LOC = "A10" ; +NET "EM_A<3>" LOC = "E7" ; +NET "EM_A<2>" LOC = "A7" ; +NET "EM_A<1>" LOC = "C15" ; + +NET "EM_NCS6" LOC = "E17" ; +NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; + +NET "EM_CLK" LOC = "F11" ; +NET "EM_WAIT0" LOC = "F14" ; +NET "EM_NBE<1>" LOC = "D14" ; +NET "EM_NBE<0>" LOC = "A13" ; +NET "EM_NWE" LOC = "B13" ; +NET "EM_NOE" LOC = "A14" ; +#NET "EM_NADV_ALE" LOC = "B15" ; +#NET "EM_NWP" LOC = "F13" ; + +## Overo GPIO +NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug +NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug +NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug +NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug +NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug +NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug +NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug + +NET "overo_gpio127" LOC = "C8" ; # Changed name to gpio10 +NET "overo_gpio128" LOC = "G8" ; # Changed name to gpio186 + +NET "overo_gpio144" LOC = "A5" ; # tx_have_space +NET "overo_gpio145" LOC = "C7" ; # tx_underrun +NET "overo_gpio146" LOC = "A6" ; # rx_have_data +NET "overo_gpio147" LOC = "B6" ; # rx_overrun +NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug +NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug +NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug + +## Overo UART +#NET "overo_txd1" LOC = "C6" ; +#NET "overo_rxd1" LOC = "D6" ; + +## FTDI UART to USB converter +NET "FPGA_TXD" LOC = "G19" ; +NET "FPGA_RXD" LOC = "F20" ; + +#NET "SYSEN" LOC = "C11" ; + +## I2C +NET "db_scl" LOC = "F19" ; +NET "db_sda" LOC = "F18" ; + +## SPI +### DBoard SPI +NET "db_sclk_rx" LOC = "D21" ; +NET "db_miso_rx" LOC = "D22" ; +NET "db_mosi_rx" LOC = "D20" ; +NET "db_sen_rx" LOC = "E19" ; +NET "db_sclk_tx" LOC = "F21" ; +NET "db_miso_tx" LOC = "E20" ; +NET "db_mosi_tx" LOC = "G17" ; +NET "db_sen_tx" LOC = "G18" ; + +### AD9862 SPI and aux SPI Interfaces +#NET "aux_sdi_codec" LOC = "G3" ; +#NET "aux_sdo_codec" LOC = "F3" ; +#NET "aux_sclk_codec" LOC = "C1" ; +NET "sen_codec" LOC = "F5" |IOSTANDARD = LVCMOS33; +NET "mosi_codec" LOC = "F4" |IOSTANDARD = LVCMOS33; +NET "miso_codec" LOC = "H4" ; +NET "sclk_codec" LOC = "H3" |IOSTANDARD = LVCMOS33; + +### Clock Gen SPI +NET "cgen_miso" LOC = "F22" ; +NET "cgen_mosi" LOC = "E22" ; +NET "cgen_sclk" LOC = "J19" ; +NET "cgen_sen_b" LOC = "H20" ; + +## Clock gen control +NET "cgen_st_status" LOC = "P20" ; +NET "cgen_st_ld" LOC = "R17" ; +NET "cgen_st_refmon" LOC = "P17" ; +NET "cgen_sync_b" LOC = "U18" ; +NET "cgen_ref_sel" LOC = "U19" ; + +## Debug pins +NET "debug_led<3>" LOC = "Y15" ; +NET "debug_led<2>" LOC = "K16" ; +NET "debug_led<1>" LOC = "J17" ; +NET "debug_led<0>" LOC = "H22" ; +NET "debug<0>" LOC = "G22" ; +NET "debug<1>" LOC = "H17" ; +NET "debug<2>" LOC = "H18" ; +NET "debug<3>" LOC = "K20" ; +NET "debug<4>" LOC = "J20" ; +NET "debug<5>" LOC = "K19" ; +NET "debug<6>" LOC = "K18" ; +NET "debug<7>" LOC = "L22" ; +NET "debug<8>" LOC = "K22" ; +NET "debug<9>" LOC = "N22" ; +NET "debug<10>" LOC = "M22" ; +NET "debug<11>" LOC = "N20" ; +NET "debug<12>" LOC = "N19" ; +NET "debug<13>" LOC = "R22" ; +NET "debug<14>" LOC = "P22" ; +NET "debug<15>" LOC = "N17" ; +NET "debug<16>" LOC = "P16" ; +NET "debug<17>" LOC = "U22" ; +NET "debug<18>" LOC = "P19" ; +NET "debug<19>" LOC = "R18" ; +NET "debug<20>" LOC = "U20" ; +NET "debug<21>" LOC = "T20" ; +NET "debug<22>" LOC = "R19" ; +NET "debug<23>" LOC = "R20" ; +NET "debug<24>" LOC = "W22" ; +NET "debug<25>" LOC = "Y22" ; +NET "debug<26>" LOC = "T18" ; +NET "debug<27>" LOC = "T17" ; +NET "debug<28>" LOC = "W19" ; +NET "debug<29>" LOC = "V20" ; +NET "debug<30>" LOC = "Y21" ; +NET "debug<31>" LOC = "AA22" ; +NET "debug_clk<0>" LOC = "N18" ; +NET "debug_clk<1>" LOC = "M17" ; + +NET "debug_pb" LOC = "C22" ; + +#NET "reset_codec" LOC = "C2" ; + +NET "RXSYNC" LOC = "F2" ; +NET "DB<11>" LOC = "G6" ; +NET "DB<10>" LOC = "G5" ; +NET "DB<9>" LOC = "E4" ; +NET "DB<8>" LOC = "E3" ; +NET "DB<7>" LOC = "H6" ; +NET "DB<6>" LOC = "H5" ; +NET "DB<5>" LOC = "H1" ; +NET "DB<4>" LOC = "G1" ; +NET "DB<3>" LOC = "K5" ; +NET "DB<2>" LOC = "K4" ; +NET "DB<1>" LOC = "H2" ; +NET "DB<0>" LOC = "L5" ; + +NET "DA<11>" LOC = "K6" ; +NET "DA<10>" LOC = "K3" ; +NET "DA<9>" LOC = "K2" ; +NET "DA<8>" LOC = "N1" ; +NET "DA<7>" LOC = "N5" ; +NET "DA<6>" LOC = "N6" ; +NET "DA<5>" LOC = "P2" ; +NET "DA<4>" LOC = "P1" ; +NET "DA<3>" LOC = "R6" ; +NET "DA<2>" LOC = "P6" ; +NET "DA<1>" LOC = "R1" ; +NET "DA<0>" LOC = "R2" ; + +NET "TX<13>" LOC = "T6" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<12>" LOC = "U1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<11>" LOC = "T1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<10>" LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<9>" LOC = "V1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<8>" LOC = "U2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<7>" LOC = "T4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<6>" LOC = "R3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<5>" LOC = "W1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<4>" LOC = "Y1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<3>" LOC = "V3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<2>" LOC = "V4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<1>" LOC = "W2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<0>" LOC = "W3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXSYNC" LOC = "U5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXBLANK" LOC = "U4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; + +NET "PPS_IN" LOC = "M5" ; + +NET "io_tx<0>" LOC = "AB20" ; +NET "io_tx<1>" LOC = "Y17" ; +NET "io_tx<2>" LOC = "Y16" ; +NET "io_tx<3>" LOC = "U16" ; +NET "io_tx<4>" LOC = "V16" ; +NET "io_tx<5>" LOC = "AB19" ; +NET "io_tx<6>" LOC = "AA19" ; +NET "io_tx<7>" LOC = "U14" ; +NET "io_tx<8>" LOC = "U15" ; +NET "io_tx<9>" LOC = "AB17" ; +NET "io_tx<10>" LOC = "AB18" ; +NET "io_tx<11>" LOC = "Y13" ; +NET "io_tx<12>" LOC = "W14" ; +NET "io_tx<13>" LOC = "U13" ; +NET "io_tx<14>" LOC = "AA15" ; +NET "io_tx<15>" LOC = "AB14" ; + +NET "io_rx<0>" LOC = "Y8" ; +NET "io_rx<1>" LOC = "Y9" ; +NET "io_rx<2>" LOC = "V7" ; +NET "io_rx<3>" LOC = "U8" ; +NET "io_rx<4>" LOC = "V10" ; +NET "io_rx<5>" LOC = "U9" ; +NET "io_rx<6>" LOC = "AB7" ; +NET "io_rx<7>" LOC = "AA8" ; +NET "io_rx<8>" LOC = "W8" ; +NET "io_rx<9>" LOC = "V8" ; +NET "io_rx<10>" LOC = "AB5" ; +NET "io_rx<11>" LOC = "AB6" ; +NET "io_rx<12>" LOC = "AB4" ; +NET "io_rx<13>" LOC = "AA4" ; +NET "io_rx<14>" LOC = "W5" ; +NET "io_rx<15>" LOC = "Y4" ; + +#NET "CLKOUT2_CODEC" LOC = "U12" ; +#NET "CLKOUT1_CODEC" LOC = "V12" ; + +## FPGA Config Pins +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "AB21" ; +#NET "fpga_cfg_din" LOC = "W17" ; +#NET "fpga_cfg_cclk" LOC = "V17" ; +#NET "fpga_cfg_init_b" LOC = "W15" ; + +## Unused +#NET "unnamed_net53" LOC = "B1" ; # TMS +#NET "unnamed_net52" LOC = "B22" ; # TDO +#NET "unnamed_net51" LOC = "D2" ; # TDI +#NET "unnamed_net50" LOC = "A21" ; # TCK +#NET "unnamed_net59" LOC = "F7" ; # PUDC_B +#NET "unnamed_net58" LOC = "V6" ; # M2 +#NET "unnamed_net57" LOC = "AA3" ; # M1 +#NET "unnamed_net56" LOC = "AB3" ; # M0 +#NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/fpga/usrp2/top/u1e/u1e.v b/fpga/usrp2/top/u1e/u1e.v new file mode 100644 index 000000000..445b14a03 --- /dev/null +++ b/fpga/usrp2/top/u1e/u1e.v @@ -0,0 +1,141 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u1e + (input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input debug_pb, output FPGA_TXD, input FPGA_RXD, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, + + inout db_sda, inout db_scl, // I2C + + output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx, // DB TX SPI + output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI + output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI + output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + + output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls + input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO + input overo_gpio23, input overo_gpio64, input overo_gpio65, input overo_gpio127, // Misc GPIO + input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO + + inout [15:0] io_tx, inout [15:0] io_rx, + + output [13:0] TX, output TXSYNC, output TXBLANK, + input [11:0] DA, input [11:0] DB, input RXSYNC, + + input PPS_IN + ); + + // ///////////////////////////////////////////////////////////////////////// + // Clocking + wire clk_fpga, clk_fpga_in; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + wire clk_2x, dcm_rst, dcm_locked, clk_fb; + DCM #(.CLK_FEEDBACK ( "1X" ), + .CLKDV_DIVIDE ( 2 ), + .CLKFX_DIVIDE ( 2 ), + .CLKFX_MULTIPLY ( 2 ), + .CLKIN_DIVIDE_BY_2 ( "FALSE" ), + .CLKIN_PERIOD ( 15.625 ), + .CLKOUT_PHASE_SHIFT ( "NONE" ), + .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ), + .DFS_FREQUENCY_MODE ( "LOW" ), + .DLL_FREQUENCY_MODE ( "LOW" ), + .DUTY_CYCLE_CORRECTION ( "TRUE" ), + .FACTORY_JF ( 16'h8080 ), + .PHASE_SHIFT ( 0 ), + .STARTUP_WAIT ( "FALSE" )) + clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), + .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), + .CLKDV(), .CLKFX(), .CLKFX180(), + .CLK2X(), .CLK2X180(), + .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), + .LOCKED(dcm_locked), .STATUS()); + + // ///////////////////////////////////////////////////////////////////////// + // SPI + wire mosi, sclk, miso; + assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; + assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; + assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0; + assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; + assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | + (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + + // ///////////////////////////////////////////////////////////////////////// + // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL + + assign TXBLANK = 0; + wire [13:0] tx_i, tx_q; + + reg[13:0] delay_q; + always @(posedge clk_fpga) + delay_q <= tx_q; + + genvar i; + generate + for(i=0;i<14;i=i+1) + begin : gen_dacout + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_inst (.Q(TX[i]), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(tx_i[i]), // 1-bit data input (associated with C0) + .D1(delay_q[i]), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_dacout + endgenerate + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + + // ///////////////////////////////////////////////////////////////////////// + // Main U1E Core + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), + .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .db_sda(db_sda), .db_scl(db_scl), + .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), + .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), + .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), + .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), + .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), + .io_tx(io_tx), .io_rx(io_rx), + .tx_i(tx_i), .tx_q(tx_q), + .rx_i(DA), .rx_q(DB), + .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, + {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, + {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), + .pps_in(PPS_IN) ); + + // ///////////////////////////////////////////////////////////////////////// + // Local Debug + // assign debug_clk = {clk_fpga, clk_2x }; + // assign debug = { TXSYNC, TXBLANK, TX }; + +endmodule // u1e diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v new file mode 100644 index 000000000..e7e798b34 --- /dev/null +++ b/fpga/usrp2/top/u1e/u1e_core.v @@ -0,0 +1,459 @@ + + +//`define LOOPBACK 1 +//`define TIMED 1 +`define DSP 1 + +module u1e_core + (input clk_fpga, input rst_fpga, + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output debug_txd, input debug_rxd, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, + + inout db_sda, inout db_scl, + output sclk, output [7:0] sen, output mosi, input miso, + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, + inout [15:0] io_tx, inout [15:0] io_rx, + output [13:0] tx_i, output [13:0] tx_q, + input [11:0] rx_i, input [11:0] rx_q, + + input [11:0] misc_gpio, input pps_in + ); + + localparam TXFIFOSIZE = 13; + localparam RXFIFOSIZE = 13; + + localparam SR_RX_DSP = 0; // 5 regs + localparam SR_CLEAR_FIFO = 6; // 1 reg + localparam SR_RX_CTRL = 8; // 9 regs + localparam SR_TX_DSP = 17; // 5 regs + localparam SR_TX_CTRL = 24; // 2 regs + localparam SR_TIME64 = 28; // 4 regs + + wire [7:0] COMPAT_NUM = 8'd2; + + wire wb_clk = clk_fpga; + wire wb_rst = rst_fpga; + + wire pps_int; + wire [63:0] vita_time; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire [31:0] debug_vt; + + // ///////////////////////////////////////////////////////////////////////////////////// + // GPMC Slave to Wishbone Master + localparam dw = 16; + localparam aw = 11; + localparam sw = 2; + + wire [dw-1:0] m0_dat_mosi, m0_dat_miso; + wire [aw-1:0] m0_adr; + wire [sw-1:0] m0_sel; + wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; + + wire [31:0] debug_gpmc; + + wire [35:0] tx_data, rx_data, tx_err_data; + wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, + tx_err_src_rdy, tx_err_dst_rdy; + reg [15:0] tx_frame_len; + wire [15:0] rx_frame_len; + wire [7:0] rate; + + wire bus_error; + + wire clear_rx_int, clear_tx_int, clear_tx, clear_rx, do_clear; + + setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(2)) sr_clear + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({clear_tx_int,clear_rx_int}),.changed(do_clear)); + assign clear_tx = clear_tx_int & do_clear; + assign clear_rx = clear_rx_int & do_clear; + + gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) + gpmc (.arst(wb_rst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), + .EM_NOE(EM_NOE), + + .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), + .bus_error(bus_error), .bus_reset(0), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack), + + .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), + + .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), + .debug(debug_gpmc)); + + wire rx_sof = rx_data[32]; + wire rx_eof = rx_data[33]; + wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; + +`ifdef LOOPBACK + wire [7:0] WHOAMI = 1; + + fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx), + .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + assign tx_underrun = 0; + assign rx_overrun = 0; + + wire run_tx, run_rx, strobe_tx, strobe_rx; +`endif // LOOPBACK + +`ifdef TIMED + wire [7:0] WHOAMI = 2; + + // TX side + wire tx_enable; + + fifo_pacer tx_pacer + (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable), + .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy), + .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int), + .underrun(tx_underrun), .overrun()); + + packet_verifier32 pktver32 + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), + .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + + // RX side + wire rx_enable; + + packet_generator32 pktgen32 + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int)); + + fifo_pacer rx_pacer + (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable), + .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int), + .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy), + .underrun(), .overrun(rx_overrun)); + +`endif // `ifdef TIMED + +`ifdef DSP + wire [7:0] WHOAMI = 0; + + wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + wire rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx1_data; + wire run_rx; + wire [35:0] vita_rx_data; + wire vita_rx_src_rdy, vita_rx_dst_rdy; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), .overrun(rx_overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), + .debug_rx(vrc_debug)); + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), + .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vrf_debug) ); + + fifo36_mux #(.prio(0)) mux_err_stream + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy), + .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [15:0] tx_i_int, tx_q_int; + wire run_tx; + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .PROT_ENG_FLAGS(0)) + vita_tx_chain + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(tx_i_int),.dac_b(tx_q_int), + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + + assign tx_i = tx_i_int[15:2]; + assign tx_q = tx_q_int[15:2]; + +`else // !`ifdef DSP + // Dummy DSP signal generator for test purposes + wire [23:0] tx_i_int, tx_q_int; + wire [23:0] freq = {reg_test,8'd0}; + reg [23:0] phase; + + always @(posedge wb_clk) + phase <= phase + freq; + + cordic_z24 #(.bitwidth(24)) tx_cordic + (.clock(wb_clk), .reset(wb_rst), .enable(1), + .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo()); + + assign tx_i = tx_i_int[23:10]; + assign tx_q = tx_q_int[23:10]; +`endif // !`ifdef DSP + + // ///////////////////////////////////////////////////////////////////////////////////// + // Wishbone Intercon, single master + wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, + s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso, + s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso, + sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso; + wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; + wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel; + wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack; + wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb; + wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc; + wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we; + wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we; + + wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4), + .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF), + .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), + .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), + .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), + .s8_addr(4'h8), .s8_mask(4'hF), .s9_addr(4'h9), .s9_mask(4'hF), + .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), + .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), + .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) + wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); + + assign s7_ack = 0; + assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; + assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 0, Misc LEDs, Switches, controls + + localparam REG_LEDS = 7'd0; // out + localparam REG_SWITCHES = 7'd2; // in + localparam REG_CGEN_CTRL = 7'd4; // out + localparam REG_CGEN_ST = 7'd6; // in + localparam REG_TEST = 7'd8; // out + localparam REG_RX_FRAMELEN = 7'd10; // in + localparam REG_TX_FRAMELEN = 7'd12; // out + localparam REG_XFER_RATE = 7'd14; // out + localparam REG_COMPAT = 7'd16; // in + + always @(posedge wb_clk) + if(wb_rst) + begin + reg_leds <= 0; + reg_cgen_ctrl <= 2'b11; + reg_test <= 0; + tx_frame_len <= 0; + xfer_rate <= 0; + end + else + if(s0_cyc & s0_stb & s0_we) + case(s0_adr[6:0]) + REG_LEDS : + reg_leds <= s0_dat_mosi; + REG_CGEN_CTRL : + reg_cgen_ctrl <= s0_dat_mosi; + REG_TEST : + reg_test <= s0_dat_mosi; + REG_TX_FRAMELEN : + tx_frame_len <= s0_dat_mosi; + REG_XFER_RATE : + xfer_rate <= s0_dat_mosi; + endcase // case (s0_adr[6:0]) + + assign tx_enable = xfer_rate[15]; + assign rx_enable = xfer_rate[14]; + assign rate = xfer_rate[7:0]; + + assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]}; + assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; + + assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : + (s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } : + (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : + (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : + (s0_adr[6:0] == REG_TEST) ? reg_test : + (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : + (s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } : + 16'hBEEF; + + assign s0_ack = s0_stb & s0_cyc; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 1, UART + // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), + .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), + .rx_int_o(),.tx_int_o(), + .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 2, SPI + + spi_top16 shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), + .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(), + .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // Slave 3, I2C + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; + i2c_master_top #(.ARST_LVL(1)) i2c + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_miso[15:8] = 8'd0; + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + + wire [31:0] atr_lines; + wire [31:0] debug_gpio_0, debug_gpio_1; + + nsgpio16LE + nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #5 + + // only have 32 regs, 32 bits each with current setup... + settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi), + .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data) ); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller -- Slave #6 + + atr_controller16 atr_controller16 + (.clk_i(wb_clk), .rst_i(wb_rst), + .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), + .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); + + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit + (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Debug circuitry + + assign debug_clk = { EM_CLK, clk_fpga }; + + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun }, + { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, + { EM_D } }; + + assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, + {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; + + assign debug_gpio_1 = debug_vt; + +/* + assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, + {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, + {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, + {2'b0, bus_error, debug_gpmc[4:0] }, + {misc_gpio[7:0]} }; + */ +endmodule // u1e_core diff --git a/fpga/usrp2/top/u1e_ethdebug/.gitignore b/fpga/usrp2/top/u1e_ethdebug/.gitignore new file mode 100644 index 000000000..8d872713e --- /dev/null +++ b/fpga/usrp2/top/u1e_ethdebug/.gitignore @@ -0,0 +1,6 @@ +*~ +build +*.log +*.cmd +tb_u1e +*.lxt diff --git a/fpga/usrp2/top/u1e_ethdebug/Makefile b/fpga/usrp2/top/u1e_ethdebug/Makefile new file mode 100644 index 000000000..751b52970 --- /dev/null +++ b/fpga/usrp2/top/u1e_ethdebug/Makefile @@ -0,0 +1,83 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u1e +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u1e.v \ +u1e.ucf + +SOURCES = $(abspath $(TOP_SRCS)) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u1e_ethdebug/u1e.ucf b/fpga/usrp2/top/u1e_ethdebug/u1e.ucf new file mode 100644 index 000000000..d6a2ea4ed --- /dev/null +++ b/fpga/usrp2/top/u1e_ethdebug/u1e.ucf @@ -0,0 +1,88 @@ + +## GPMC +NET "EM_D<15>" LOC = "D13" ; +NET "EM_D<14>" LOC = "D15" ; +NET "EM_D<13>" LOC = "C16" ; +NET "EM_D<12>" LOC = "B20" ; +NET "EM_D<11>" LOC = "A19" ; +NET "EM_D<10>" LOC = "A17" ; +NET "EM_D<9>" LOC = "E15" ; +NET "EM_D<8>" LOC = "F15" ; +NET "EM_D<7>" LOC = "E16" ; +NET "EM_D<6>" LOC = "F16" ; +NET "EM_D<5>" LOC = "B17" ; +NET "EM_D<4>" LOC = "C17" ; +NET "EM_D<3>" LOC = "B19" ; +NET "EM_D<2>" LOC = "D19" ; +NET "EM_D<1>" LOC = "C19" ; +NET "EM_D<0>" LOC = "A20" ; + +NET "EM_A<10>" LOC = "C14" ; +NET "EM_A<9>" LOC = "C10" ; +NET "EM_A<8>" LOC = "C5" ; +NET "EM_A<7>" LOC = "A18" ; +NET "EM_A<6>" LOC = "A15" ; +NET "EM_A<5>" LOC = "A12" ; +NET "EM_A<4>" LOC = "A10" ; +NET "EM_A<3>" LOC = "E7" ; +NET "EM_A<2>" LOC = "A7" ; +NET "EM_A<1>" LOC = "C15" ; + +NET "EM_NCS6" LOC = "E17" ; +NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; + +NET "EM_CLK" LOC = "F11" ; +NET "EM_WAIT0" LOC = "F14" ; +#NET "EM_NBE<1>" LOC = "D14" ; +#NET "EM_NBE<0>" LOC = "A13" ; +NET "EM_NWE" LOC = "B13" ; +NET "EM_NOE" LOC = "A14" ; +NET "EM_NADV_ALE" LOC = "B15" ; +#NET "EM_NWP" LOC = "F13" ; +NET "overo_gpio64" LOC = "A4" ; # nRESET +NET "overo_gpio176" LOC = "B4" ; # IRQ + +## Debug pins +NET "debug_led<3>" LOC = "Y15" ; +NET "debug_led<2>" LOC = "K16" ; +NET "debug_led<1>" LOC = "J17" ; +NET "debug_led<0>" LOC = "H22" ; +NET "debug<0>" LOC = "G22" ; +NET "debug<1>" LOC = "H17" ; +NET "debug<2>" LOC = "H18" ; +NET "debug<3>" LOC = "K20" ; +NET "debug<4>" LOC = "J20" ; +NET "debug<5>" LOC = "K19" ; +NET "debug<6>" LOC = "K18" ; +NET "debug<7>" LOC = "L22" ; +NET "debug<8>" LOC = "K22" ; +NET "debug<9>" LOC = "N22" ; +NET "debug<10>" LOC = "M22" ; +NET "debug<11>" LOC = "N20" ; +NET "debug<12>" LOC = "N19" ; +NET "debug<13>" LOC = "R22" ; +NET "debug<14>" LOC = "P22" ; +NET "debug<15>" LOC = "N17" ; +NET "debug<16>" LOC = "P16" ; +NET "debug<17>" LOC = "U22" ; +NET "debug<18>" LOC = "P19" ; +NET "debug<19>" LOC = "R18" ; +NET "debug<20>" LOC = "U20" ; +NET "debug<21>" LOC = "T20" ; +NET "debug<22>" LOC = "R19" ; +NET "debug<23>" LOC = "R20" ; +NET "debug<24>" LOC = "W22" ; +NET "debug<25>" LOC = "Y22" ; +NET "debug<26>" LOC = "T18" ; +NET "debug<27>" LOC = "T17" ; +NET "debug<28>" LOC = "W19" ; +NET "debug<29>" LOC = "V20" ; +NET "debug<30>" LOC = "Y21" ; +NET "debug<31>" LOC = "AA22" ; +NET "debug_clk<0>" LOC = "N18" ; +NET "debug_clk<1>" LOC = "M17" ; + +NET "debug_pb" LOC = "C22" ; diff --git a/fpga/usrp2/top/u1e_ethdebug/u1e.v b/fpga/usrp2/top/u1e_ethdebug/u1e.v new file mode 100644 index 000000000..2a543a313 --- /dev/null +++ b/fpga/usrp2/top/u1e_ethdebug/u1e.v @@ -0,0 +1,28 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +//`define DCM 1 + +module u1e + (output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input debug_pb, + + // GPMC + input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, input EM_NWE, input EM_NOE, + input EM_NADV_ALE, + + input overo_gpio64, input overo_gpio176 + ); + + assign debug_clk = {EM_CLK, EM_NADV_ALE}; + + assign debug_led = {1'b0, EM_A[9], EM_A[8], debug_pb}; + + assign debug = { {overo_gpio64, overo_gpio176, EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE }, + { EM_A[10], EM_A[7:1] }, + { EM_D[15:8] }, + { EM_D[7:0] } }; + + +endmodule // u1e diff --git a/fpga/usrp2/top/u1e_passthru/.gitignore b/fpga/usrp2/top/u1e_passthru/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/fpga/usrp2/top/u1e_passthru/.gitignore @@ -0,0 +1 @@ +build* diff --git a/fpga/usrp2/top/u1e_passthru/Makefile b/fpga/usrp2/top/u1e_passthru/Makefile new file mode 100644 index 000000000..d1950629b --- /dev/null +++ b/fpga/usrp2/top/u1e_passthru/Makefile @@ -0,0 +1,99 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = passthru +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs +include ../../gpmc/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +passthru.v \ +passthru.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPMC_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u1e_passthru/passthru.ucf b/fpga/usrp2/top/u1e_passthru/passthru.ucf new file mode 100644 index 000000000..64e6f0440 --- /dev/null +++ b/fpga/usrp2/top/u1e_passthru/passthru.ucf @@ -0,0 +1,6 @@ +NET "overo_gpio145" LOC = "C7" ; +NET "cgen_mosi" LOC = "E22" ; +NET "cgen_sclk" LOC = "J19" ; +NET "cgen_sen_b" LOC = "H20" ; +NET "fpga_cfg_din" LOC = "W17" ; +NET "fpga_cfg_cclk" LOC = "V17" ; diff --git a/fpga/usrp2/top/u1e_passthru/passthru.v b/fpga/usrp2/top/u1e_passthru/passthru.v new file mode 100644 index 000000000..12e4db017 --- /dev/null +++ b/fpga/usrp2/top/u1e_passthru/passthru.v @@ -0,0 +1,18 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module passthru + (input overo_gpio145, + output cgen_sclk, + output cgen_sen_b, + output cgen_mosi, + input fpga_cfg_din, + input fpga_cfg_cclk + ); + + assign cgen_sclk = fpga_cfg_cclk; + assign cgen_sen_b = overo_gpio145; + assign cgen_mosi = fpga_cfg_din; + + +endmodule // passthru diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v index a5963f6b1..a5963f6b1 100755..100644 --- a/fpga/usrp2/top/u2_rev3/u2_core.v +++ b/fpga/usrp2/top/u2_rev3/u2_core.v diff --git a/fpga/usrp2/top/u2_rev3/u2_core_udp.v b/fpga/usrp2/top/u2_rev3/u2_core_udp.v index b47e7e311..9e62ee1cc 100644 --- a/fpga/usrp2/top/u2_rev3/u2_core_udp.v +++ b/fpga/usrp2/top/u2_rev3/u2_core_udp.v @@ -125,7 +125,6 @@ module u2_core output [18:0] RAM_A, output RAM_CE1n, output RAM_CENn, - // output RAM_CLK, output RAM_WEn, output RAM_OEn, output RAM_LDn, @@ -162,6 +161,7 @@ module u2_core wire ram_loader_done; wire ram_loader_rst, wb_rst, dsp_rst; + assign dsp_rst = wb_rst; wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; @@ -561,14 +561,6 @@ module u2_core // Master Timer, Slave #9 // No longer used, replaced with simple_timer below - /* - wire [31:0] master_time; - timer timer - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), - .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), - .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - */ assign s9_ack = 0; // ///////////////////////////////////////////////////////////////////////// @@ -632,9 +624,15 @@ module u2_core .debug(debug_rx_dsp) ); wire [31:0] vrc_debug; + wire clear_rx; + setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx)); + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time), .overrun(overrun), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), @@ -644,7 +642,7 @@ module u2_core wire [3:0] vita_state; vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), @@ -652,7 +650,7 @@ module u2_core .debug_rx(vita_state) ); fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); @@ -662,23 +660,17 @@ module u2_core wire [35:0] tx_data; wire tx_src_rdy, tx_dst_rdy; wire [31:0] debug_vt; + wire clear_tx; - // FIFO cascade draws from buffer pool, feeds vita tx deframer -/* -----\/----- EXCLUDED -----\/----- - - fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), - .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); - -----/\----- EXCLUDED -----/\----- */ + setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) ext_fifo_i1 - ( - .int_clk(dsp_clk), + (.int_clk(dsp_clk), .ext_clk(clk_to_mac), -// .ext_clk(wb_clk), - .rst(dsp_rst), + .rst(dsp_rst | clear_tx), .RAM_D_pi(RAM_D_pi), .RAM_D_po(RAM_D_po), .RAM_D_poe(RAM_D_poe), @@ -688,17 +680,14 @@ module u2_core .RAM_LDn(RAM_LDn), .RAM_OEn(RAM_OEn), .RAM_CE1n(RAM_CE1n), -// .datain({rd1_flags,rd1_dat}), .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), - .src_rdy_i(rd1_ready_o), // WRITE - .dst_rdy_o(rd1_ready_i), // not FULL -// .dataout(tx_data), + .src_rdy_i(rd1_ready_o), + .dst_rdy_o(rd1_ready_i), .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), - .src_rdy_o(tx_src_rdy), // not EMPTY + .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy), .debug(debug_extfifo), - .debug2(debug_extfifo2) - ); + .debug2(debug_extfifo2) ); vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), @@ -713,8 +702,6 @@ module u2_core .underrun(underrun), .run(run_tx), .debug(debug_vt)); - assign dsp_rst = wb_rst; - // /////////////////////////////////////////////////////////////////////////////////// // SERDES @@ -728,63 +715,7 @@ module u2_core .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - // /////////////////////////////////////////////////////////////////////////////////// - // External RAM Interface - - /* - localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes - - wire [15:0] bus2ram, ram2bus; - wire [15:0] bridge_adr; - wire [1:0] bridge_sel; - wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; - - wire [19:0] page; - wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; - setting_reg #(.my_addr(6),.width(20)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(page),.changed()); - - wb_bridge_16_32 bridge - (.wb_clk(wb_clk),.wb_rst(wb_rst), - .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel), - .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack), - .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), - .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); - - wb_zbt16_b wb_zbt16_b - (.clk(wb_clk),.rst(wb_rst), - .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), - .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), - .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), - .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), - .sram_mode(),.sram_zz() ); - - assign RAM_CE1n = 0; - assign RAM_D[17:16] = 2'bzz; -/* -----\/----- EXCLUDED -----\/----- - *-/ - - test_sram_if test_sram_if_i1 - ( - // .clk(wb_clk), - .clk(clk_to_mac), - .rst(wb_rst), - .RAM_D_pi(RAM_D_pi), - .RAM_D_po(RAM_D_po), - .RAM_D_poe(RAM_D_poe), - .RAM_A(RAM_A), - .RAM_WEn(RAM_WEn), - .RAM_CENn(RAM_CENn), - .RAM_LDn(RAM_LDn), - .RAM_OEn(RAM_OEn), - .RAM_CE1n(RAM_CE1n), - .correct() - ); - -----/\----- EXCLUDED -----/\----- */ - - //assign RAM_CLK = wb_clk; - //assign RAM_CLK = clk_to_mac; - + assign RAM_CLK = clk_to_mac; // ///////////////////////////////////////////////////////////////////////// // VITA Timing @@ -802,140 +733,3 @@ module u2_core assign debug_gpio_1 = 32'd0; endmodule // u2_core - -/* - // FIFO Level Debugging - reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; - - always @(posedge dsp_clk) - serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, - {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; - - assign debug_clk[0] = GMII_RX_CLK; // wb_clk; - assign debug_clk[1] = dsp_clk; -*/ -/* - - wire mdio_cpy = MDIO; - assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, - { s6_adr[15:8] }, - { s6_adr[7:0] }, - { 6'd0, mdio_cpy, MDC } }; - - assign debug = { { GMII_TXD }, - { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, - { wr2_flags, rd2_flags }, - { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - assign debug = { { GMII_RXD }, - { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, - { wr2_flags, rd2_flags }, - { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - -// assign debug = debug_udp; - // assign debug = vrc_debug; -/* - assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state}, - {2'd0, rx_dst_rdy, rx_src_rdy, rx_data[99:96]}, - {run_rx_d1, run_rx, strobe_rx, overrun, wr1_flags[3:0]} , - {wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}}; -*/ -// assign debug_gpio_1 = {vita_time[63:32] }; -/* - assign debug_gpio_1 = { { tx_f19_data[15:8] }, - { tx_f19_data[7:0] }, - { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] }, - { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } }; - */ - -// wire debug_mux; -// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), -// .in(set_data),.out(debug_mux),.changed()); - -//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; -//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; - -//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, -// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; - -//assign debug = debug_tx_dsp; -//assign debug = debug_serdes0; - -//assign debug_gpio_0 = 0; //debug_serdes0; -//assign debug_gpio_1 = 0; //debug_serdes1; - -// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, -// {8'b0}, -// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, -// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; - -//assign debug = {dac_a,dac_b}; - -/* - assign debug = {{ram_loader_done, takeover, 6'd0}, - {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, - {8'd0}, - {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ - -/*assign debug = host_to_dsp_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; - */ -// Assign various commonly used debug buses. -/* - wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, - irq[7:0], - GMII_RXD, - GMII_TXD}; - - wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; - - wire [31:0] debug_time = {uart_tx_o, 7'b0, - irq[7:0], - 6'b0, GMII_RX_DV, GMII_TX_EN, - 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; - - wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, - irq[7:0], - proc_int, 7'b0 }; - - wire [31:0] debug_eth = - {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, - {8'd0}, - {8'd0}, - {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; - - assign debug_serdes0 = { { rd0_dat[7:0] }, - { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, - { ser_t[15:8] }, - { ser_t[7:0] } }; - - assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, - { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, - { ser_r[15:8] }, - { ser_r[7:0] } }; - - assign debug_gpio_1 = {uart_tx_o,7'd0, - 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, - debug_txc[15:0]}; - assign debug_gpio_1 = debug_rx; - assign debug_gpio_1 = debug_serdes1; - assign debug_gpio_1 = debug_eth; - - */ - diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf index deaeecb53..6e0caedd5 100644 --- a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf @@ -74,49 +74,49 @@ NET "MDC" LOC = "V18" ; NET "PHY_INTn" LOC = "AB13" ; NET "PHY_RESETn" LOC = "AA19" ; NET "PHY_CLK" LOC = "V15" ; -NET "RAM_D[0]" LOC = "N20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[1]" LOC = "N21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[2]" LOC = "N22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[3]" LOC = "M17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[4]" LOC = "M18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[5]" LOC = "M19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[6]" LOC = "M20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[7]" LOC = "M21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[8]" LOC = "M22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[9]" LOC = "Y22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[10]" LOC = "Y21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[11]" LOC = "Y20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[12]" LOC = "Y19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[13]" LOC = "W22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[14]" LOC = "W21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[15]" LOC = "W20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[16]" LOC = "W19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_D[17]" LOC = "V22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[0]" LOC = "U21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[1]" LOC = "T19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[2]" LOC = "V21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[3]" LOC = "V20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[4]" LOC = "T20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[5]" LOC = "T21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[6]" LOC = "T22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[7]" LOC = "T18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[8]" LOC = "R18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[9]" LOC = "P19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[10]" LOC = "P21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[11]" LOC = "P22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[12]" LOC = "N19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[13]" LOC = "N17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[14]" LOC = "N18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[15]" LOC = "T17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[16]" LOC = "U19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[17]" LOC = "U18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_A[18]" LOC = "V19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_CE1n" LOC = "U20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_CENn" LOC = "P18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_CLK" LOC = "P17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_WEn" LOC = "R22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_OEn" LOC = "R21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; -NET "RAM_LDn" LOC = "R19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = SLOW ; +NET "RAM_D[0]" LOC = "N20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[1]" LOC = "N21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[2]" LOC = "N22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[3]" LOC = "M17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[4]" LOC = "M18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[5]" LOC = "M19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[6]" LOC = "M20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[7]" LOC = "M21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[8]" LOC = "M22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[9]" LOC = "Y22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[10]" LOC = "Y21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[11]" LOC = "Y20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[12]" LOC = "Y19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[13]" LOC = "W22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[14]" LOC = "W21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[15]" LOC = "W20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[16]" LOC = "W19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[17]" LOC = "V22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[0]" LOC = "U21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[1]" LOC = "T19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[2]" LOC = "V21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[3]" LOC = "V20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[4]" LOC = "T20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[5]" LOC = "T21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[6]" LOC = "T22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[7]" LOC = "T18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[8]" LOC = "R18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[9]" LOC = "P19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[10]" LOC = "P21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[11]" LOC = "P22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[12]" LOC = "N19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[13]" LOC = "N17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[14]" LOC = "N18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[15]" LOC = "T17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[16]" LOC = "U19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[17]" LOC = "U18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[18]" LOC = "V19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CE1n" LOC = "U20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CENn" LOC = "P18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CLK" LOC = "P17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_WEn" LOC = "R22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_OEn" LOC = "R21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_LDn" LOC = "R19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; NET "ser_enable" LOC = "W11" ; NET "ser_prbsen" LOC = "AA3" ; NET "ser_loopen" LOC = "Y4" ; diff --git a/fpga/usrp2/top/u2plus/.gitignore b/fpga/usrp2/top/u2plus/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/fpga/usrp2/top/u2plus/.gitignore @@ -0,0 +1 @@ +build* diff --git a/fpga/usrp2/top/u2plus/Makefile b/fpga/usrp2/top/u2plus/Makefile new file mode 100644 index 000000000..c38bd3ec1 --- /dev/null +++ b/fpga/usrp2/top/u2plus/Makefile @@ -0,0 +1,99 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u2plus/bootloader.rmi b/fpga/usrp2/top/u2plus/bootloader.rmi new file mode 100644 index 000000000..7c15699db --- /dev/null +++ b/fpga/usrp2/top/u2plus/bootloader.rmi @@ -0,0 +1,245 @@ +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b808175c_00000000_b8080050; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8081764; +defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401e70_31a01e98_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f40668_80000000_b9f400cc; +defparam bootram.RAM0.INIT_04=256'he8830000_e8601e78_80000000_99fc2000_f8601e78_b8000044_bc030014_f9e10000; +defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a01e8c_bc030010_30600000_b0000000_30630004_be24ffec; +defparam bootram.RAM0.INIT_06=256'h30600000_b0000000_3021001c_b60f0008_e9e10000_f060f800_b0000000_30600001; +defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a01e8c_f9e10000_3021ffe4; +defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01e90_bc030014_30800000_b0000000_e8601e90; +defparam bootram.RAM0.INIT_09=256'h06463800_20e01e98_20c01e98_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; +defparam bootram.RAM0.INIT_0A=256'hb0000000_20c0f800_b0000000_bc92fff4_06463800_20c60004_f8060000_bc720014; +defparam bootram.RAM0.INIT_0B=256'hb9f415f8_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f82c; +defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f401c8_20e00000_20c00000_80000000_b9f41778_80000000; +defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f415c4_80000000_b9f41780; +defparam bootram.RAM0.INIT_0E=256'he9e10000_f9610004_fa410010_95608001_fa21000c_f9610008_f9e10000_3021ffec; +defparam bootram.RAM0.INIT_0F=256'hbc050018_30210014_b62e0000_ea410010_ea21000c_e9610008_940bc001_e9610004; +defparam bootram.RAM0.INIT_10=256'h3021ff2c_80000000_b60f0008_bc32fff4_16432800_30630001_80000000_10600000; +defparam bootram.RAM0.INIT_11=256'hb9f4062c_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c; +defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a01984_10b30000_b9f40da4_10d60000_10b30000; +defparam bootram.RAM0.INIT_13=256'h30a01984_bc120040_aa430001_30a0194c_e061001c_10a30000_be520034_16439003; +defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f406c0_b800ffb4_80000000_b9f406cc; +defparam bootram.RAM0.INIT_15=256'h80000000_b9f40694_b800ff88_80000000_b9f406a0_30a0194c_80000000_b9f4155c; +defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f40678_30a01950_80000000_b9f411e8_30a08000_b0000000; +defparam bootram.RAM0.INIT_17=256'hbe030020_30a00050_31000001_30e1001c_30c000f7_f9e10000_a46500ff_3021ffe0; +defparam bootram.RAM0.INIT_18=256'hb810ffe8_30210020_b60f0008_e9e10000_80000000_b9f40330_f081001c_3080005e; +defparam bootram.RAM0.INIT_19=256'h31000001_b9f40280_f9e10000_30e1001c_30c000f7_30a00050_3021ffe0_308000dc; +defparam bootram.RAM0.INIT_1A=256'h3021ffdc_30210020_b60f0008_6463001f_3063ffff_a863005e_e9e10000_e061001c; +defparam bootram.RAM0.INIT_1B=256'h30a0a120_b0000007_9403c001_ac640002_94808001_fac10020_fa61001c_f9e10000; +defparam bootram.RAM0.INIT_1C=256'hb9f40ea8_80000000_b9f4082c_f800200c_80000000_b9f4fe74_f860200c_306000ff; +defparam bootram.RAM0.INIT_1D=256'h80000000_b9f4ff6c_80000000_b9f4059c_30a01988_80000000_b9f409ec_80000000; +defparam bootram.RAM0.INIT_1E=256'h30a00000_b0000030_bc160100_bc130134_a6632000_e8603334_12c30000_be23017c; +defparam bootram.RAM0.INIT_1F=256'hb0000000_80000000_b9f40558_30a01b04_12c30000_be030068_80000000_b9f41180; +defparam bootram.RAM0.INIT_20=256'hb9f41094_30a08000_b0000000_30c07c00_b9f40e70_30a00000_b0000030_30e08000; +defparam bootram.RAM0.INIT_21=256'he9e10000_30600001_10a00000_b9f41244_80000000_b9f40524_30a01b30_80000000; +defparam bootram.RAM0.INIT_22=256'hb000003f_80000000_b9f404f8_30a01b6c_30210024_b60f0008_eac10020_ea61001c; +defparam bootram.RAM0.INIT_23=256'h80000000_b9f404d4_30a019f8_12630000_be230024_80000000_b9f410fc_30a00000; +defparam bootram.RAM0.INIT_24=256'h30a00000_b000003f_30e08000_b0000000_10730000_b810ffb4_80000000_b9f4fd9c; +defparam bootram.RAM0.INIT_25=256'hb9f40490_30a019bc_80000000_b9f41000_30a08000_b0000000_30c07c00_b9f40ddc; +defparam bootram.RAM0.INIT_26=256'h80000000_b9f40474_30a01a50_30600001_b810ff70_10b60000_b9f411b0_80000000; +defparam bootram.RAM0.INIT_27=256'h80000000_b9f40454_30a01ab4_bc230098_80000000_b9f41000_30a00000_b0000018; +defparam bootram.RAM0.INIT_28=256'h80000000_b9f41048_30a00000_b000003f_80000000_b9f40444_30a0199c_b800fed8; +defparam bootram.RAM0.INIT_29=256'hb9f4fda4_b800fe9c_80000000_b9f4fcec_80000000_b9f40424_30a019f8_bc230028; +defparam bootram.RAM0.INIT_2A=256'h30c07c00_b9f40d24_30a00000_b000003f_30e08000_b0000000_b800fe84_10a00000; +defparam bootram.RAM0.INIT_2B=256'hb9f410f8_80000000_b9f403d8_30a019bc_80000000_b9f40f48_30a08000_b0000000; +defparam bootram.RAM0.INIT_2C=256'hb9f4fc60_30a00001_b9f4fd4c_80000000_b9f403c0_30a01a7c_b800fe50_10b30000; +defparam bootram.RAM0.INIT_2D=256'hfa610020_3021ffd4_b800ff40_80000000_b9f410c8_30a00000_b0000018_30a07530; +defparam bootram.RAM0.INIT_2E=256'hfac10024_30e00001_30c1001c_12e70000_f0c1001c_fae10028_10b30000_a66500ff; +defparam bootram.RAM0.INIT_2F=256'h10b30000_10f60000_10d70000_10830000_be030030_12c80000_b9f40898_f9e10000; +defparam bootram.RAM0.INIT_30=256'h10640000_a8830001_6463001f_3063ffff_80000000_b9f407d0_30800001_be76001c; +defparam bootram.RAM0.INIT_31=256'hfac10024_3021ffcc_3021002c_b60f0008_eae10028_eac10024_ea610020_e9e10000; +defparam bootram.RAM0.INIT_32=256'hf9e10000_12c80000_12e70000_13250000_13060000_fb210030_fb01002c_fae10028; +defparam bootram.RAM0.INIT_33=256'h32d6ffff_e0770000_f301001c_30e00002_be76005c_30c1001c_10b90000_fa610020; +defparam bootram.RAM0.INIT_34=256'hbe33ffcc_32f70001_b9f4089c_30a0000a_12630000_33180001_b9f407f8_f061001d; +defparam bootram.RAM0.INIT_35=256'heb210030_eb01002c_eae10028_eac10024_ea610020_e9e10000_10730000_10b90000; +defparam bootram.RAM0.INIT_36=256'h80000000_b9f4f998_f9e10000_3021ffe4_30600001_b810ffe0_30210034_b60f0008; +defparam bootram.RAM0.INIT_37=256'h12660000_fb21002c_fb010028_fae10024_fa61001c_3021ffd0_80000000_b60f0008; +defparam bootram.RAM0.INIT_38=256'haa43ffff_12c00000_b810001c_f9e10000_fac10020_13260000_12e70000_13050000; +defparam bootram.RAM0.INIT_39=256'h10960000_90630060_10b80000_b9f405ec_32730001_bcb2002c_16572001_bc120030; +defparam bootram.RAM0.INIT_3A=256'he9e10000_10640000_f0130000_14999800_32d60001_be32ffd4_aa43000a_f0730000; +defparam bootram.RAM0.INIT_3B=256'h3021ffd0_30210030_b60f0008_eb21002c_eb010028_eae10024_eac10020_ea61001c; +defparam bootram.RAM0.INIT_3C=256'h13260000_12e70000_13050000_12660000_fb21002c_fb010028_fae10024_fa61001c; +defparam bootram.RAM0.INIT_3D=256'hb9f4051c_32730001_bcb2002c_16572001_12c00000_b8100014_f9e10000_fac10020; +defparam bootram.RAM0.INIT_3E=256'h14999800_32d60001_be32ffdc_aa43000a_f0730000_10960000_90630060_10b80000; +defparam bootram.RAM0.INIT_3F=256'heb21002c_eb010028_eae10024_eac10020_ea61001c_e9e10000_10640000_f0130000; +defparam bootram.RAM1.INIT_00=256'h12e60000_12c50000_fae10024_fac10020_fa61001c_3021ffd8_30210030_b60f0008; +defparam bootram.RAM1.INIT_01=256'hbe32ffec_aa43000a_f0730000_90630060_10b60000_b9f404b0_12660000_f9e10000; +defparam bootram.RAM1.INIT_02=256'heae10024_eac10020_ea61001c_e9e10000_10770000_f0130000_3273ffff_32730001; +defparam bootram.RAM1.INIT_03=256'he9e10000_10a00000_b9f4ff94_f9e10000_3021ffe4_10c50000_30210028_b60f0008; +defparam bootram.RAM1.INIT_04=256'hb60f0008_e9e10000_80000000_b9f40448_f9e10000_3021ffe4_3021001c_b60f0008; +defparam bootram.RAM1.INIT_05=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ffdc_f9e10000_3021ffe4_3021001c; +defparam bootram.RAM1.INIT_06=256'hbe060024_90c30060_12660000_e0660000_f9e10000_fac10020_fa61001c_3021ffdc; +defparam bootram.RAM1.INIT_07=256'h10b60000_be26fff0_90c30060_e0730000_32730001_b9f40324_10b60000_12c50000; +defparam bootram.RAM1.INIT_08=256'hfac1001c_3021ffe0_30210024_b60f0008_10600000_eac10020_ea61001c_e9e10000; +defparam bootram.RAM1.INIT_09=256'heac1001c_e9e10000_30c0000a_b9f402dc_10b60000_12c50000_b9f4ff9c_f9e10000; +defparam bootram.RAM1.INIT_0A=256'h10a00000_b9f4ffc0_f9e10000_3021ffe4_10c50000_30210020_b60f0008_10600000; +defparam bootram.RAM1.INIT_0B=256'h10a00000_b9f4ff48_f9e10000_3021ffe4_10c50000_3021001c_b60f0008_e9e10000; +defparam bootram.RAM1.INIT_0C=256'he9e10000_30c0000a_b9f40278_f9e10000_3021ffe4_3021001c_b60f0008_e9e10000; +defparam bootram.RAM1.INIT_0D=256'hb9f40250_f9e10000_10a00000_12c50000_fac1001c_3021ffe0_3021001c_b60f0008; +defparam bootram.RAM1.INIT_0E=256'hfac1001c_3021ffe0_30210020_b60f0008_eac1001c_e9e10000_10760000_10d60000; +defparam bootram.RAM1.INIT_0F=256'h30210020_b60f0008_eac1001c_e9e10000_10760000_12c60000_b9f40228_f9e10000; +defparam bootram.RAM1.INIT_10=256'h94e08001_3021001c_b60f0008_e9e10000_80000000_b9f401b8_f9e10000_3021ffe4; +defparam bootram.RAM1.INIT_11=256'h80633000_84632000_84c62800_a866ffff_e880f81c_b0000000_9404c001_ac870002; +defparam bootram.RAM1.INIT_12=256'h9404c001_80843800_ac840002_94808001_a4e70002_f860f81c_b0000000_f860200c; +defparam bootram.RAM1.INIT_13=256'h88a52000_e880f81c_b0000000_9406c001_acc30002_94608001_80000000_b60f0008; +defparam bootram.RAM1.INIT_14=256'h9404c001_80841800_ac840002_94808001_a4630002_f8a0f81c_b0000000_f8a0200c; +defparam bootram.RAM1.INIT_15=256'ha866ffff_e880f820_b0000000_9404c001_ac870002_94e08001_80000000_b60f0008; +defparam bootram.RAM1.INIT_16=256'h94808001_a4e70002_f860f820_b0000000_f8602020_80633000_84632000_84c62800; +defparam bootram.RAM1.INIT_17=256'hfae10024_fa61001c_3021ffd4_80000000_b60f0008_9404c001_80843800_ac840002; +defparam bootram.RAM1.INIT_18=256'hbe060040_90c30060_13050000_12e60000_e0660000_fac10020_f9e10000_fb010028; +defparam bootram.RAM1.INIT_19=256'h10730000_be120028_16569800_32c70001_b8100014_32600001_be670038_12660000; +defparam bootram.RAM1.INIT_1A=256'h10730000_3273ffff_32730001_be26ffe4_90c30060_c0779800_10b80000_b9f400cc; +defparam bootram.RAM1.INIT_1B=256'h3021ffe4_3021002c_b60f0008_eb010028_eae10024_eac10020_ea61001c_e9e10000; +defparam bootram.RAM1.INIT_1C=256'hf0c51e7c_3021001c_b60f0008_e9e10000_30c0000a_b9f40084_f9e10000_10a00000; +defparam bootram.RAM1.INIT_1D=256'h80000000_b60f0008_f8653700_64a50405_e4661bac_10c63000_80000000_b60f0008; +defparam bootram.RAM1.INIT_1E=256'h90c60060_b9f4ffc4_10b30000_e0d31e7c_12600000_f9e10000_fa61001c_3021ffe0; +defparam bootram.RAM1.INIT_1F=256'he9e10000_bc32ffd8_aa530003_90c60060_b9f4ffbc_32730001_10b30000_e0d31ba8; +defparam bootram.RAM1.INIT_20=256'h12c60000_f9e10000_fac10020_fa61001c_3021ffdc_30210020_b60f0008_ea61001c; +defparam bootram.RAM1.INIT_21=256'hfac5000c_bc03fffc_e8650004_30a33700_64730405_12650000_be120030_aa46000a; +defparam bootram.RAM1.INIT_22=256'hbc32ffd0_aa430001_e0651e7c_30210024_b60f0008_eac10020_ea61001c_e9e10000; +defparam bootram.RAM1.INIT_23=256'hf9e10000_fac10020_fa61001c_3021ffdc_64730405_b810ffc8_30c0000d_b9f4ffac; +defparam bootram.RAM1.INIT_24=256'hbc040008_e8830004_30633700_64730405_12650000_be120030_aa46000a_12c60000; +defparam bootram.RAM1.INIT_25=256'haa430001_e0651e7c_30210024_b60f0008_eac10020_ea61001c_e9e10000_fac3000c; +defparam bootram.RAM1.INIT_26=256'h30a53700_64a50405_64730405_b810ffc4_80000000_b9f4ff44_30c0000d_be32ffd0; +defparam bootram.RAM1.INIT_27=256'he8650008_30a53700_64a50405_80000000_b60f0008_e8650010_bc03fffc_e8650008; +defparam bootram.RAM1.INIT_28=256'h64a50405_80000000_b60f0008_90630060_be24fff8_e8850008_e8650010_bc030014; +defparam bootram.RAM1.INIT_29=256'h32600001_be230040_e8760008_32c53700_fa61001c_f9e10000_fac10020_3021ffdc; +defparam bootram.RAM1.INIT_2A=256'hbe03ffe8_e8760008_30a00001_b9f401e0_3060ffff_be120034_aa53012d_b8000010; +defparam bootram.RAM1.INIT_2B=256'he9e10000_e8760010_3060ffff_be52000c_16539001_3240012b_3273ffff_32730001; +defparam bootram.RAM1.INIT_2C=256'h32400004_a463000f_e8603324_f8003108_30210024_b60f0008_eac10020_ea61001c; +defparam bootram.RAM1.INIT_2D=256'ha46300ff_64a30008_e4641bb8_10831800_30600004_10831800_beb20010_16439001; +defparam bootram.RAM1.INIT_2E=256'ha4a500ff_be070088_80000000_b60f0008_f8603108_30600080_f8a03104_f8603100; +defparam bootram.RAM1.INIT_2F=256'hf8803110_30800090_f860310c_a0630001_10652800_be23fff8_a4630040_e8603110; +defparam bootram.RAM1.INIT_30=256'haa470001_10800000_be230058_a4630080_e8603110_bc23fff8_a4630002_e8603110; +defparam bootram.RAM1.INIT_31=256'h30e7ffff_e860310c_bc23fff8_a4630002_e8603110_f8603110_30600020_be120038; +defparam bootram.RAM1.INIT_32=256'h30600068_b810ffd0_30600020_be32ffd8_aa470001_30c60001_be07001c_f0660000; +defparam bootram.RAM1.INIT_33=256'ha4a500ff_10640000_b60f0008_f8603110_30600040_10640000_b60f0008_30800001; +defparam bootram.RAM1.INIT_34=256'h306000d0_30600090_be27000c_f860310c_10652800_be23fff8_a4630040_e8603110; +defparam bootram.RAM1.INIT_35=256'h10800000_be23005c_a4630080_e8603110_bc23fff8_a4630002_e8603110_f8603110; +defparam bootram.RAM1.INIT_36=256'hf8803110_bc120030_aa470001_f860310c_30800010_e0660000_30800001_be070068; +defparam bootram.RAM1.INIT_37=256'hbe070028_30e7ffff_be23001c_a4630080_e8603110_bc23fff8_a4630002_e8603110; +defparam bootram.RAM1.INIT_38=256'hb60f0008_f8603110_30600040_10800000_30800050_b810ffd4_b800ffc4_30c60001; +defparam bootram.RAM1.INIT_39=256'hbc260054_a4c30000_b0008000_e8603324_10640000_b60f0008_30800001_10640000; +defparam bootram.RAM1.INIT_3A=256'h80000000_10800000_bc660030_e8c01e80_10660000_be650048_bc430054_e8601e80; +defparam bootram.RAM1.INIT_3B=256'h16443000_30840001_80000000_80000000_80000000_80000000_80000000_80000000; +defparam bootram.RAM1.INIT_3C=256'ha4630007_e8603324_80000000_b60f0008_bc32ffc8_16432800_30630001_bc32ffdc; +defparam bootram.RAM1.INIT_3D=256'h16459001_3240005a_3065ffa9_90a50060_b800ff9c_f8801e80_e4831bc4_10631800; +defparam bootram.RAM1.INIT_3E=256'h3085ffd0_be52000c_16459001_32400039_a46300ff_3065ffc9_a46300ff_be520024; +defparam bootram.RAM1.INIT_3F=256'hf9e10000_fb610034_13250000_fb21002c_3021ffc8_80000000_b60f0008_a46400ff; +defparam bootram.RAM2.INIT_00=256'haa43003a_13660000_e0790000_fb410030_fb010028_fae10024_fac10020_fa61001c; +defparam bootram.RAM2.INIT_01=256'heb010028_eae10024_eac10020_ea61001c_e9e10000_10650000_30a0ffff_be120034; +defparam bootram.RAM2.INIT_02=256'hc085c800_30a00001_e8c01e84_30210038_b60f0008_eb610034_eb410030_eb21002c; +defparam bootram.RAM2.INIT_03=256'hb810ffac_bc23ffe4_a4630044_c0662000_a4a300ff_be04001c_90840060_30650001; +defparam bootram.RAM2.INIT_04=256'h12761800_66c30404_b9f4ff1c_e0b90002_80000000_b9f4ff28_e0b90001_30a0fffe; +defparam bootram.RAM2.INIT_05=256'he0b90005_30a0fffd_be38ff74_93040060_e083000b_10791800_fa7b0004_10739800; +defparam bootram.RAM2.INIT_06=256'h66c3040c_b9f4fed8_e0b90004_66e30404_b9f4fee4_e0b90003_13530000_b9f4fef0; +defparam bootram.RAM2.INIT_07=256'he0b90007_fafb0008_12f7b000_12d61800_12d61800_b9f4fec8_64630408_e0b90006; +defparam bootram.RAM2.INIT_08=256'hbe130060_f07b0000_1063b000_66c30404_b9f4fea4_e0b90008_80000000_b9f4feb0; +defparam bootram.RAM2.INIT_09=256'hb9f4fe74_c0b6c800_a6d600ff_32d60009_12d8c000_ea7b000c_13580000_10f30000; +defparam bootram.RAM2.INIT_0A=256'he8fb0004_ea7b000c_d0789800_1063b800_66e30404_b9f4fe68_e0b60001_12d9b000; +defparam bootram.RAM2.INIT_0B=256'headb0008_a74300ff_be52ffb8_1647c003_107a1800_a70400ff_c073c000_30980001; +defparam bootram.RAM2.INIT_0C=256'h107a1800_12c7b000_10632000_e0b70009_12f9b800_64760008_12e73800_e09b0000; +defparam bootram.RAM2.INIT_0D=256'ha6d600ff_1063c000_16d60000_67030404_b9f4fe04_e0b7000a_12d61800_b9f4fe10; +defparam bootram.RAM2.INIT_0E=256'ha4630100_e8603b10_10a00000_b810fe58_30a0fffb_be32fe60_1643b000_a46300ff; +defparam bootram.RAM2.INIT_0F=256'ha4a500ff_80884800_a1292000_a508007f_a5290600_80000000_b60f0008_bc23fff8; +defparam bootram.RAM2.INIT_10=256'ha0840100_f8603b18_a46600ff_f8803b10_f8e03b00_bc23fff8_a4630100_e8603b10; +defparam bootram.RAM2.INIT_11=256'hb60f0008_e8603b00_bc23fff8_a4630100_e8603b10_10650000_be050018_f8803b10; +defparam bootram.RAM2.INIT_12=256'h31200400_31000008_10a00000_f9e10000_3021ffe4_10e60000_10c00000_80000000; +defparam bootram.RAM2.INIT_13=256'h3021ffc4_3021001c_b60f0008_e9e10000_80000000_b9f4ff84_f8603b14_30600001; +defparam bootram.RAM2.INIT_14=256'hb9f4ff3c_fae10034_13060000_f9e10000_fb010038_fa61002c_12c50000_fac10030; +defparam bootram.RAM2.INIT_15=256'hfac03b00_f8603b04_3060000b_66d60408_f8603b10_f8003b18_30600400_12670000; +defparam bootram.RAM2.INIT_16=256'h80000000_b9f4ff00_f8603b10_30600528_f8803b10_30800428_f8603b18_30600001; +defparam bootram.RAM2.INIT_17=256'hf8803b10_30800500_f8603b10_30600400_3261001c_12e00000_12d30000_be18009c; +defparam bootram.RAM2.INIT_18=256'he8803b04_f8610020_e8603b08_f881001c_14b7c000_e8803b0c_80000000_b9f4fed8; +defparam bootram.RAM2.INIT_19=256'h30a00010_10800000_beb20034_16459003_22400010_f8610028_e8603b00_f8810024; +defparam bootram.RAM2.INIT_1A=256'hbeb20020_1658b803_12f72800_bc32fff0_16442800_30840001_d0762000_c0732000; +defparam bootram.RAM2.INIT_1B=256'hf8003b18_12d62800_be52ff7c_1658b803_12f72800_bc25ffd8_b800ff8c_12d62800; +defparam bootram.RAM2.INIT_1C=256'hb0009f00_3021003c_b60f0008_eb010038_eae10034_eac10030_ea61002c_e9e10000; +defparam bootram.RAM2.INIT_1D=256'h31200400_b9f4fe34_f9e10000_31000020_30c00001_30a00001_3021ffe4_30e00000; +defparam bootram.RAM2.INIT_1E=256'h3021ffe4_e860f828_b0000000_3021001c_b60f0008_a463ffff_b00000ff_e9e10000; +defparam bootram.RAM2.INIT_1F=256'h64830008_80000000_b9f4ffa8_3021001c_b60f0008_e9e10000_bc030010_f9e10000; +defparam bootram.RAM2.INIT_20=256'h16439001_32400015_80000000_b9f40330_a46300ff_be120010_aa440020_a48400ff; +defparam bootram.RAM2.INIT_21=256'hb0000000_b800ffb0_f860f828_b0000000_bc52ffe4_16439001_32400018_bcb2fff0; +defparam bootram.RAM2.INIT_22=256'hb9f4ff40_3021001c_b60f0008_e9e10000_bc030010_f9e10000_3021ffe4_e860f824; +defparam bootram.RAM2.INIT_23=256'h80000000_b9f402c8_a4a300ff_be120010_aa440020_a48400ff_64830008_80000000; +defparam bootram.RAM2.INIT_24=256'hb0000000_e0651bbe_bc52ffe4_16459001_32400018_bcb2fff0_16459001_32400015; +defparam bootram.RAM2.INIT_25=256'h10c50000_12c00000_fac1001c_3021ffe0_b800ffa4_f860f824_b0000000_f8a0f828; +defparam bootram.RAM2.INIT_26=256'heac1001c_e9e10000_80000000_99fcb000_30e00024_b9f40334_f9e10000_10b60000; +defparam bootram.RAM2.INIT_27=256'hb810001c_30e1001c_b9f4fd88_f9e10000_30c00040_3021ffa4_30210020_b60f0008; +defparam bootram.RAM2.INIT_28=256'he063001c_10612800_10600000_be520044_16459001_3240003e_30a50001_10a00000; +defparam bootram.RAM2.INIT_29=256'haa440099_e083001c_10612800_30a50001_bc32ffd8_aa4300aa_bc12ffe0_aa4300ff; +defparam bootram.RAM2.INIT_2A=256'h3021005c_b60f0008_e9e10000_3021005c_b60f0008_e9e10000_30600001_be32ffc8; +defparam bootram.RAM2.INIT_2B=256'h10b60000_30c00006_b9f4fd08_f9e10000_10f60000_32c1001c_fac10028_3021ffd4; +defparam bootram.RAM2.INIT_2C=256'heac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f401f8_30c01bd8; +defparam bootram.RAM2.INIT_2D=256'h65040403_64e40003_64a40007_64c40005_e0803a03_3021002c_b60f0008_6464001f; +defparam bootram.RAM2.INIT_2E=256'ha4a50008_80e73000_90a40041_a4e70004_80c62800_a4c60002_64640407_65240405; +defparam bootram.RAM2.INIT_2F=256'h81294000_a5290040_81082000_a5080020_80842800_a4840010_80a53800_10842000; +defparam bootram.RAM2.INIT_30=256'h64e50403_64c50003_64650007_64850005_a4a500ff_a46300ff_b60f0008_80634800; +defparam bootram.RAM2.INIT_31=256'ha4630008_80c62000_90650041_a4c60004_80841800_a4840002_65250407_65050405; +defparam bootram.RAM2.INIT_32=256'h81083800_a5080040_80e72800_a4e70020_80a51800_a4a50010_80633000_10a52800; +defparam bootram.RAM2.INIT_33=256'hb00000ff_fac1001c_3021ffe0_80000000_b60f0008_f9203a00_a52900ff_81294000; +defparam bootram.RAM2.INIT_34=256'h30a0ffaa_b9f4ff74_30a0ffff_b9f4ff7c_30a0ffff_b9f4ff84_f9e10000_a6c5ffff; +defparam bootram.RAM2.INIT_35=256'h30a00061_b9f4ff54_30a00032_b9f4ff5c_a2d60000_b0000b00_30a0ff99_b9f4ff6c; +defparam bootram.RAM2.INIT_36=256'h30a0ff81_b9f4ff34_30a00032_b9f4ff3c_10b60000_b9f4ff44_64b60008_b9f4ff4c; +defparam bootram.RAM2.INIT_37=256'h30a0ffa1_b9f4ff14_30a00030_b9f4ff1c_64b60010_b9f4ff24_30a0000b_b9f4ff2c; +defparam bootram.RAM2.INIT_38=256'h10a00000_b9f4fef4_30a00020_b9f4fefc_30a0000e_b9f4ff04_10a00000_b9f4ff0c; +defparam bootram.RAM2.INIT_39=256'h30210020_b60f0008_eac1001c_e9e10000_10a00000_b9f4fee4_30a00020_b9f4feec; +defparam bootram.RAM2.INIT_3A=256'hb6110000_30a0ffff_b9f4e91c_80000000_b9f4f220_f9e10000_3021ffe4_30a01be0; +defparam bootram.RAM2.INIT_3B=256'h22400003_80000000_b60f0008_80000000_b60f0008_80000000_b6910000_80000000; +defparam bootram.RAM2.INIT_3C=256'h16432000_e8660000_e8850000_bc230050_a4630003_80653000_beb2005c_16479003; +defparam bootram.RAM2.INIT_3D=256'h30e7ffff_30c60004_be52ffe0_16479003_22400003_30a50004_30e7fffc_bc320040; +defparam bootram.RAM2.INIT_3E=256'h30c60001_30a50001_be320020_16434000_e0660000_e1050000_bc120028_aa47ffff; +defparam bootram.RAM2.INIT_3F=256'h2240000f_14634000_b60f0008_10600000_b60f0008_bc32ffe0_aa47ffff_30e7ffff; +defparam bootram.RAM3.INIT_00=256'hbc070024_11050000_be030034_a4630003_80662800_10850000_beb20018_16479003; +defparam bootram.RAM3.INIT_01=256'h30c60001_be32fff0_16474000_31080001_f0680000_e0660000_10e72000_11040000; +defparam bootram.RAM3.INIT_02=256'he8860008_f8680004_e8660004_f8880000_30e7fff0_e8860000_10650000_b60f0008; +defparam bootram.RAM3.INIT_03=256'h31080010_be52ffd0_16479003_2240000f_f868000c_30c60010_e866000c_f8880008; +defparam bootram.RAM3.INIT_04=256'h22400003_d8682000_30e7fffc_c8662000_10800000_bcb2002c_16479003_22400003; +defparam bootram.RAM3.INIT_05=256'he860193c_10880000_b810ff68_11044000_10c43000_30840004_be52ffec_16479003; +defparam bootram.RAM3.INIT_06=256'h3273fffc_99fc1800_bc120018_aa43ffff_3260193c_f9e10000_fa61001c_3021ffe0; +defparam bootram.RAM3.INIT_07=256'h3021fff8_30210020_b60f0008_ea61001c_e9e10000_bc32fff0_aa43ffff_e8730000; +defparam bootram.RAM3.INIT_08=256'h30210008_b60f0008_c9e00800_80000000_b9f4ffb0_80000000_b9f4e7d4_d9e00800; +defparam bootram.RAM3.INIT_09=256'hffffffff_30210008_b60f0008_c9e00800_80000000_b9f4e74c_d9e00800_3021fff8; +defparam bootram.RAM3.INIT_0A=256'h696d6167_61696e20_523a206d_4552524f_4f4b0000_00000000_ffffffff_00000000; +defparam bootram.RAM3.INIT_0B=256'h64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e_65207265; +defparam bootram.RAM3.INIT_0C=256'h53746172_720a0000_6f616465_6f6f746c_322b2062_55535250_4e4f4b00_64652e00; +defparam bootram.RAM3.INIT_0D=256'h4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20_20555352_74696e67; +defparam bootram.RAM3.INIT_0E=256'h20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672_65747572_523a2072; +defparam bootram.RAM3.INIT_0F=256'h523a206e_4552524f_6e210000_61707065_65722068_206e6576_6f756c64_73207368; +defparam bootram.RAM3.INIT_10=256'h626c652e_61696c61_65206176_696d6167_61726520_69726d77_66652066_6f207361; +defparam bootram.RAM3.INIT_11=256'h6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963_6d206120_20492061; +defparam bootram.RAM3.INIT_12=256'h2076616c_20666f72_6b696e67_43686563_2e000000_2052414d_5820746f_20494845; +defparam bootram.RAM3.INIT_13=256'h56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070; +defparam bootram.RAM3.INIT_14=256'h642e2041_666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072; +defparam bootram.RAM3.INIT_15=256'h2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e_7474656d; +defparam bootram.RAM3.INIT_16=256'h74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741_696f6e20_64756374; +defparam bootram.RAM3.INIT_17=256'h77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164_20746f20_74696e67; +defparam bootram.RAM3.INIT_18=256'h6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69_2e2e2e00; +defparam bootram.RAM3.INIT_19=256'h6e206672_65747572_523a2052_4552524f_2e2e2e00_64696e67_204c6f61_756e642e; +defparam bootram.RAM3.INIT_1A=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d; +defparam bootram.RAM3.INIT_1B=256'h696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000_61707065_65722068; +defparam bootram.RAM3.INIT_1C=256'h6669726d_61666520_6e672073_54727969_6e642e20_20666f75_77617265_6669726d; +defparam bootram.RAM3.INIT_1D=256'h0018000f_ffff0031_01b200d9_05160364_14580a2c_05050400_2e2e2e00_77617265; +defparam bootram.RAM3.INIT_1E=256'hb8080000_b0000000_10101200_06820594_09c407d0_13880d05_00002710_000b0000; +defparam bootram.RAM3.INIT_1F=256'h20202020_28282820_20202828_20202020_00202020_00000000_6f72740a_0a0a6162; +defparam bootram.RAM3.INIT_20=256'h10040404_10101010_10101010_10101010_20881010_20202020_20202020_20202020; +defparam bootram.RAM3.INIT_21=256'h01010101_01010101_01010101_41414141_10104141_10101010_04040410_04040404; +defparam bootram.RAM3.INIT_22=256'h02020202_02020202_02020202_42424242_10104242_10101010_01010101_01010101; +defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_20000000_10101010_02020202_02020202; +defparam bootram.RAM3.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2B=256'h28282020_20282828_20202020_20202020_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_2C=256'h10101010_10101010_10101010_88101010_20202020_20202020_20202020_20202020; +defparam bootram.RAM3.INIT_2D=256'h01010101_01010101_41414101_10414141_10101010_04041010_04040404_04040404; +defparam bootram.RAM3.INIT_2E=256'h02020202_02020202_42424202_10424242_10101010_01010110_01010101_01010101; +defparam bootram.RAM3.INIT_2F=256'h00000000_00000000_00000000_00000000_10101020_02020210_02020202_02020202; +defparam bootram.RAM3.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_33=256'h01010100_00001948_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00001d70_ffffffff; diff --git a/fpga/usrp2/top/u2plus/capture_ddrlvds.v b/fpga/usrp2/top/u2plus/capture_ddrlvds.v new file mode 100644 index 000000000..b9f53ff8c --- /dev/null +++ b/fpga/usrp2/top/u2plus/capture_ddrlvds.v @@ -0,0 +1,39 @@ + + +module capture_ddrlvds + #(parameter WIDTH=7) + (input clk, + input ssclk_p, + input ssclk_n, + input [WIDTH-1:0] in_p, + input [WIDTH-1:0] in_n, + output reg [(2*WIDTH)-1:0] out); + + wire [WIDTH-1:0] ddr_dat; + wire ssclk_regional; + wire ssclk_io; + wire ssclk; + wire [(2*WIDTH)-1:0] out_pre1; + reg [(2*WIDTH)-1:0] out_pre2; + + IBUFGDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); + + genvar i; + generate + for(i = 0; i < WIDTH; i = i + 1) + begin : gen_lvds_pins + IBUFDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) ibufds + (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); + IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 + (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), + .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0)); + end + endgenerate + + always @(negedge clk) + out_pre2 <= out_pre1; + + always @(posedge clk) + out <= out_pre2; + +endmodule // capture_ddrlvds diff --git a/fpga/usrp2/top/u2plus/u2plus.ucf b/fpga/usrp2/top/u2plus/u2plus.ucf index 091eb2005..25267a67e 100755 --- a/fpga/usrp2/top/u2plus/u2plus.ucf +++ b/fpga/usrp2/top/u2plus/u2plus.ucf @@ -1,157 +1,137 @@ -NET "DAC_LOCK" LOC = "P4" ; +## Main 100 MHz Clock +NET "CLK_FPGA_P" LOC = "AA13" ; +NET "CLK_FPGA_N" LOC = "Y13" ; + +## ADC NET "ADC_clkout_p" LOC = "P1" ; NET "ADC_clkout_n" LOC = "P2" ; -NET "io_rx<15>" LOC = "AD1" ; -NET "io_rx<14>" LOC = "AD2" ; -NET "io_rx<13>" LOC = "AC2" ; -NET "io_rx<12>" LOC = "AC3" ; -NET "io_rx<11>" LOC = "W7" ; -NET "io_rx<10>" LOC = "W6" ; -NET "io_rx<09>" LOC = "U9" ; -NET "io_rx<08>" LOC = "V8" ; -NET "io_rx<07>" LOC = "AB1" ; -NET "io_rx<06>" LOC = "AC1" ; -NET "io_rx<05>" LOC = "V7" ; -NET "io_rx<04>" LOC = "V6" ; -NET "io_rx<03>" LOC = "Y5" ; -NET "ADCB_2_3_p" LOC = "U7" ; -NET "ADCB_2_3_n" LOC = "U8" ; -NET "ADCB_0_1_p" LOC = "AA2" ; -NET "ADCB_0_1_n" LOC = "AA3" ; -NET "ADCA_12_13_p" LOC = "Y1" ; -NET "ADCA_12_13_n" LOC = "Y2" ; -NET "ADCA_10_11_p" LOC = "W3" ; -NET "ADCA_10_11_n" LOC = "W4" ; -NET "ADCA_8_9_p" LOC = "T7" ; -NET "ADCA_8_9_n" LOC = "U6" ; -NET "ADCA_6_7_p" LOC = "U5" ; -NET "ADCA_6_7_n" LOC = "V5" ; -NET "ADCA_4_5_p" LOC = "T10" ; -NET "ADCA_4_5_n" LOC = "T9" ; -NET "ADCA_2_3_p" LOC = "V1" ; -NET "ADCA_2_3_n" LOC = "V2" ; -NET "ADCA_0_1_p" LOC = "R8" ; -NET "ADCA_0_1_n" LOC = "R7" ; -NET "TX00_A" LOC = "P8" ; -NET "TX01_A" LOC = "P9" ; -NET "TX02_A" LOC = "R5" ; -NET "TX03_A" LOC = "R6" ; -NET "TX04_A" LOC = "P7" ; -NET "TX05_A" LOC = "P6" ; -NET "TX06_A" LOC = "T3" ; -NET "TX07_A" LOC = "T4" ; -NET "TX08_A" LOC = "R3" ; -NET "TX09_A" LOC = "R4" ; -NET "TX10_A" LOC = "R2" ; -NET "TX11_A" LOC = "N1" ; -NET "TX12_A" LOC = "N2" ; -NET "TX13_A" LOC = "N5" ; -NET "TX14_A" LOC = "N4" ; -NET "TX15_A" LOC = "M2" ; -NET "TX00_B" LOC = "M5" ; -NET "TX01_B" LOC = "M6" ; -NET "TX02_B" LOC = "M4" ; -NET "TX03_B" LOC = "M3" ; -NET "TX04_B" LOC = "M8" ; -NET "TX05_B" LOC = "M7" ; -NET "TX06_B" LOC = "L4" ; -NET "TX07_B" LOC = "L3" ; -NET "TX08_B" LOC = "K3" ; -NET "TX09_B" LOC = "K2" ; -NET "TX10_B" LOC = "K5" ; -NET "TX11_B" LOC = "K4" ; -NET "TX12_B" LOC = "M10" ; -NET "TX13_B" LOC = "M9" ; -NET "TX14_B" LOC = "J5" ; -NET "TX15_B" LOC = "J4" ; +NET "ADCA_12_p" LOC = "Y1" ; +NET "ADCA_12_n" LOC = "Y2" ; +NET "ADCA_10_p" LOC = "W3" ; +NET "ADCA_10_n" LOC = "W4" ; +NET "ADCA_8_p" LOC = "T7" ; +NET "ADCA_8_n" LOC = "U6" ; +NET "ADCA_6_p" LOC = "U5" ; +NET "ADCA_6_n" LOC = "V5" ; +NET "ADCA_4_p" LOC = "T10" ; +NET "ADCA_4_n" LOC = "T9" ; +NET "ADCA_2_p" LOC = "V1" ; +NET "ADCA_2_n" LOC = "V2" ; +NET "ADCA_0_p" LOC = "R8" ; +NET "ADCA_0_n" LOC = "R7" ; +NET "ADCB_2_p" LOC = "U7" ; +NET "ADCB_2_n" LOC = "U8" ; +NET "ADCB_0_p" LOC = "AA2" ; +NET "ADCB_0_n" LOC = "AA3" ; +NET "ADCB_4_p" LOC = "AE1" ; +NET "ADCB_4_n" LOC = "AE2" ; +NET "ADCB_6_p" LOC = "W1" ; +NET "ADCB_6_n" LOC = "W2" ; +NET "ADCB_8_p" LOC = "U3" ; +NET "ADCB_8_n" LOC = "V4" ; +NET "ADCB_10_p" LOC = "J1" ; +NET "ADCB_10_n" LOC = "K1" ; +NET "ADCB_12_p" LOC = "J3" ; +NET "ADCB_12_n" LOC = "J2" ; + +## DAC +NET "DAC_LOCK" LOC = "P4" ; +NET "DACA<0>" LOC = "P8" ; +NET "DACA<1>" LOC = "P9" ; +NET "DACA<2>" LOC = "R5" ; +NET "DACA<3>" LOC = "R6" ; +NET "DACA<4>" LOC = "P7" ; +NET "DACA<5>" LOC = "P6" ; +NET "DACA<6>" LOC = "T3" ; +NET "DACA<7>" LOC = "T4" ; +NET "DACA<8>" LOC = "R3" ; +NET "DACA<9>" LOC = "R4" ; +NET "DACA<10>" LOC = "R2" ; +NET "DACA<11>" LOC = "N1" ; +NET "DACA<12>" LOC = "N2" ; +NET "DACA<13>" LOC = "N5" ; +NET "DACA<14>" LOC = "N4" ; +NET "DACA<15>" LOC = "M2" ; +NET "DACB<0>" LOC = "M5" ; +NET "DACB<1>" LOC = "M6" ; +NET "DACB<2>" LOC = "M4" ; +NET "DACB<3>" LOC = "M3" ; +NET "DACB<4>" LOC = "M8" ; +NET "DACB<5>" LOC = "M7" ; +NET "DACB<6>" LOC = "L4" ; +NET "DACB<7>" LOC = "L3" ; +NET "DACB<8>" LOC = "K3" ; +NET "DACB<9>" LOC = "K2" ; +NET "DACB<10>" LOC = "K5" ; +NET "DACB<11>" LOC = "K4" ; +NET "DACB<12>" LOC = "M10" ; +NET "DACB<13>" LOC = "M9" ; +NET "DACB<14>" LOC = "J5" ; +NET "DACB<15>" LOC = "J4" ; + +## TX DB GPIO NET "io_tx<15>" LOC = "K6" ; NET "io_tx<14>" LOC = "L7" ; NET "io_tx<13>" LOC = "H2" ; NET "io_tx<12>" LOC = "H1" ; NET "io_tx<11>" LOC = "L10" ; NET "io_tx<10>" LOC = "L9" ; -NET "io_tx<09>" LOC = "G3" ; -NET "io_tx<08>" LOC = "F3" ; -NET "io_tx<07>" LOC = "K7" ; -NET "io_tx<06>" LOC = "J6" ; -NET "io_tx<05>" LOC = "E1" ; -NET "io_tx<04>" LOC = "F2" ; -NET "io_tx<03>" LOC = "J7" ; -NET "io_tx<02>" LOC = "H6" ; -NET "io_tx<01>" LOC = "F5" ; -NET "io_tx<00>" LOC = "G4" ; -NET "MOSI_RX_ADC" LOC = "E3" ; -NET "SCLK_RX_ADC" LOC = "F4" ; -NET "SEN_RX_ADC" LOC = "D3" ; -NET "SCLK_RX_DAC" LOC = "E4" ; -NET "SEN_RX_DAC" LOC = "K9" ; -NET "MOSI_RX_DAC" LOC = "K8" ; -NET "SCLK_RX_DB" LOC = "G6" ; -NET "MOSI_RX_DB" LOC = "H7" ; -NET "SEN_RX_DB" LOC = "B2" ; -NET "SCLK_ADC" LOC = "B1" ; -NET "MOSI_ADC" LOC = "J8" ; -NET "SEN_ADC" LOC = "J9" ; -NET "ADCB_4_5_p" LOC = "AE1" ; -NET "ADCB_4_5_n" LOC = "AE2" ; -NET "ADCB_6_7_p" LOC = "W1" ; -NET "ADCB_6_7_n" LOC = "W2" ; -NET "ADCB_8_9_p" LOC = "U3" ; -NET "ADCB_8_9_n" LOC = "V4" ; -NET "ADCB_10_11_p" LOC = "J1" ; -NET "ADCB_10_11_n" LOC = "K1" ; -NET "ADCB_12_13_p" LOC = "J3" ; -NET "ADCB_12_13_n" LOC = "J2" ; -NET "MISO_RX_DB" LOC = "H4" ; -NET "MISO_RX_ADC" LOC = "C1" ; -NET "MISO_TX_DB" LOC = "AA5" ; -NET "MISO_DAC" LOC = "Y3" ; -NET "MISO_TX_ADC" LOC = "G1" ; -NET "io_rx<02>" LOC = "R10" ; -NET "io_rx<01>" LOC = "R1" ; -NET "io_rx<00>" LOC = "M1" ; -NET "exp_user_out_p" LOC = "AF14" ; -NET "exp_user_out_n" LOC = "AE14" ; -NET "exp_time_out_p" LOC = "Y14" ; -NET "exp_time_out_n" LOC = "AA14" ; -NET "CLK_FPGA_P" LOC = "AA13" ; -NET "CLK_FPGA_N" LOC = "Y13" ; +NET "io_tx<9>" LOC = "G3" ; +NET "io_tx<8>" LOC = "F3" ; +NET "io_tx<7>" LOC = "K7" ; +NET "io_tx<6>" LOC = "J6" ; +NET "io_tx<5>" LOC = "E1" ; +NET "io_tx<4>" LOC = "F2" ; +NET "io_tx<3>" LOC = "J7" ; +NET "io_tx<2>" LOC = "H6" ; +NET "io_tx<1>" LOC = "F5" ; +NET "io_tx<0>" LOC = "G4" ; + +## RX DB GPIO +NET "io_rx<15>" LOC = "AD1" ; +NET "io_rx<14>" LOC = "AD2" ; +NET "io_rx<13>" LOC = "AC2" ; +NET "io_rx<12>" LOC = "AC3" ; +NET "io_rx<11>" LOC = "W7" ; +NET "io_rx<10>" LOC = "W6" ; +NET "io_rx<9>" LOC = "U9" ; +NET "io_rx<8>" LOC = "V8" ; +NET "io_rx<7>" LOC = "AB1" ; +NET "io_rx<6>" LOC = "AC1" ; +NET "io_rx<5>" LOC = "V7" ; +NET "io_rx<4>" LOC = "V6" ; +NET "io_rx<3>" LOC = "Y5" ; +NET "io_rx<2>" LOC = "R10" ; +NET "io_rx<1>" LOC = "R1" ; +NET "io_rx<0>" LOC = "M1" ; + +## MISC NET "leds<5>" LOC = "AF25" ; NET "leds<4>" LOC = "AE25" ; NET "leds<3>" LOC = "AF23" ; NET "leds<2>" LOC = "AE23" ; NET "leds<1>" LOC = "AB18" ; -NET "SEN_CLK" LOC = "AA18" ; -NET "MOSI_CLK" LOC = "W17" ; -NET "SCLK_CLK" LOC = "V17" ; -NET "CLK_STATUS" LOC = "AD22" ; -NET "CLK_FUNC" LOC = "AC21" ; -NET "clk_sel<0>" LOC = "AE21" ; -NET "clk_sel<1>" LOC = "AD21" ; -NET "clk_en<1>" LOC = "AA17" ; -NET "clk_en<0>" LOC = "Y17" ; -NET "SDA" LOC = "V16" ; -NET "SCL" LOC = "U16" ; -NET "TXD3" LOC = "AD20" ; -NET "TXD2" LOC = "AC20" ; -NET "TXD1" LOC = "AD19" ; -NET "debug<00>" LOC = "AC19" ; -NET "debug<01>" LOC = "AF20" ; -NET "debug<02>" LOC = "AE20" ; -NET "debug<03>" LOC = "AC16" ; -NET "debug<04>" LOC = "AB16" ; -NET "debug<05>" LOC = "AF19" ; -NET "debug<06>" LOC = "AE19" ; -NET "debug<07>" LOC = "V15" ; -NET "debug<08>" LOC = "U15" ; -NET "debug<09>" LOC = "AE17" ; +NET "FPGA_RESET" LOC = "K24" ; + +## Debug +NET "debug_clk<0>" LOC = "AA10" ; +NET "debug_clk<1>" LOC = "AD11" ; +NET "debug<0>" LOC = "AC19" ; +NET "debug<1>" LOC = "AF20" ; +NET "debug<2>" LOC = "AE20" ; +NET "debug<3>" LOC = "AC16" ; +NET "debug<4>" LOC = "AB16" ; +NET "debug<5>" LOC = "AF19" ; +NET "debug<6>" LOC = "AE19" ; +NET "debug<7>" LOC = "V15" ; +NET "debug<8>" LOC = "U15" ; +NET "debug<9>" LOC = "AE17" ; NET "debug<10>" LOC = "AD17" ; NET "debug<11>" LOC = "V14" ; NET "debug<12>" LOC = "W15" ; NET "debug<13>" LOC = "AC15" ; NET "debug<14>" LOC = "AD14" ; NET "debug<15>" LOC = "AC14" ; -NET "debug_clk<1>" LOC = "AD11" ; NET "debug<16>" LOC = "AC11" ; NET "debug<17>" LOC = "AB12" ; NET "debug<18>" LOC = "AC12" ; @@ -168,187 +148,277 @@ NET "debug<28>" LOC = "AB7" ; NET "debug<29>" LOC = "V11" ; NET "debug<30>" LOC = "U11" ; NET "debug<31>" LOC = "Y10" ; -NET "debug_clk<0>" LOC = "AA10" ; + +## UARTS +NET "TXD<3>" LOC = "AD20" ; +NET "TXD<2>" LOC = "AC20" ; +NET "TXD<1>" LOC = "AD19" ; +NET "RXD<3>" LOC = "AF17" ; +NET "RXD<2>" LOC = "AF15" ; +NET "RXD<1>" LOC = "AD12" ; + +## AD9510 +NET "CLK_STATUS" LOC = "AD22" ; +NET "CLK_FUNC" LOC = "AC21" ; +NET "clk_sel<0>" LOC = "AE21" ; +NET "clk_sel<1>" LOC = "AD21" ; +NET "clk_en<1>" LOC = "AA17" ; +NET "clk_en<0>" LOC = "Y17" ; + +## I2C +NET "SDA" LOC = "V16" ; +NET "SCL" LOC = "U16" ; + +## Timing +NET "PPS_IN" LOC = "AB6" ; +NET "PPS2_IN" LOC = "AA20" ; + +## SPI +NET "SEN_CLK" LOC = "AA18" ; +NET "MOSI_CLK" LOC = "W17" ; +NET "SCLK_CLK" LOC = "V17" ; +NET "MISO_CLK" LOC = "AC10" ; + NET "SEN_DAC" LOC = "AE7" ; NET "SCLK_DAC" LOC = "AF5" ; NET "MOSI_DAC" LOC = "AE6" ; +NET "MISO_DAC" LOC = "Y3" ; + +NET "SCLK_ADC" LOC = "B1" ; +NET "MOSI_ADC" LOC = "J8" ; +NET "SEN_ADC" LOC = "J9" ; + NET "MOSI_TX_ADC" LOC = "V10" ; NET "SEN_TX_ADC" LOC = "W10" ; NET "SCLK_TX_ADC" LOC = "AC6" ; +NET "MISO_TX_ADC" LOC = "G1" ; + NET "MOSI_TX_DAC" LOC = "AD6" ; NET "SEN_TX_DAC" LOC = "AE4" ; NET "SCLK_TX_DAC" LOC = "AF4" ; + NET "SCLK_TX_DB" LOC = "AE3" ; NET "MOSI_TX_DB" LOC = "AF3" ; NET "SEN_TX_DB" LOC = "W9" ; -NET "RXD3" LOC = "AF17" ; -NET "RXD2" LOC = "AF15" ; -NET "RXD1" LOC = "AD12" ; -NET "MISO_CLK" LOC = "AC10" ; -NET "PPS_IN" LOC = "AB6" ; -NET "PPS2_IN" LOC = "AA20" ; -NET "ser_rx_clk" LOC = "P18" ; -NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK +NET "MISO_TX_DB" LOC = "AA5" ; + +NET "MOSI_RX_ADC" LOC = "E3" ; +NET "SCLK_RX_ADC" LOC = "F4" ; +NET "SEN_RX_ADC" LOC = "D3" ; +NET "MISO_RX_ADC" LOC = "C1" ; + +NET "SCLK_RX_DAC" LOC = "E4" ; +NET "SEN_RX_DAC" LOC = "K9" ; +NET "MOSI_RX_DAC" LOC = "K8" ; + +NET "SCLK_RX_DB" LOC = "G6" ; +NET "MOSI_RX_DB" LOC = "H7" ; +NET "SEN_RX_DB" LOC = "B2" ; +NET "MISO_RX_DB" LOC = "H4" ; + +## ETH PHY NET "CLK_TO_MAC" LOC = "P26" ; -NET "GMII_TX_CLK" LOC = "P25" ; -NET "GMII_RX_CLK" LOC = "P21" ; -NET "ETH_LED" LOC = "H20" ; -NET "GMII_TXD7" LOC = "G21" ; -NET "GMII_TXD6" LOC = "C26" ; -NET "GMII_TXD5" LOC = "C25" ; -NET "GMII_TXD4" LOC = "J21" ; -NET "GMII_TXD3" LOC = "H21" ; -NET "GMII_TXD2" LOC = "D25" ; -NET "GMII_TXD1" LOC = "D24" ; -NET "GMII_TXD0" LOC = "E26" ; + +NET "GMII_TXD<7>" LOC = "G21" ; +NET "GMII_TXD<6>" LOC = "C26" ; +NET "GMII_TXD<5>" LOC = "C25" ; +NET "GMII_TXD<4>" LOC = "J21" ; +NET "GMII_TXD<3>" LOC = "H21" ; +NET "GMII_TXD<2>" LOC = "D25" ; +NET "GMII_TXD<1>" LOC = "D24" ; +NET "GMII_TXD<0>" LOC = "E26" ; NET "GMII_TX_EN" LOC = "D26" ; NET "GMII_TX_ER" LOC = "J19" ; NET "GMII_GTX_CLK" LOC = "J20" ; -NET "GMII_RXD7" LOC = "G22" ; -NET "GMII_RXD6" LOC = "K19" ; -NET "GMII_RXD5" LOC = "K18" ; -NET "GMII_RXD4" LOC = "E24" ; -NET "GMII_RXD3" LOC = "F23" ; -NET "GMII_RXD2" LOC = "L18" ; -NET "GMII_RXD1" LOC = "L17" ; -NET "GMII_RXD0" LOC = "F25" ; +NET "GMII_TX_CLK" LOC = "P25" ; + +NET "GMII_RX_CLK" LOC = "P21" ; +NET "GMII_RXD<7>" LOC = "G22" ; +NET "GMII_RXD<6>" LOC = "K19" ; +NET "GMII_RXD<5>" LOC = "K18" ; +NET "GMII_RXD<4>" LOC = "E24" ; +NET "GMII_RXD<3>" LOC = "F23" ; +NET "GMII_RXD<2>" LOC = "L18" ; +NET "GMII_RXD<1>" LOC = "L17" ; +NET "GMII_RXD<0>" LOC = "F25" ; NET "GMII_RX_DV" LOC = "F24" ; NET "GMII_RX_ER" LOC = "L20" ; NET "GMII_CRS" LOC = "K20" ; NET "GMII_COL" LOC = "G23" ; + NET "PHY_INTn" LOC = "L22" ; NET "MDIO" LOC = "K21" ; NET "MDC" LOC = "J23" ; -NET "PHY_RESET" LOC = "J22" ; +NET "PHY_RESETn" LOC = "J22" ; +NET "ETH_LED" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; + +## MIMO Interface +NET "exp_time_out_p" LOC = "Y14" ; +NET "exp_time_out_n" LOC = "AA14" ; NET "exp_time_in_p" LOC = "N18" ; NET "exp_time_in_n" LOC = "N17" ; +NET "exp_user_out_p" LOC = "AF14" ; +NET "exp_user_out_n" LOC = "AE14" ; NET "exp_user_in_p" LOC = "L24" ; NET "exp_user_in_n" LOC = "M23" ; + +## SERDES +NET "ser_enable" LOC = "R20" ; NET "ser_prbsen" LOC = "U23" ; NET "ser_loopen" LOC = "R19" ; -NET "ser_enable" LOC = "R20" ; +NET "ser_rx_en" LOC = "Y21" ; +NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK NET "ser_t<15>" LOC = "V23" ; NET "ser_t<14>" LOC = "U22" ; NET "ser_t<13>" LOC = "V24" ; NET "ser_t<12>" LOC = "V25" ; NET "ser_t<11>" LOC = "W23" ; NET "ser_t<10>" LOC = "V22" ; -NET "ser_t<09>" LOC = "T18" ; -NET "ser_t<08>" LOC = "T17" ; -NET "ser_t<07>" LOC = "Y24" ; -NET "ser_t<06>" LOC = "Y25" ; -NET "ser_t<05>" LOC = "U21" ; -NET "ser_t<04>" LOC = "T20" ; -NET "ser_t<03>" LOC = "Y22" ; -NET "ser_t<02>" LOC = "Y23" ; -NET "ser_t<01>" LOC = "U19" ; -NET "ser_t<00>" LOC = "U18" ; +NET "ser_t<9>" LOC = "T18" ; +NET "ser_t<8>" LOC = "T17" ; +NET "ser_t<7>" LOC = "Y24" ; +NET "ser_t<6>" LOC = "Y25" ; +NET "ser_t<5>" LOC = "U21" ; +NET "ser_t<4>" LOC = "T20" ; +NET "ser_t<3>" LOC = "Y22" ; +NET "ser_t<2>" LOC = "Y23" ; +NET "ser_t<1>" LOC = "U19" ; +NET "ser_t<0>" LOC = "U18" ; NET "ser_tkmsb" LOC = "AA24" ; NET "ser_tklsb" LOC = "AA25" ; +NET "ser_rx_clk" LOC = "P18" ; NET "ser_r<15>" LOC = "V21" ; NET "ser_r<14>" LOC = "U20" ; NET "ser_r<13>" LOC = "AA22" ; NET "ser_r<12>" LOC = "AA23" ; NET "ser_r<11>" LOC = "V18" ; NET "ser_r<10>" LOC = "V19" ; -NET "ser_r<09>" LOC = "AB23" ; -NET "ser_r<08>" LOC = "AC26" ; -NET "ser_r<07>" LOC = "AB26" ; -NET "ser_r<06>" LOC = "AD26" ; -NET "ser_r<05>" LOC = "AC25" ; -NET "ser_r<04>" LOC = "W20" ; -NET "ser_r<03>" LOC = "W21" ; -NET "ser_r<02>" LOC = "AC23" ; -NET "ser_r<01>" LOC = "AC24" ; -NET "ser_r<00>" LOC = "AE26" ; +NET "ser_r<9>" LOC = "AB23" ; +NET "ser_r<8>" LOC = "AC26" ; +NET "ser_r<7>" LOC = "AB26" ; +NET "ser_r<6>" LOC = "AD26" ; +NET "ser_r<5>" LOC = "AC25" ; +NET "ser_r<4>" LOC = "W20" ; +NET "ser_r<3>" LOC = "W21" ; +NET "ser_r<2>" LOC = "AC23" ; +NET "ser_r<1>" LOC = "AC24" ; +NET "ser_r<0>" LOC = "AE26" ; NET "ser_rkmsb" LOC = "AD25" ; NET "ser_rklsb" LOC = "Y20" ; -NET "ser_rx_en" LOC = "Y21" ; -NET "FPGA_RESET" LOC = "K24" ; -NET "RAM_D<17>" LOC = "F7" ; -NET "RAM_D<16>" LOC = "E7" ; -NET "RAM_D<15>" LOC = "G9" ; -NET "RAM_D<14>" LOC = "H9" ; -NET "RAM_D<13>" LOC = "G10" ; -NET "RAM_D<12>" LOC = "H10" ; -NET "RAM_D<11>" LOC = "A4" ; -NET "RAM_D<10>" LOC = "B4" ; -NET "RAM_D<09>" LOC = "C5" ; -NET "RAM_D<08>" LOC = "D6" ; -NET "RAM_D<07>" LOC = "J11" ; -NET "RAM_D<06>" LOC = "K11" ; -NET "RAM_D<05>" LOC = "B7" ; -NET "RAM_D<04>" LOC = "C7" ; -NET "RAM_D<03>" LOC = "B6" ; -NET "RAM_D<02>" LOC = "C6" ; -NET "RAM_D<01>" LOC = "C8" ; -NET "RAM_D<00>" LOC = "D8" ; -NET "RAM_ZZ" LOC = "J12" ; -NET "RAM_BWn<3>" LOC = "D9" ; -NET "RAM_BWn<2>" LOC = "A9" ; -NET "RAM_BWn<1>" LOC = "B9" ; -NET "RAM_BWn<0>" LOC = "G12" ; -NET "RAM_LDn" LOC = "H12" ; -NET "RAM_OEn" LOC = "C10" ; -NET "RAM_WEn" LOC = "D10" ; -NET "RAM_CLK" LOC = "A10" ; -NET "RAM_CENn" LOC = "B10" ; -NET "RAM_A<00>" LOC = "C11" ; -NET "RAM_A<01>" LOC = "E12" ; -NET "RAM_A<02>" LOC = "F12" ; -NET "RAM_A<03>" LOC = "D13" ; -NET "RAM_A<04>" LOC = "C12" ; -NET "RAM_A<05>" LOC = "A12" ; -NET "RAM_A<06>" LOC = "B12" ; -NET "RAM_A<07>" LOC = "E14" ; -NET "RAM_A<08>" LOC = "F14" ; -NET "RAM_A<09>" LOC = "B15" ; -NET "RAM_A<10>" LOC = "A15" ; -NET "RAM_A<11>" LOC = "D16" ; -NET "RAM_A<12>" LOC = "C15" ; -NET "RAM_A<13>" LOC = "D17" ; -NET "RAM_A<14>" LOC = "C16" ; -NET "RAM_A<15>" LOC = "F15" ; -NET "RAM_A<16>" LOC = "C17" ; -NET "RAM_A<17>" LOC = "B17" ; -NET "RAM_A<18>" LOC = "B18" ; -NET "RAM_A<19>" LOC = "A18" ; -NET "RAM_A<20>" LOC = "D18" ; -NET "RAM_D<35>" LOC = "K16" ; -NET "RAM_D<34>" LOC = "D20" ; -NET "RAM_D<33>" LOC = "C20" ; -NET "RAM_D<32>" LOC = "E21" ; -NET "RAM_D<31>" LOC = "D21" ; -NET "RAM_D<30>" LOC = "C21" ; -NET "RAM_D<29>" LOC = "B21" ; -NET "RAM_D<28>" LOC = "H17" ; -NET "RAM_D<27>" LOC = "G17" ; -NET "RAM_D<26>" LOC = "B23" ; -NET "RAM_D<25>" LOC = "A22" ; -NET "RAM_D<24>" LOC = "D23" ; -NET "RAM_D<23>" LOC = "C23" ; -NET "RAM_D<22>" LOC = "D22" ; -NET "RAM_D<21>" LOC = "C22" ; -NET "RAM_D<20>" LOC = "F19" ; -NET "RAM_D<19>" LOC = "G20" ; -NET "RAM_D<18>" LOC = "F20" ; -#NET "unnamed_net20" LOC = "V20" ; # SUSPEND -NET "PROG_B" LOC = "A2" ; -NET "PUDC_B" LOC = "G8" ; -NET "DONE" LOC = "AB21" ; + +## SRAM +NET "RAM_D<35>" LOC = "K16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<34>" LOC = "D20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<33>" LOC = "C20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<32>" LOC = "E21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<31>" LOC = "D21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<30>" LOC = "C21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<29>" LOC = "B21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<28>" LOC = "H17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<27>" LOC = "G17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<26>" LOC = "B23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<25>" LOC = "A22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<24>" LOC = "D23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<23>" LOC = "C23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<22>" LOC = "D22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<21>" LOC = "C22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<20>" LOC = "F19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<19>" LOC = "G20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<18>" LOC = "F20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<17>" LOC = "F7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<16>" LOC = "E7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<15>" LOC = "G9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<14>" LOC = "H9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<13>" LOC = "G10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<12>" LOC = "H10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<11>" LOC = "A4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<10>" LOC = "B4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<9>" LOC = "C5" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<8>" LOC = "D6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<7>" LOC = "J11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<6>" LOC = "K11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<5>" LOC = "B7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<4>" LOC = "C7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<3>" LOC = "B6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<2>" LOC = "C6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<1>" LOC = "C8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<0>" LOC = "D8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<0>" LOC = "C11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<1>" LOC = "E12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<2>" LOC = "F12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<3>" LOC = "D13" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<4>" LOC = "C12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<5>" LOC = "A12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<6>" LOC = "B12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<7>" LOC = "E14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<8>" LOC = "F14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<9>" LOC = "B15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<10>" LOC = "A15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<11>" LOC = "D16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<12>" LOC = "C15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<13>" LOC = "D17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<14>" LOC = "C16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<15>" LOC = "F15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<16>" LOC = "C17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<17>" LOC = "B17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<18>" LOC = "B18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<19>" LOC = "A18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<20>" LOC = "D18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<3>" LOC = "D9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<2>" LOC = "A9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<1>" LOC = "B9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<0>" LOC = "G12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_ZZ" LOC = "J12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_LDn" LOC = "H12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_OEn" LOC = "C10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_WEn" LOC = "D10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_CENn" LOC = "B10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_CLK" LOC = "A10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; + +## SPI Flash NET "flash_miso" LOC = "AF24" ; NET "flash_clk" LOC = "AE24" ; -NET "INIT_B" LOC = "AA15" ; NET "flash_mosi" LOC = "AB15" ; +NET "flash_cs" LOC = "AA7" ; + +## MISC FPGA, unused for now +#NET "PROG_B" LOC = "A2" ; +#NET "PUDC_B" LOC = "G8" ; +#NET "DONE" LOC = "AB21" ; +#NET "INIT_B" LOC = "AA15" ; + + #NET "unnamed_net19" LOC = "AE9" ; # VS1 #NET "unnamed_net18" LOC = "AF9" ; # VS0 #NET "unnamed_net17" LOC = "AA12" ; # VS2 #NET "unnamed_net16" LOC = "Y7" ; # M2 -NET "flash_cs" LOC = "AA7" ; #NET "unnamed_net15" LOC = "AC4" ; # M1 #NET "unnamed_net14" LOC = "AD4" ; # M0 #NET "unnamed_net13" LOC = "D4" ; # TMS #NET "unnamed_net12" LOC = "E23" ; # TDO #NET "unnamed_net11" LOC = "G7" ; # TDI #NET "unnamed_net10" LOC = "A25" ; # TCK +#NET "unnamed_net20" LOC = "V20" ; # SUSPEND + + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + +TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; + +#NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; + +#NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; + diff --git a/fpga/usrp2/top/u2plus/u2plus.v b/fpga/usrp2/top/u2plus/u2plus.v index e95445867..270655a8d 100644 --- a/fpga/usrp2/top/u2plus/u2plus.v +++ b/fpga/usrp2/top/u2plus/u2plus.v @@ -1,48 +1,96 @@ `timescale 1ns / 1ps +//`define DCM_FOR_RAMCLK ////////////////////////////////////////////////////////////////////////////////// module u2plus ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + + // ADC + input ADC_clkout_p, input ADC_clkout_n, + input ADCA_12_p, input ADCA_12_n, + input ADCA_10_p, input ADCA_10_n, + input ADCA_8_p, input ADCA_8_n, + input ADCA_6_p, input ADCA_6_n, + input ADCA_4_p, input ADCA_4_n, + input ADCA_2_p, input ADCA_2_n, + input ADCA_0_p, input ADCA_0_n, + input ADCB_12_p, input ADCB_12_n, + input ADCB_10_p, input ADCB_10_n, + input ADCB_8_p, input ADCB_8_n, + input ADCB_6_p, input ADCB_6_n, + input ADCB_4_p, input ADCB_4_n, + input ADCB_2_p, input ADCB_2_n, + input ADCB_0_p, input ADCB_0_n, + + // DAC + output reg [15:0] DACA, + output reg [15:0] DACB, + input DAC_LOCK, // unused for now + + // DB IO Pins + inout [15:0] io_tx, + inout [15:0] io_rx, + // Misc, debug - output [4:0] leds, // LED4 is shared w/INIT_B - input [3:0] dipsw, - output [31:0] debug, + output [5:1] leds, // LED4 is shared w/INIT_B + input FPGA_RESET, output [1:0] debug_clk, - output uart_tx_o, - input uart_rx_i, - - // Expansion - input exp_pps_in_p, // Diff - input exp_pps_in_n, // Diff - output exp_pps_out_p, // Diff - output exp_pps_out_n, // Diff + output [31:0] debug, + output [3:1] TXD, input [3:1] RXD, // UARTs + //input [3:0] dipsw, // Forgot DIP Switches... - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input CLK_FUNC, // FIXME is an input to control the 9510 + input CLK_STATUS, + + inout SCL, inout SDA, // I2C + + // PPS + input PPS_IN, input PPS2_IN, + + // SPI + output SEN_CLK, output SCLK_CLK, output MOSI_CLK, input MISO_CLK, + output SEN_DAC, output SCLK_DAC, output MOSI_DAC, input MISO_DAC, + output SEN_ADC, output SCLK_ADC, output MOSI_ADC, + output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, + output SEN_TX_DAC, output SCLK_TX_DAC, output MOSI_TX_DAC, + output SEN_TX_ADC, output SCLK_TX_ADC, output MOSI_TX_ADC, input MISO_TX_ADC, + output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, + output SEN_RX_DAC, output SCLK_RX_DAC, output MOSI_RX_DAC, + output SEN_RX_ADC, output SCLK_RX_ADC, output MOSI_RX_ADC, input MISO_RX_ADC, + + // GigE PHY + input CLK_TO_MAC, - // GMII-TX output reg [7:0] GMII_TXD, output reg GMII_TX_EN, output reg GMII_TX_ER, output GMII_GTX_CLK, input GMII_TX_CLK, // 100mbps clk - // GMII-RX - input [7:0] GMII_RXD, input GMII_RX_CLK, + input [7:0] GMII_RXD, input GMII_RX_DV, input GMII_RX_ER, + input GMII_COL, + input GMII_CRS, - // GMII-Management + input PHY_INTn, // open drain inout MDIO, output MDC, - input PHY_INTn, // open drain output PHY_RESETn, - input PHY_CLK, // possibly use on-board osc - input clk_to_mac, - output eth_led, + output ETH_LED, + +// input POR, + + // Expansion + input exp_time_in_p, input exp_time_in_n, // Diff + output exp_time_out_p, output exp_time_out_n, // Diff + input exp_user_in_p, input exp_user_in_n, // Diff + output exp_user_out_p, output exp_user_out_n, // Diff // SERDES output ser_enable, @@ -59,75 +107,18 @@ module u2plus input [15:0] ser_r, input ser_rklsb, input ser_rkmsb, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_oen_a, - output adc_pdn_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_oen_b, - output adc_pdn_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - input dac_lock, // unused for now - - // I2C - inout SCL, - inout SDA, - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Clocks - input clk_fpga_p, // Diff - input clk_fpga_n, // Diff - input pps_in, - input POR, + // SRAM + inout [35:0] RAM_D, + output [20:0] RAM_A, + output [3:0] RAM_BWn, + output RAM_ZZ, + output RAM_LDn, + output RAM_OEn, + output RAM_WEn, + output RAM_CENn, + output RAM_CLK, - // AD9510 SPI - output sclk, - output sen_clk, - output sdi, - input sdo, - - // TX side SPI -- tx_db, tx_adc, tx_dac, 9777 - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output mosi_tx, - input miso_dac, - input miso_tx_db, - input miso_tx_adc, - output sclk_tx, - - // RX side SPI - output sen_rx_db, - output sclk_rx_db, - input sdo_rx_db, - output sdi_rx_db, - - output sen_rx_adc, - output sclk_rx_adc, - input sdo_rx_adc, - output sdi_rx_adc, - - output sen_rx_dac, - output sclk_rx_dac, - output sdi_rx_dac, - - // DB IO Pins - inout [15:0] io_tx, - inout [15:0] io_rx, - // SPI Flash output flash_cs, output flash_clk, @@ -135,38 +126,63 @@ module u2plus input flash_miso ); + wire CLK_TO_MAC_int, CLK_TO_MAC_int2; + IBUFG phyclk (.O(CLK_TO_MAC_int), .I(CLK_TO_MAC)); + BUFG phyclk2 (.O(CLK_TO_MAC_int2), .I(CLK_TO_MAC_int)); + // FPGA-specific pins connections - wire aux_clk = PHY_CLK; - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - wire exp_pps_in; - IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); - defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; + + wire exp_user_in; + IBUFDS exp_user_in_pin (.O(exp_user_in),.I(exp_user_in_p),.IB(exp_user_in_n)); + defparam exp_user_in_pin.IOSTANDARD = "LVDS_25"; - wire exp_pps_out; - OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); - defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; + wire exp_user_out; + OBUFDS exp_user_out_pin (.O(exp_user_out_p),.OB(exp_user_out_n),.I(exp_user_out)); + defparam exp_user_out_pin.IOSTANDARD = "LVDS_25"; reg [5:0] clock_ready_d; - always @(posedge aux_clk) + always @(posedge clk_fpga) clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; - wire dcm_rst = ~&clock_ready_d & |clock_ready_d; - wire clk_muxed = clock_ready ? clk_fpga : aux_clk; - - wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; - assign adc_oen_a = ~adc_oe_a; - assign adc_oen_b = ~adc_oe_b; - assign adc_pdn_a = ~adc_on_a; - assign adc_pdn_b = ~adc_on_b; + // ADC A is inverted on the schematic to facilitate a clean layout + // We account for that here by inverting it +`ifdef LVDS + wire [13:0] adc_a, adc_a_inv, adc_b; + capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds + (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), + .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, + {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), + .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, + {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), + .out({adc_a_inv,adc_b})); + assign adc_a = ~adc_a_inv; +`else + reg [13:0] adc_a, adc_b; + always @(posedge dsp_clk) + begin + adc_a <= ~{ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, + ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n }; + adc_b <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, + ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n }; + end +`endif // !`ifdef LVDS + // Handle Clocks DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_muxed), + .CLKIN(clk_fpga), .DSSEN(0), .PSCLK(0), .PSEN(0), @@ -180,7 +196,7 @@ module u2plus .CLK2X180(), .CLK90(), .CLK180(), - .CLK270(), + .CLK270(clk270_100), .LOCKED(LOCKED_OUT), .PSDONE(), .STATUS()); @@ -202,28 +218,43 @@ module u2plus BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + // Create clock for external SRAM thats -90degree phase to DSPCLK (i.e) 2nS earlier at 100MHz. + BUFG clk270_100_buf_i1 (.I(clk270_100), + .O(clk270_100_buf)); + OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), + .C0(clk270_100_buf), + .C1(~clk270_100_buf), + .CE(1'b1), + .D0(1'b1), + .D1(1'b0), + .R(1'b0), + .S(1'b0)); + // I2C -- Don't use external transistors for open drain, the FPGA implements this IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); // LEDs are active low outputs - wire [4:0] leds_int; - assign leds = ~leds_int; // drive low to turn on leds + wire [5:0] leds_int; + assign {ETH_LED,leds} = {6'b011111 ^ leds_int}; // drive low to turn on leds // SPI - wire miso, mosi, sclk_int; - assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; - assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; - - assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | - (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | - (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); + wire miso, mosi, sclk; + assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; + assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; + + assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | + (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | + (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; wire [7:0] GMII_TXD_unreg; wire GMII_GTX_CLK_int; @@ -281,16 +312,53 @@ module u2plus .S(0) // Synchronous preset input ); */ - u2_core u2_core(.dsp_clk (dsp_clk), + + + // + // Instantiate IO for Bidirectional bus to SRAM + // + wire [35:0] RAM_D_pi; + wire [35:0] RAM_D_po; + wire RAM_D_poe; + + genvar i; + + generate + for (i=0;i<36;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi[i]), + .I(RAM_D_po[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe) + ); + end // block: gen_RAM_D_IO + endgenerate + + + + wire [15:0] dac_a_int, dac_b_int; + // DAC A and B are swapped in schematic to facilitate clean layout + // DAC A is also inverted in schematic to facilitate clean layout + always @(negedge dsp_clk) DACA <= ~dac_b_int; + always @(negedge dsp_clk) DACB <= dac_a_int; + + u2plus_core u2p_c(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), + .clk_to_mac (CLK_TO_MAC_int2), + .pps_in (PPS_IN), .leds (leds_int), .debug (debug[31:0]), .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), + .exp_pps_in (exp_time_in), + .exp_pps_out (exp_time_out), .GMII_COL (GMII_COL), .GMII_CRS (GMII_CRS), .GMII_TXD (GMII_TXD_unreg[7:0]), @@ -306,7 +374,6 @@ module u2plus .MDC (MDC), .PHY_INTn (PHY_INTn), .PHY_RESETn (PHY_RESETn), - .PHY_CLK (PHY_CLK), .ser_enable (ser_enable), .ser_prbsen (ser_prbsen), .ser_loopen (ser_loopen), @@ -319,22 +386,16 @@ module u2plus .ser_r (ser_r_int[15:0]), .ser_rklsb (ser_rklsb_int), .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), + .adc_ovf_a (1'b0), + .adc_on_a (), + .adc_oe_a (), .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (dac_a[15:0]), - .dac_b (dac_b[15:0]), + .adc_ovf_b (1'b0), + .adc_on_b (), + .adc_oe_b (), + .dac_a (dac_a_int[15:0]), + .dac_b (dac_b_int[15:0]), .scl_pad_i (scl_pad_i), .scl_pad_o (scl_pad_o), .scl_pad_oen_o (scl_pad_oen_o), @@ -345,33 +406,45 @@ module u2plus .clk_sel (clk_sel[1:0]), .clk_func (clk_func), .clk_status (clk_status), - .sclk (sclk_int), + .sclk (sclk), .mosi (mosi), .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), + .sen_clk (SEN_CLK), + .sen_dac (SEN_DAC), + .sen_adc (SEN_ADC), + .sen_tx_db (SEN_TX_DB), + .sen_tx_adc (SEN_TX_ADC), + .sen_tx_dac (SEN_TX_DAC), + .sen_rx_db (SEN_RX_DB), + .sen_rx_adc (SEN_RX_ADC), + .sen_rx_dac (SEN_RX_DAC), .io_tx (io_tx[15:0]), .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), + .RAM_D_po (RAM_D_po), + .RAM_D_pi (RAM_D_pi), + .RAM_D_poe (RAM_D_poe), .RAM_A (RAM_A), .RAM_CE1n (RAM_CE1n), .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), .RAM_WEn (RAM_WEn), .RAM_OEn (RAM_OEn), .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - //.uart_rx_i (uart_rx_i), - .uart_rx_i (), + .uart_tx_o (TXD[3:1]), + .uart_rx_i ({1'b1,RXD[3:1]}), .uart_baud_o (), .sim_mode (1'b0), - .clock_divider (2) + .clock_divider (2), + .button (FPGA_RESET), + .spiflash_cs (flash_cs), + .spiflash_clk (flash_clk), + .spiflash_miso (flash_miso), + .spiflash_mosi (flash_mosi) ); + + // Drive low so that RAM does not sleep. + assign RAM_ZZ = 0; + // Byte Writes are qualified by the global write enable + // Always do 36bit operations to extram. + assign RAM_BWn = 4'b0000; endmodule // u2plus diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v new file mode 100644 index 000000000..8426826e2 --- /dev/null +++ b/fpga/usrp2/top/u2plus/u2plus_core.v @@ -0,0 +1,696 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2plus_core + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_pps_in, + output exp_pps_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_adc, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + input [35:0] RAM_D_pi, + output [35:0] RAM_D_po, + output RAM_D_poe, + output [20:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output [3:0] uart_tx_o, + input [3:0] uart_rx_i, + output [3:0] uart_baud_o, + input sim_mode, + input [3:0] clock_divider, + input button, + + output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi + ); + + localparam SR_BUF_POOL = 64; // Uses 1 reg + localparam SR_UDP_SM = 96; // 64 regs + localparam SR_RX_DSP = 160; // 16 + localparam SR_RX_CTRL = 176; // 16 + localparam SR_TIME64 = 192; // 3 + localparam SR_SIMTIMER = 198; // 2 + localparam SR_TX_DSP = 208; // 16 + localparam SR_TX_CTRL = 224; // 16 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + localparam DSP_TX_FIFOSIZE = 10; + localparam DSP_RX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 10; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? + + wire [7:0] set_addr, set_addr_dsp; + wire [31:0] set_data, set_data_dsp; + wire set_stb, set_stb_dsp; + + wire wb_rst, dsp_rst; + + wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; + wire proc_int, overrun, underrun; + wire [3:0] uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up; + wire epoch; + wire [31:0] irq; + wire [63:0] vita_time; + wire run_rx, run_tx; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; + + wb_1master #(.decode_w(8), + .s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000), // 0-8K, Boot RAM + .s1_addr(8'b0100_0000),.s1_mask(8'b1100_0000), // 16K-32K, Buffer Pool + .s2_addr(8'b0011_0000),.s2_mask(8'b1111_1111), // SPI + .s3_addr(8'b0011_0001),.s3_mask(8'b1111_1111), // I2C + .s4_addr(8'b0011_0010),.s4_mask(8'b1111_1111), // GPIO + .s5_addr(8'b0011_0011),.s5_mask(8'b1111_1111), // Readback + .s6_addr(8'b0011_0100),.s6_mask(8'b1111_1111), // Ethernet MAC + .s7_addr(8'b0010_0000),.s7_mask(8'b1111_0000), // 8-12K, Settings Bus (only uses 1K) + .s8_addr(8'b0011_0101),.s8_mask(8'b1111_1111), // PIC + .s9_addr(8'b0011_0110),.s9_mask(8'b1111_1111), // Unused + .sa_addr(8'b0011_0111),.sa_mask(8'b1111_1111), // UART + .sb_addr(8'b0011_1000),.sb_mask(8'b1111_1111), // ATR + .sc_addr(8'b0011_1001),.sc_mask(8'b1111_1111), // Unused + .sd_addr(8'b0011_1010),.sd_mask(8'b1111_1111), // ICAP + .se_addr(8'b0011_1011),.se_mask(8'b1111_1111), // SPI Flash + .sf_addr(8'b1000_0000),.sf_mask(8'b1000_0000), // 32-64K, Main RAM + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + + // ///////////////////////////////////////////////////////////////////////// + // Processor + wire [31:0] if_dat; + wire [15:0] if_adr; + + aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) + aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), + // Instruction Wishbone bus to I-RAM + .if_adr(if_adr), + .if_dat(if_dat), + // Data Wishbone bus to system bus fabric + .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), + .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + // Interrupts and exceptions + .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + assign bus_error = m0_err | m0_rty; + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone + // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone + // I-port connects directly to processor + + wire [31:0] if_dat_boot, if_dat_main; + assign if_dat = if_adr[15] ? if_dat_main : if_dat_boot; + + bootram bootram(.clk(wb_clk), .reset(wb_rst), + .if_adr(if_adr[12:0]), .if_data(if_dat_boot), + .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); + +////blinkenlights v0.1 +//defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; +//defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; + +`include "bootloader.rmi" + + ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(32768)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .if_adr(if_adr[14:0]), .if_data(if_dat_main), + .dwb_adr_i(sf_adr[14:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), + .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .status(status),.sys_int_o(buffer_int), + + .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), + .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), + + // Write Interfaces + .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), + .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), + .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), + .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), + // Read Interfaces + .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), + .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), + .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), + .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) + ); + + wire [31:0] status_enc; + priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio({io_tx,io_rx}) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + reg [31:0] cycle_count; + always @(posedge wb_clk) + if(wb_rst) + cycle_count <= 0; + else + cycle_count <= cycle_count + 1; + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = 32'd3; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), + .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + wire [18:0] rx_f19_data, tx_f19_data; + wire rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy; + + simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 + (.clk125(clk_to_mac), .reset(wb_rst), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .sys_clk(dsp_clk), + .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), + .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), + .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), + .mdio(MDIO), .mdc(MDC), + .debug(debug_mac)); + + wire [35:0] udp_tx_data, udp_rx_data; + wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy; + + udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), + .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), + .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy), + .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), + .debug(debug_udp) ); + + wire [35:0] tx_err_data, udp1_tx_data; + wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy; + + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), + .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy)); + + fifo36_mux #(.prio(0)) mux_err_stream + (.clk(dsp_clk), .reset(dsp_reset), .clear(0), + .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy), + .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), + .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + settings_bus_crossclock settings_bus_crossclock + (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), + .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(serdes_outs),.changed()); + setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(adc_outs),.changed()); + setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phy_reset),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0}; + + setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(led_sw),.changed()); + + setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110)) + sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + // Pass interrupts on dsp_clk to wb_clk. These need edge triggering in the pic + wire underrun_wb, overrun_wb, pps_wb; + + oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); + oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb)); + oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); + + assign irq= {{8'b0}, + {uart_tx_int[3:0], uart_rx_int[3:0]}, + {2'b0, button, periodic_int, clk_status, serdes_link_up, 2'b00}, + {pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + // No longer used, replaced with simple_timer below + assign s9_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // Simple Timer interrupts + + simple_timer #(.BASE(SR_SIMTIMER)) simple_timer + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .onetime_int(onetime_int), .periodic_int(periodic_int)); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + quad_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[6:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), + .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), + .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + // No longer used, see time_64bit. Still need to handle mimo time, though + assign sc_ack = 0; + + // ///////////////////////////////////////////////////////////////////////// + // ICAP for reprogramming the FPGA, Slave #13 (D) + + s3a_icap_wb s3a_icap_wb + (.clk(wb_clk), .reset(wb_rst), .cyc_i(sd_cyc), .stb_i(sd_stb), + .we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI for Flash -- Slave #14 (E) + spi_top flash_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(se_adr[4:0]),.wb_dat_i(se_dat_o), + .wb_dat_o(se_dat_i),.wb_sel_i(se_sel),.wb_we_i(se_we),.wb_stb_i(se_stb), + .wb_cyc_i(se_cyc),.wb_ack_o(se_ack),.wb_err_o(se_err),.wb_int_o(spiflash_int), + .ss_pad_o(spiflash_cs), + .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx_data; + wire [35:0] rx1_data; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + wire [31:0] vrc_debug; + wire clear_rx; + + setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx)); + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), .overrun(overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), + .debug_rx(vrc_debug)); + + wire [3:0] vita_state; + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), + .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vita_state) ); + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), + .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [35:0] tx_data; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; + wire clear_tx; + + setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + + assign RAM_A[20:18] = 3'b0; + + ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18)) + ext_fifo_i1 + (.int_clk(dsp_clk), + .ext_clk(dsp_clk), + .rst(dsp_rst | clear_tx), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A[17:0]), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), + .src_rdy_i(rd1_ready_o), + .dst_rdy_o(rd1_ready_i), + .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), + .src_rdy_o(tx_src_rdy), + .dst_rdy_i(tx_dst_rdy), + .debug(debug_extfifo), + .debug2(debug_extfifo2) ); + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(dac_a),.dac_b(dac_b), + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + + assign dsp_rst = wb_rst; + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit + (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; // debug_extfifo; + assign debug_gpio_0 = 32'd0; + assign debug_gpio_1 = 32'd0; + +endmodule // u2_core diff --git a/fpga/usrp2/vrt/gen_context_pkt.v b/fpga/usrp2/vrt/gen_context_pkt.v index 0eb035f3e..bf83aeae5 100644 --- a/fpga/usrp2/vrt/gen_context_pkt.v +++ b/fpga/usrp2/vrt/gen_context_pkt.v @@ -7,8 +7,7 @@ module gen_context_pkt input [31:0] streamid, input [63:0] vita_time, input [31:0] message, - input [31:0] seqnum0, - input [31:0] seqnum1, + input [31:0] seqnum, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); localparam CTXT_IDLE = 0; @@ -19,9 +18,8 @@ module gen_context_pkt localparam CTXT_TICS = 5; localparam CTXT_TICS2 = 6; localparam CTXT_MESSAGE = 7; - localparam CTXT_FLOWCTRL0 = 8; - localparam CTXT_FLOWCTRL1 = 9; - localparam CTXT_DONE = 10; + localparam CTXT_FLOWCTRL = 8; + localparam CTXT_DONE = 9; reg [33:0] data_int; wire src_rdy_int, dst_rdy_int; @@ -36,11 +34,12 @@ module gen_context_pkt else if(trigger) stored_message <= message; - else if(ctxt_state == CTXT_FLOWCTRL1) + else if(ctxt_state == CTXT_DONE) stored_message <= 0; - + + // Don't want to clear most of this to avoid getting stuck with a half packet in the pipe always @(posedge clk) - if(reset | clear) + if(reset) begin ctxt_state <= CTXT_IDLE; seqno <= 0; @@ -72,19 +71,18 @@ module gen_context_pkt always @* case(ctxt_state) CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd32 }; - CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd8 }; + CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 }; CTXT_STREAMID : data_int <= { 2'b00, streamid }; CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; CTXT_TICS : data_int <= { 2'b00, 32'd0 }; CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] }; CTXT_MESSAGE : data_int <= { 2'b00, message }; - CTXT_FLOWCTRL0 : data_int <= { 2'b00, seqnum0 }; - CTXT_FLOWCTRL1 : data_int <= { 2'b10, seqnum1 }; + CTXT_FLOWCTRL : data_int <= { 2'b10, seqnum }; default : data_int <= {2'b00, 32'b00}; endcase // case (ctxt_state) fifo_short #(.WIDTH(34)) ctxt_fifo - (.clk(clk), .reset(reset), .clear(clear), + (.clk(clk), .reset(reset), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); assign data_o[35:34] = 2'b00; diff --git a/fpga/usrp2/vrt/vita_rx_control.v b/fpga/usrp2/vrt/vita_rx_control.v index 93673d292..0769f3a24 100644 --- a/fpga/usrp2/vrt/vita_rx_control.v +++ b/fpga/usrp2/vrt/vita_rx_control.v @@ -9,7 +9,7 @@ module vita_rx_control output overrun, // To vita_rx_framer - output [4+64+WIDTH-1:0] sample_fifo_o, + output [5+64+WIDTH-1:0] sample_fifo_o, output sample_fifo_src_rdy_o, input sample_fifo_dst_rdy_i, @@ -25,16 +25,14 @@ module vita_rx_control wire [63:0] new_time; wire [31:0] new_command; - wire sc_pre1, clear_int, clear_reg; + wire sc_pre1; - assign clear_int = clear | clear_reg; - wire [63:0] rcvtime_pre; reg [63:0] rcvtime; wire [28:0] numlines_pre; wire send_imm_pre, chain_pre, reload_pre; reg send_imm, chain, reload; - wire full_ctrl, read_ctrl, empty_ctrl, write_ctrl; + wire read_ctrl, not_empty_ctrl, write_ctrl; reg sc_pre2; wire [33:0] fifo_line; reg [28:0] lines_left, lines_total; @@ -54,21 +52,22 @@ module vita_rx_control (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(new_time[31:0]),.changed(sc_pre1)); - setting_reg #(.my_addr(BASE+3)) sr_clear - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_reg)); - // FIFO to store commands sent from the settings bus always @(posedge clk) - sc_pre2 <= sc_pre1; + if(reset | clear) + sc_pre2 <= 0; + else + sc_pre2 <= sc_pre1; + assign write_ctrl = sc_pre1 & ~sc_pre2; wire [4:0] command_queue_len; - shortfifo #(.WIDTH(96)) commandfifo - (.clk(clk),.rst(reset),.clear(clear_int), - .datain({new_command,new_time}), .write(write_ctrl&~full_ctrl), .full(full_ctrl), + + fifo_short #(.WIDTH(96)) commandfifo + (.clk(clk),.reset(reset),.clear(clear), + .datain({new_command,new_time}), .src_rdy_i(write_ctrl), .dst_rdy_o(), .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}), - .read(read_ctrl), .empty(empty_ctrl), + .src_rdy_o(not_empty_ctrl), .dst_rdy_i(read_ctrl), .occupied(command_queue_len), .space() ); reg [33:0] pkt_fifo_line; @@ -79,20 +78,23 @@ module vita_rx_control localparam IBS_OVERRUN = 4; localparam IBS_BROKENCHAIN = 5; localparam IBS_LATECMD = 6; - - wire signal_cmd_done = (lines_left == 1) & (~chain | (~empty_ctrl & (numlines_pre==0))); + localparam IBS_ZEROLEN = 7; + + wire signal_cmd_done = (lines_left == 1) & (~chain | (not_empty_ctrl & (numlines_pre==0))); wire signal_overrun = (ibs_state == IBS_OVERRUN); wire signal_brokenchain = (ibs_state == IBS_BROKENCHAIN); wire signal_latecmd = (ibs_state == IBS_LATECMD); + wire signal_zerolen = (ibs_state == IBS_ZEROLEN); // Buffer of samples for while we're writing the packet headers - wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done}; + wire [4:0] flags = {signal_zerolen,signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done}; wire attempt_sample_write = ((run & strobe) | (ibs_state==IBS_OVERRUN) | - (ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD)); + (ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD) | + (ibs_state==IBS_ZEROLEN)); - fifo_short #(.WIDTH(4+64+WIDTH)) rx_sample_fifo - (.clk(clk),.reset(reset),.clear(clear_int), + fifo_short #(.WIDTH(5+64+WIDTH)) rx_sample_fifo + (.clk(clk),.reset(reset),.clear(clear), .datain({flags,vita_time,sample}), .src_rdy_i(attempt_sample_write), .dst_rdy_o(sample_fifo_in_rdy), .dataout(sample_fifo_o), .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i), @@ -107,7 +109,7 @@ module vita_rx_control wire full = ~sample_fifo_in_rdy; always @(posedge clk) - if(reset | clear_int) + if(reset | clear) begin ibs_state <= IBS_IDLE; lines_left <= 0; @@ -120,12 +122,15 @@ module vita_rx_control else case(ibs_state) IBS_IDLE : - if(~empty_ctrl) + if(not_empty_ctrl) begin lines_left <= numlines_pre; lines_total <= numlines_pre; rcvtime <= rcvtime_pre; - ibs_state <= IBS_WAITING; + if(numlines_pre == 0) + ibs_state <= IBS_ZEROLEN; + else + ibs_state <= IBS_WAITING; send_imm <= send_imm_pre; chain <= chain_pre; reload <= reload_pre; @@ -145,12 +150,12 @@ module vita_rx_control if(lines_left == 1) if(~chain) ibs_state <= IBS_IDLE; - else if(empty_ctrl & reload) + else if(~not_empty_ctrl & reload) begin ibs_state <= IBS_RUNNING; lines_left <= lines_total; end - else if(empty_ctrl) + else if(~not_empty_ctrl) ibs_state <= IBS_BROKENCHAIN; else begin @@ -175,17 +180,20 @@ module vita_rx_control IBS_BROKENCHAIN : if(sample_fifo_in_rdy) ibs_state <= IBS_IDLE; + IBS_ZEROLEN : + if(sample_fifo_in_rdy) + ibs_state <= IBS_IDLE; endcase // case(ibs_state) assign overrun = (ibs_state == IBS_OVERRUN); assign run = (ibs_state == IBS_RUNNING); assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) ) - & ~empty_ctrl; + & not_empty_ctrl; assign debug_rx = { { ibs_state[2:0], command_queue_len }, { 8'd0 }, - { go_now, too_late, run, strobe, read_ctrl, write_ctrl, full_ctrl, empty_ctrl }, + { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl }, { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; endmodule // rx_control diff --git a/fpga/usrp2/vrt/vita_rx_framer.v b/fpga/usrp2/vrt/vita_rx_framer.v index 235817941..bce8fe334 100644 --- a/fpga/usrp2/vrt/vita_rx_framer.v +++ b/fpga/usrp2/vrt/vita_rx_framer.v @@ -11,7 +11,7 @@ module vita_rx_framer output src_rdy_o, // From vita_rx_control - input [4+64+(32*MAXCHAN)-1:0] sample_fifo_i, + input [5+64+(32*MAXCHAN)-1:0] sample_fifo_i, input sample_fifo_src_rdy_i, output sample_fifo_dst_rdy_o, @@ -23,11 +23,11 @@ module vita_rx_framer output [31:0] debug_rx ); - localparam SAMP_WIDTH = 4+64+(32*MAXCHAN); + localparam SAMP_WIDTH = 5+64+(32*MAXCHAN); reg [3:0] sample_phase; wire [3:0] numchan; - wire [3:0] flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-4]; - wire [63:0] vita_time_fifo_o = sample_fifo_i[SAMP_WIDTH-5:SAMP_WIDTH-68]; + wire [4:0] flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-5]; + wire [63:0] vita_time_fifo_o = sample_fifo_i[SAMP_WIDTH-6:SAMP_WIDTH-69]; reg [31:0] data_fifo_o; @@ -55,14 +55,7 @@ module vita_rx_framer reg [3:0] pkt_count; wire [15:0] vita_pkt_len = samples_per_packet + 6; - //wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done}; - - wire clear_reg; - wire clear_int = clear | clear_reg; - - setting_reg #(.my_addr(BASE+3)) sr_clear - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_reg)); + //wire [4:0] flags = {signal_zerolen,signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done}; setting_reg #(.my_addr(BASE+4)) sr_header (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), @@ -76,11 +69,11 @@ module vita_rx_framer (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(vita_trailer),.changed()); - setting_reg #(.my_addr(BASE+7)) sr_samples_per_pkt + setting_reg #(.my_addr(BASE+7),.width(16)) sr_samples_per_pkt (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(samples_per_packet),.changed()); - setting_reg #(.my_addr(BASE+8), .at_reset(1)) sr_numchan + setting_reg #(.my_addr(BASE+8),.width(4), .at_reset(1)) sr_numchan (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(numchan),.changed()); @@ -102,7 +95,7 @@ module vita_rx_framer localparam VITA_ERR_TRAILER = 15; // Extension context packets have no trailer always @(posedge clk) - if(reset | clear_pkt_count) + if(reset | clear | clear_pkt_count) pkt_count <= 0; else if((vita_state == VITA_TRAILER) & pkt_fifo_rdy) pkt_count <= pkt_count + 1; @@ -114,7 +107,8 @@ module vita_rx_framer always @* case(vita_state) // Data packets are IF Data packets with or w/o streamid, no classid, with trailer - VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:20],pkt_count,vita_pkt_len}; + VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:24], + vita_header[23:20],pkt_count[3:0],vita_pkt_len[15:0]}; VITA_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid}; VITA_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]}; VITA_TICS : pkt_fifo_line <= {2'b00,32'd0}; @@ -128,14 +122,14 @@ module vita_rx_framer VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]}; VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0}; VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]}; - VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,28'd0,flags_fifo_o}; + VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,27'd0,flags_fifo_o}; //VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer}; default : pkt_fifo_line <= 34'h0_FFFF_FFFF; endcase // case (vita_state) always @(posedge clk) - if(reset) + if(reset | clear) begin vita_state <= VITA_IDLE; sample_ctr <= 0; @@ -147,7 +141,7 @@ module vita_rx_framer sample_ctr <= 1; sample_phase <= 0; if(sample_fifo_src_rdy_i) - if(|flags_fifo_o[3:1]) + if(|flags_fifo_o[4:1]) vita_state <= VITA_ERR_HEADER; else vita_state <= VITA_HEADER; @@ -192,7 +186,7 @@ module vita_rx_framer req_write_pkt_fifo <= 1; VITA_PAYLOAD : // Write if sample ready and no error flags - req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[3:1]); + req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[4:1]); VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD : req_write_pkt_fifo <= 1; default : @@ -203,7 +197,7 @@ module vita_rx_framer // Short FIFO to buffer between us and the FIFOs outside fifo_short #(.WIDTH(34)) rx_pkt_fifo - (.clk(clk), .reset(reset), .clear(clear_int), + (.clk(clk), .reset(reset), .clear(clear), .datain(pkt_fifo_line), .src_rdy_i(req_write_pkt_fifo), .dst_rdy_o(pkt_fifo_rdy), .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .space(),.occupied(fifo_occupied[4:0]) ); @@ -212,7 +206,7 @@ module vita_rx_framer assign sample_fifo_dst_rdy_o = pkt_fifo_rdy & ( ((vita_state==VITA_PAYLOAD) & (sample_phase == (numchan-4'd1)) & - ~|flags_fifo_o[3:1]) | + ~|flags_fifo_o[4:1]) | (vita_state==VITA_ERR_PAYLOAD)); assign debug_rx = vita_state; diff --git a/fpga/usrp2/vrt/vita_rx_tb.v b/fpga/usrp2/vrt/vita_rx_tb.v index 3e01e2ee2..023934f39 100644 --- a/fpga/usrp2/vrt/vita_rx_tb.v +++ b/fpga/usrp2/vrt/vita_rx_tb.v @@ -37,7 +37,7 @@ module vita_rx_tb; wire sample_dst_rdy, sample_src_rdy; //wire [99:0] sample_data_o; - wire [64+4+(MAXCHAN*32)-1:0] sample_data_o; + wire [64+5+(MAXCHAN*32)-1:0] sample_data_o; vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control (.clk(clk), .reset(reset), .clear(0), @@ -92,58 +92,68 @@ module vita_rx_tb; begin @(negedge reset); @(posedge clk); - write_setting(4,32'hDEADBEEF); // VITA header + write_setting(4,32'h15F00000); // VITA header write_setting(5,32'hF00D1234); // VITA streamid - write_setting(6,32'hF0000000); // VITA trailer + write_setting(6,32'hE0000000); // VITA trailer write_setting(7,8); // Samples per VITA packet - write_setting(8,NUMCHAN); // Samples per VITA packet - queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet - queue_rx_cmd(1,0,16,32'h0,32'h0); // send imm, 2 packets worth - queue_rx_cmd(1,0,7,32'h0,32'h0); // send imm, 1 short packet worth - queue_rx_cmd(1,0,9,32'h0,32'h0); // send imm, just longer than 1 packet + write_setting(8,NUMCHAN); // Vector length + + queue_rx_cmd(1,1,0,10,32'h0,32'h0); // send imm, single packet + #10000; + + queue_rx_cmd(1,0,0,0,32'h0,32'h0); // send imm, single packet + //queue_rx_cmd(1,1,0,0,32'h0,32'h0); // send imm, single packet + + //queue_rx_cmd(1,0,0,0,32'h0,32'h0); // send imm, single packet + + /* + queue_rx_cmd(1,0,0,8,32'h0,32'h0); // send imm, single packet + queue_rx_cmd(1,0,0,16,32'h0,32'h0); // send imm, 2 packets worth + queue_rx_cmd(1,0,0,7,32'h0,32'h0); // send imm, 1 short packet worth + queue_rx_cmd(1,0,0,9,32'h0,32'h0); // send imm, just longer than 1 packet - queue_rx_cmd(1,1,16,32'h0,32'h0); // chained - queue_rx_cmd(0,0,8,32'h0,32'h0); // 2nd in chain + queue_rx_cmd(1,1,0,16,32'h0,32'h0); // chained + queue_rx_cmd(0,0,0,8,32'h0,32'h0); // 2nd in chain - queue_rx_cmd(1,1,17,32'h0,32'h0); // chained, odd length - queue_rx_cmd(0,0,9,32'h0,32'h0); // 2nd in chain, also odd length + queue_rx_cmd(1,1,0,17,32'h0,32'h0); // chained, odd length + queue_rx_cmd(0,0,0,9,32'h0,32'h0); // 2nd in chain, also odd length - queue_rx_cmd(0,0,8,32'h0,32'h340); // send at, on time - queue_rx_cmd(0,0,8,32'h0,32'h100); // send at, but late + queue_rx_cmd(0,0,0,8,32'h0,32'h340); // send at, on time + queue_rx_cmd(0,0,0,8,32'h0,32'h100); // send at, but late #100000; $display("\nChained, break chain\n"); - queue_rx_cmd(1,1,8,32'h0,32'h0); // chained, but break chain + queue_rx_cmd(1,1,0,8,32'h0,32'h0); // chained, but break chain #100000; $display("\nSingle packet\n"); - queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet + queue_rx_cmd(1,0,0,8,32'h0,32'h0); // send imm, single packet #100000; $display("\nEnd chain with zero samples, shouldn't error\n"); - queue_rx_cmd(1,1,8,32'h0,32'h0); // chained - queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error + queue_rx_cmd(1,1,0,8,32'h0,32'h0); // chained + queue_rx_cmd(0,0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error #100000; $display("\nEnd chain with zero samples on odd-length, shouldn't error\n"); - queue_rx_cmd(1,1,14,32'h0,32'h0); // chained - queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error + queue_rx_cmd(1,1,0,14,32'h0,32'h0); // chained + queue_rx_cmd(0,0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error #100000; $display("Should have gotten 14 samples and EOF by now\n"); - queue_rx_cmd(1,1,9,32'h0,32'h0); // chained, but break chain, odd length + queue_rx_cmd(1,1,0,9,32'h0,32'h0); // chained, but break chain, odd length #100000; dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun - queue_rx_cmd(1,0,100,32'h0,32'h0); // long enough to fill the fifos - queue_rx_cmd(1,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent + queue_rx_cmd(1,0,0,100,32'h0,32'h0); // long enough to fill the fifos + queue_rx_cmd(1,0,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent #100000; dst_rdy <= 1; // restart the reads so we can see what we got #100000; dst_rdy <= 0; // stop pulling out of fifo so we can get an overrun - queue_rx_cmd(1,1,100,32'h0,32'h0); // long enough to fill the fifos - //queue_rx_cmd(1,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent + queue_rx_cmd(1,1,0,100,32'h0,32'h0); // long enough to fill the fifos + //queue_rx_cmd(1,0,0,5,32'h0,32'h0); // this command waits until the previous error packet is sent #100000; @(posedge clk); dst_rdy <= 1; - + */ #100000 $finish; end @@ -164,11 +174,12 @@ module vita_rx_tb; task queue_rx_cmd; input send_imm; input chain; - input [29:0] lines; + input reload; + input [28:0] lines; input [31:0] secs; input [31:0] tics; begin - write_setting(0,{send_imm,chain,lines}); + write_setting(0,{send_imm,chain,reload,lines}); write_setting(1,secs); write_setting(2,tics); end diff --git a/fpga/usrp2/vrt/vita_tx.build b/fpga/usrp2/vrt/vita_tx.build index 902929c08..e7106aa10 100755 --- a/fpga/usrp2/vrt/vita_tx.build +++ b/fpga/usrp2/vrt/vita_tx.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v +iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v diff --git a/fpga/usrp2/vrt/vita_tx_chain.v b/fpga/usrp2/vrt/vita_tx_chain.v index 00da4c6e1..2ec78189b 100644 --- a/fpga/usrp2/vrt/vita_tx_chain.v +++ b/fpga/usrp2/vrt/vita_tx_chain.v @@ -31,9 +31,13 @@ module vita_tx_chain wire clear_seqnum; wire [31:0] current_seqnum; - assign underrun = error & ~(error_code == 1); + assign underrun = error; assign message = error_code; - + + setting_reg #(.my_addr(BASE_CTRL+1)) sr + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_vita)); + setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(streamid),.changed(clear_seqnum)); @@ -52,7 +56,7 @@ module vita_tx_chain vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control (.clk(clk), .reset(reset), .clear(clear_vita), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time),.error(error),.error_code(error_code), + .vita_time(vita_time), .error(error), .ack(ack), .error_code(error_code), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), .sample(sample_tx), .run(run), .strobe(strobe_tx), .packet_consumed(packet_consumed), .debug(debug_vtc) ); @@ -71,7 +75,7 @@ module vita_tx_chain (.clk(clk), .reset(reset), .clear(clear_vita), .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(32'd0), - .seqnum0(current_seqnum), .seqnum1(32'd0), + .seqnum(current_seqnum), .data_o(flow_data), .src_rdy_o(flow_src_rdy), .dst_rdy_i(flow_dst_rdy)); trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt (.clk(clk), .reset(reset), .clear(clear_vita), @@ -80,15 +84,15 @@ module vita_tx_chain gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt (.clk(clk), .reset(reset), .clear(clear_vita), - .trigger(error & (REPORT_ERROR==1)), .sent(), + .trigger((error|ack) & (REPORT_ERROR==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(message), - .seqnum0(current_seqnum), .seqnum1(32'd0), + .seqnum(current_seqnum), .data_o(err_data_int), .src_rdy_o(err_src_rdy_int), .dst_rdy_i(err_dst_rdy_int)); assign debug = debug_vtc | debug_vtd; fifo36_mux #(.prio(1)) mux_err_and_flow // Priority to err messages - (.clk(clk), .reset(reset), .clear(clear_vita), + (.clk(clk), .reset(reset), .clear(0), // Don't clear this or it could get clogged .data0_i(err_data_int), .src0_rdy_i(err_src_rdy_int), .dst0_rdy_o(err_dst_rdy_int), .data1_i(flow_data), .src1_rdy_i(flow_src_rdy), .dst1_rdy_o(flow_dst_rdy), .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v index 936762212..20ad6b995 100644 --- a/fpga/usrp2/vrt/vita_tx_control.v +++ b/fpga/usrp2/vrt/vita_tx_control.v @@ -6,7 +6,7 @@ module vita_tx_control input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, - output error, + output error, output ack, output reg [31:0] error_code, output reg packet_consumed, @@ -38,9 +38,8 @@ module vita_tx_control // FIXME ignore too_early for now for timing reasons assign too_early = 0; time_compare - time_compare (.time_now(vita_time), .trigger_time(send_time), .now(now), .early(early), - .late(late), .too_early()); -// .late(late), .too_early(too_early)); + time_compare (.time_now(vita_time), .trigger_time(send_time), + .now(now), .early(early), .late(late), .too_early()); localparam IBS_IDLE = 0; localparam IBS_RUN = 1; // FIXME do we need this? @@ -58,11 +57,6 @@ module vita_tx_control reg [2:0] ibs_state; - wire clear_state; - setting_reg #(.my_addr(BASE+1)) sr - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(clear_state)); - wire [31:0] error_policy; setting_reg #(.my_addr(BASE+3)) sr_error_policy (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), @@ -71,13 +65,15 @@ module vita_tx_control wire policy_wait = error_policy[0]; wire policy_next_packet = error_policy[1]; wire policy_next_burst = error_policy[2]; - reg send_error; + reg send_error, send_ack; always @(posedge clk) - if(reset | clear_state) + if(reset | clear) begin ibs_state <= IBS_IDLE; send_error <= 0; + send_ack <= 0; + error_code <= 0; end else case(ibs_state) @@ -111,7 +107,7 @@ module vita_tx_control begin ibs_state <= IBS_ERROR_DONE; // Not really an error error_code <= CODE_EOB_ACK; - send_error <= 1; + send_ack <= 1; end else ibs_state <= IBS_CONT_BURST; @@ -151,6 +147,7 @@ module vita_tx_control IBS_ERROR_DONE : begin send_error <= 0; + send_ack <= 0; ibs_state <= IBS_IDLE; end @@ -161,14 +158,15 @@ module vita_tx_control assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); assign error = send_error; + assign ack = send_ack; always @(posedge clk) - if(reset) + if(reset | clear) packet_consumed <= 0; else packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o; - assign debug = { { now,early,late,too_early,eop,eob,sob,send_at }, + assign debug = { { now,early,late,ack,eop,eob,sob,send_at }, { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, { 8'b0 }, { 8'b0 } }; diff --git a/fpga/usrp2/vrt/vita_tx_deframer.v b/fpga/usrp2/vrt/vita_tx_deframer.v index 7fb8e3893..eb39feaec 100644 --- a/fpga/usrp2/vrt/vita_tx_deframer.v +++ b/fpga/usrp2/vrt/vita_tx_deframer.v @@ -80,7 +80,7 @@ module vita_tx_deframer wire fifo_space; always @(posedge clk) - if(reset | clear_seqnum) + if(reset | clear | clear_seqnum) begin seqnum_reg <= 32'hFFFF_FFFF; vita_seqnum_reg <= 4'hF; @@ -201,8 +201,6 @@ module vita_tx_deframer send_time[63:32] <= data_i[31:0]; VITA_TICS2 : send_time[31:0] <= data_i[31:0]; - VITA_STORE, VITA_HEADER : - send_time[63:0] <= 64'd0; endcase // case (vita_state) always @(posedge clk) diff --git a/fpga/usrp2/vrt/vita_tx_tb.v b/fpga/usrp2/vrt/vita_tx_tb.v index 0223d6850..a118ffd4e 100644 --- a/fpga/usrp2/vrt/vita_tx_tb.v +++ b/fpga/usrp2/vrt/vita_tx_tb.v @@ -33,7 +33,7 @@ module vita_tx_tb; wire [31:0] set_data_dsp; wire sample_dst_rdy, sample_src_rdy; - wire [64+4+(MAXCHAN*32)-1:0] sample_data_o, sample_data_tx; + wire [5+64+16+(MAXCHAN*32)-1:0] sample_data_o, sample_data_tx; time_64bit #(.TICKS_PER_SEC(100000000), .BASE(0)) time_64bit (.clk(clk), .rst(reset), @@ -49,8 +49,8 @@ module vita_tx_tb; .datain(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), .dataout(data_tx), .src_rdy_o(src_rdy_tx), .dst_rdy_i(dst_rdy_tx)); - vita_tx_deframer #(.BASE(16), .MAXCHAN(MAXCHAN)) vita_tx_deframer - (.clk(clk), .reset(reset), .clear(0), + vita_tx_deframer #(.BASE(16), .MAXCHAN(MAXCHAN), .USE_TRANS_HEADER(0)) vita_tx_deframer + (.clk(clk), .reset(reset), .clear(0), .clear_seqnum(0), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .data_i(data_tx), .dst_rdy_o(dst_rdy_tx), .src_rdy_i(src_rdy_tx), .sample_fifo_o(sample_data_tx), @@ -60,7 +60,7 @@ module vita_tx_tb; vita_tx_control #(.BASE(16), .WIDTH(MAXCHAN*32)) vita_tx_control (.clk(clk), .reset(reset), .clear(0), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .vita_time(vita_time), .underrun(underrun), + .vita_time(vita_time), .error(underrun), .error_code(), .sample_fifo_i(sample_data_tx), .sample_fifo_dst_rdy_o(sample_dst_rdy_tx), .sample_fifo_src_rdy_i(sample_src_rdy_tx), .sample(sample_tx), .run(run_tx), .strobe(strobe_tx)); @@ -92,35 +92,47 @@ module vita_tx_tb; write_setting(7,8); // Samples per VITA packet write_setting(8,NUMCHAN); // Samples per VITA packet #10000; - queue_vita_packets(32'h300, 106, 32'hF00D_1234, 32'h55AA_AA55); - //queue_vita_packets(32'h300, 6, 32'hF00D_1234, 32'h0); - queue_vita_packets(32'h600, 9, 32'h9876_ABCD, 32'h0); - + queue_vita_packets(0, 32'h300, 5, 32'h0000_1000, 32'h0, 4'h0, 1, 0, 1); + queue_vita_packets(0, 32'h0, 5, 32'h0000_2000, 32'h0, 4'h1, 0, 0, 0); + queue_vita_packets(0, 32'h0, 5, 32'h0000_3000, 32'h0, 4'h2, 0, 0, 0); + + queue_vita_packets(0, 32'h400, 3, 32'h0000_4000, 32'h0, 4'h3, 1, 0, 1); + queue_vita_packets(0, 32'h0, 3, 32'h0000_5000, 32'h0, 4'h4, 0, 0, 0); + queue_vita_packets(0, 32'h0, 3, 32'h0000_6000, 32'h0, 4'h5, 0, 1, 0); + #300000 $finish; end task queue_vita_packets; + input [31:0] send_secs; input [31:0] sendtime; input [15:0] samples; input [15:0] word; input [31:0] trailer; + input [3:0] seqnum; + input sob; + input eob; + input sendat; reg [15:0] i; begin + src_rdy <= 0; @(posedge clk); src_rdy <= 1; - data_o <= {4'b0001,4'h1,1'b0,|trailer,2'h3,8'hF0,(16'd5+samples+|trailer)}; // header - @(posedge clk); - data_o <= {4'b0000,32'h0}; // streamid - @(posedge clk); - data_o <= {4'b0000,32'h0}; // SECS - @(posedge clk); - data_o <= {4'b0000,32'h0}; // TICS + data_o <= {4'b0001,4'h0,1'b0,|trailer,sob,eob,{2{sendat}},1'b0,sendat,seqnum,(16'd1+samples+|trailer+sendat+sendat+sendat)}; // header @(posedge clk); - data_o <= {4'b0000,sendtime}; // TICS - @(posedge clk); - + //data_o <= {4'b0000,32'h0}; // streamid + //@(posedge clk); + if(sendat) + begin + data_o <= {4'b0000,send_secs}; // SECS + @(posedge clk); + data_o <= {4'b0000,32'h0}; // TICS + @(posedge clk); + data_o <= {4'b0000,sendtime}; // TICS + @(posedge clk); + end for(i=0;i<samples-1;i=i+1) begin data_o <= {4'b0000,i,word}; // Payload |