From bb0572a960edf54486a4be746c681adaac0fa398 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Tue, 23 Nov 2010 13:36:42 -0800
Subject: fpga: performed a forceful checkout of fpga to overwrite with current
 fpga code

---
 fpga/usrp2/control_lib/Makefile.srcs               |    7 +
 fpga/usrp2/control_lib/atr_controller16.v          |   60 +
 fpga/usrp2/control_lib/bootram.v                   |  250 ++
 fpga/usrp2/control_lib/newfifo/fifo_pacer.v        |   24 +
 fpga/usrp2/control_lib/newfifo/packet32_tb.v       |   27 +
 fpga/usrp2/control_lib/newfifo/packet_generator.v  |   59 +
 .../usrp2/control_lib/newfifo/packet_generator32.v |   21 +
 fpga/usrp2/control_lib/newfifo/packet_tb.v         |   29 +
 fpga/usrp2/control_lib/newfifo/packet_verifier.v   |   61 +
 fpga/usrp2/control_lib/newfifo/packet_verifier32.v |   30 +
 fpga/usrp2/control_lib/nsgpio16LE.v                |  123 +
 fpga/usrp2/control_lib/quad_uart.v                 |   71 +
 fpga/usrp2/control_lib/ram_2port_mixed_width.v     |  120 +
 fpga/usrp2/control_lib/ram_harvard2.v              |   77 +
 fpga/usrp2/control_lib/s3a_icap_wb.v               |   59 +
 fpga/usrp2/control_lib/settings_bus.v              |   17 +-
 fpga/usrp2/control_lib/settings_bus_16LE.v         |   54 +
 fpga/usrp2/control_lib/simple_uart.v               |   13 +-
 fpga/usrp2/control_lib/v5icap_wb.v                 |   54 +
 fpga/usrp2/coregen/Makefile.srcs                   |    4 +
 fpga/usrp2/coregen/coregen.cgp                     |    6 +-
 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise       |   30 +
 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf        |    0
 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc        |    3 +
 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v          | 3839 ++++++++++++++++++++
 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo        |   47 +
 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco        |   84 +
 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise       |   72 +
 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt  |   12 +
 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt |   46 +
 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl   |   68 +
 .../coregen/fifo_xlnx_512x36_2clk_prog_full.gise   |   30 +
 .../coregen/fifo_xlnx_512x36_2clk_prog_full.ngc    |    3 +
 .../coregen/fifo_xlnx_512x36_2clk_prog_full.v      |  173 +
 .../coregen/fifo_xlnx_512x36_2clk_prog_full.veo    |   53 +
 .../coregen/fifo_xlnx_512x36_2clk_prog_full.xco    |   84 +
 .../coregen/fifo_xlnx_512x36_2clk_prog_full.xise   |   72 +
 .../fifo_xlnx_512x36_2clk_prog_full_flist.txt      |   12 +
 .../fifo_xlnx_512x36_2clk_prog_full_readme.txt     |   47 +
 .../fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl       |   68 +
 fpga/usrp2/extramfifo/ext_fifo.v                   |   37 +-
 fpga/usrp2/extramfifo/ext_fifo_tb.sh               |    0
 fpga/usrp2/extramfifo/nobl_fifo.v                  |   41 +-
 fpga/usrp2/extramfifo/nobl_if.v                    |    9 +-
 fpga/usrp2/fifo/.gitignore                         |    2 +
 fpga/usrp2/fifo/fifo19_to_fifo36.v                 |   41 +-
 fpga/usrp2/fifo/fifo36_to_fifo18.v                 |   40 -
 fpga/usrp2/fifo/fifo36_to_fifo19.v                 |   44 +-
 fpga/usrp2/fifo/fifo36_to_ll8.v                    |    1 -
 fpga/usrp2/gpmc/.gitignore                         |    2 +
 fpga/usrp2/gpmc/Makefile.srcs                      |   20 +
 fpga/usrp2/gpmc/burst_data_write.txt               |   16 +
 fpga/usrp2/gpmc/dbsm.v                             |   80 +
 fpga/usrp2/gpmc/edge_sync.v                        |   22 +
 fpga/usrp2/gpmc/fifo_to_gpmc_async.v               |   37 +
 fpga/usrp2/gpmc/fifo_to_gpmc_sync.v                |   26 +
 fpga/usrp2/gpmc/fifo_watcher.v                     |   56 +
 fpga/usrp2/gpmc/gpmc_async.v                       |  130 +
 fpga/usrp2/gpmc/gpmc_sync.v                        |  108 +
 fpga/usrp2/gpmc/gpmc_to_fifo_async.v               |   68 +
 fpga/usrp2/gpmc/gpmc_to_fifo_sync.v                |   57 +
 fpga/usrp2/gpmc/gpmc_wb.v                          |   57 +
 fpga/usrp2/gpmc/make_timing_diag                   |    6 +
 fpga/usrp2/gpmc/ram_to_fifo.v                      |   46 +
 fpga/usrp2/gpmc/single_data_read.txt               |   12 +
 fpga/usrp2/gpmc/single_data_write.txt              |   10 +
 fpga/usrp2/models/gpmc_model_async.v               |  130 +
 fpga/usrp2/models/gpmc_model_sync.v                |   97 +
 fpga/usrp2/opencores/Makefile.srcs                 |    2 +-
 .../opencores/aemb/rtl/verilog/aeMB_core_BE.v      |    4 +-
 fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v   |   27 +-
 fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v |   10 +-
 fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v   |   99 +-
 fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v     |   88 +-
 fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v   |  182 +
 fpga/usrp2/opencores/spi/rtl/verilog/timescale.v   |    2 -
 fpga/usrp2/timing/time_compare.v                   |   26 +-
 fpga/usrp2/top/.gitignore                          |    1 +
 fpga/usrp2/top/Makefile.common                     |    7 +-
 fpga/usrp2/top/python/check_inout.py               |   62 +
 fpga/usrp2/top/safe_u2plus/.gitignore              |    2 +
 fpga/usrp2/top/safe_u2plus/Makefile                |  246 ++
 fpga/usrp2/top/safe_u2plus/safe_u2plus.v           |   23 +
 fpga/usrp2/top/safe_u2plus/u2plus.ucf              |  401 ++
 fpga/usrp2/top/u1e/.gitignore                      |    6 +
 fpga/usrp2/top/u1e/Makefile                        |  101 +
 fpga/usrp2/top/u1e/README                          |    4 +
 fpga/usrp2/top/u1e/cmdfile                         |   20 +
 fpga/usrp2/top/u1e/make.sim                        |    7 +
 fpga/usrp2/top/u1e/tb_u1e.v                        |   41 +
 fpga/usrp2/top/u1e/timing.ucf                      |   13 +
 fpga/usrp2/top/u1e/u1e.ucf                         |  259 ++
 fpga/usrp2/top/u1e/u1e.v                           |  141 +
 fpga/usrp2/top/u1e/u1e_core.v                      |  459 +++
 fpga/usrp2/top/u1e_ethdebug/.gitignore             |    6 +
 fpga/usrp2/top/u1e_ethdebug/Makefile               |   83 +
 fpga/usrp2/top/u1e_ethdebug/u1e.ucf                |   88 +
 fpga/usrp2/top/u1e_ethdebug/u1e.v                  |   28 +
 fpga/usrp2/top/u1e_passthru/.gitignore             |    1 +
 fpga/usrp2/top/u1e_passthru/Makefile               |   99 +
 fpga/usrp2/top/u1e_passthru/passthru.ucf           |    6 +
 fpga/usrp2/top/u1e_passthru/passthru.v             |   18 +
 fpga/usrp2/top/u2_rev3/u2_core.v                   |    0
 fpga/usrp2/top/u2_rev3/u2_core_udp.v               |  248 +-
 fpga/usrp2/top/u2_rev3/u2_rev3.ucf                 |   86 +-
 fpga/usrp2/top/u2plus/.gitignore                   |    1 +
 fpga/usrp2/top/u2plus/Makefile                     |   99 +
 fpga/usrp2/top/u2plus/bootloader.rmi               |  245 ++
 fpga/usrp2/top/u2plus/capture_ddrlvds.v            |   39 +
 fpga/usrp2/top/u2plus/u2plus.ucf                   |  590 +--
 fpga/usrp2/top/u2plus/u2plus.v                     |  391 +-
 fpga/usrp2/top/u2plus/u2plus_core.v                |  696 ++++
 fpga/usrp2/vrt/gen_context_pkt.v                   |   22 +-
 fpga/usrp2/vrt/vita_rx_control.v                   |   62 +-
 fpga/usrp2/vrt/vita_rx_framer.v                    |   38 +-
 fpga/usrp2/vrt/vita_rx_tb.v                        |   67 +-
 fpga/usrp2/vrt/vita_tx.build                       |    2 +-
 fpga/usrp2/vrt/vita_tx_chain.v                     |   18 +-
 fpga/usrp2/vrt/vita_tx_control.v                   |   26 +-
 fpga/usrp2/vrt/vita_tx_deframer.v                  |    4 +-
 fpga/usrp2/vrt/vita_tx_tb.v                        |   48 +-
 121 files changed, 11263 insertions(+), 1085 deletions(-)
 create mode 100644 fpga/usrp2/control_lib/atr_controller16.v
 create mode 100644 fpga/usrp2/control_lib/bootram.v
 create mode 100644 fpga/usrp2/control_lib/newfifo/fifo_pacer.v
 create mode 100644 fpga/usrp2/control_lib/newfifo/packet32_tb.v
 create mode 100644 fpga/usrp2/control_lib/newfifo/packet_generator.v
 create mode 100644 fpga/usrp2/control_lib/newfifo/packet_generator32.v
 create mode 100644 fpga/usrp2/control_lib/newfifo/packet_tb.v
 create mode 100644 fpga/usrp2/control_lib/newfifo/packet_verifier.v
 create mode 100644 fpga/usrp2/control_lib/newfifo/packet_verifier32.v
 create mode 100644 fpga/usrp2/control_lib/nsgpio16LE.v
 create mode 100644 fpga/usrp2/control_lib/quad_uart.v
 create mode 100644 fpga/usrp2/control_lib/ram_2port_mixed_width.v
 create mode 100644 fpga/usrp2/control_lib/ram_harvard2.v
 create mode 100644 fpga/usrp2/control_lib/s3a_icap_wb.v
 create mode 100644 fpga/usrp2/control_lib/settings_bus_16LE.v
 create mode 100644 fpga/usrp2/control_lib/v5icap_wb.v
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt
 create mode 100644 fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl
 mode change 100644 => 100755 fpga/usrp2/extramfifo/ext_fifo_tb.sh
 delete mode 100644 fpga/usrp2/fifo/fifo36_to_fifo18.v
 create mode 100644 fpga/usrp2/gpmc/.gitignore
 create mode 100644 fpga/usrp2/gpmc/Makefile.srcs
 create mode 100644 fpga/usrp2/gpmc/burst_data_write.txt
 create mode 100644 fpga/usrp2/gpmc/dbsm.v
 create mode 100644 fpga/usrp2/gpmc/edge_sync.v
 create mode 100644 fpga/usrp2/gpmc/fifo_to_gpmc_async.v
 create mode 100644 fpga/usrp2/gpmc/fifo_to_gpmc_sync.v
 create mode 100644 fpga/usrp2/gpmc/fifo_watcher.v
 create mode 100644 fpga/usrp2/gpmc/gpmc_async.v
 create mode 100644 fpga/usrp2/gpmc/gpmc_sync.v
 create mode 100644 fpga/usrp2/gpmc/gpmc_to_fifo_async.v
 create mode 100644 fpga/usrp2/gpmc/gpmc_to_fifo_sync.v
 create mode 100644 fpga/usrp2/gpmc/gpmc_wb.v
 create mode 100755 fpga/usrp2/gpmc/make_timing_diag
 create mode 100644 fpga/usrp2/gpmc/ram_to_fifo.v
 create mode 100644 fpga/usrp2/gpmc/single_data_read.txt
 create mode 100644 fpga/usrp2/gpmc/single_data_write.txt
 create mode 100644 fpga/usrp2/models/gpmc_model_async.v
 create mode 100644 fpga/usrp2/models/gpmc_model_sync.v
 create mode 100644 fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v
 delete mode 100644 fpga/usrp2/opencores/spi/rtl/verilog/timescale.v
 create mode 100755 fpga/usrp2/top/python/check_inout.py
 create mode 100644 fpga/usrp2/top/safe_u2plus/.gitignore
 create mode 100644 fpga/usrp2/top/safe_u2plus/Makefile
 create mode 100644 fpga/usrp2/top/safe_u2plus/safe_u2plus.v
 create mode 100755 fpga/usrp2/top/safe_u2plus/u2plus.ucf
 create mode 100644 fpga/usrp2/top/u1e/.gitignore
 create mode 100644 fpga/usrp2/top/u1e/Makefile
 create mode 100644 fpga/usrp2/top/u1e/README
 create mode 100644 fpga/usrp2/top/u1e/cmdfile
 create mode 100644 fpga/usrp2/top/u1e/make.sim
 create mode 100644 fpga/usrp2/top/u1e/tb_u1e.v
 create mode 100644 fpga/usrp2/top/u1e/timing.ucf
 create mode 100644 fpga/usrp2/top/u1e/u1e.ucf
 create mode 100644 fpga/usrp2/top/u1e/u1e.v
 create mode 100644 fpga/usrp2/top/u1e/u1e_core.v
 create mode 100644 fpga/usrp2/top/u1e_ethdebug/.gitignore
 create mode 100644 fpga/usrp2/top/u1e_ethdebug/Makefile
 create mode 100644 fpga/usrp2/top/u1e_ethdebug/u1e.ucf
 create mode 100644 fpga/usrp2/top/u1e_ethdebug/u1e.v
 create mode 100644 fpga/usrp2/top/u1e_passthru/.gitignore
 create mode 100644 fpga/usrp2/top/u1e_passthru/Makefile
 create mode 100644 fpga/usrp2/top/u1e_passthru/passthru.ucf
 create mode 100644 fpga/usrp2/top/u1e_passthru/passthru.v
 mode change 100755 => 100644 fpga/usrp2/top/u2_rev3/u2_core.v
 create mode 100644 fpga/usrp2/top/u2plus/.gitignore
 create mode 100644 fpga/usrp2/top/u2plus/Makefile
 create mode 100644 fpga/usrp2/top/u2plus/bootloader.rmi
 create mode 100644 fpga/usrp2/top/u2plus/capture_ddrlvds.v
 create mode 100644 fpga/usrp2/top/u2plus/u2plus_core.v

(limited to 'fpga/usrp2')

diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs
index bc8e4d5bc..d3bb7e2c8 100644
--- a/fpga/usrp2/control_lib/Makefile.srcs
+++ b/fpga/usrp2/control_lib/Makefile.srcs
@@ -21,6 +21,7 @@ nsgpio.v \
 ram_2port.v \
 ram_harv_cache.v \
 ram_harvard.v \
+ram_harvard2.v \
 ram_loader.v \
 setting_reg.v \
 settings_bus.v \
@@ -29,6 +30,7 @@ srl.v \
 system_control.v \
 wb_1master.v \
 wb_readback_mux.v \
+quad_uart.v \
 simple_uart.v \
 simple_uart_tx.v \
 simple_uart_rx.v \
@@ -42,4 +44,9 @@ pic.v \
 longfifo.v \
 shortfifo.v \
 medfifo.v \
+s3a_icap_wb.v \
+bootram.v \
+nsgpio16LE.v \
+settings_bus_16LE.v \
+atr_controller16.v \
 ))
diff --git a/fpga/usrp2/control_lib/atr_controller16.v b/fpga/usrp2/control_lib/atr_controller16.v
new file mode 100644
index 000000000..3d8b5b1e9
--- /dev/null
+++ b/fpga/usrp2/control_lib/atr_controller16.v
@@ -0,0 +1,60 @@
+
+// Automatic transmit/receive switching of control pins to daughterboards
+// Store everything in registers for now, but could use a RAM for more
+// complex state machines in the future
+
+module atr_controller16
+  (input clk_i, input rst_i,
+   input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o,
+   input we_i, input stb_i, input cyc_i, output reg ack_o,
+   input run_rx, input run_tx, input [31:0] master_time,
+   output [31:0] ctrl_lines);
+   
+   reg [3:0] state;
+   reg [31:0] atr_ram [0:15];  // DP distributed RAM
+
+   wire [3:0] sel_int = { (sel_i[1] & adr_i[1]), (sel_i[0] & adr_i[1]),
+			  (sel_i[1] & ~adr_i[1]), (sel_i[0] & ~adr_i[1]) };
+   
+   // WB Interface
+   always @(posedge clk_i)
+     if(we_i & stb_i & cyc_i)
+       begin
+	  if(sel_int[3])
+	    atr_ram[adr_i[5:2]][31:24] <= dat_i[15:8];
+	  if(sel_int[2])
+	    atr_ram[adr_i[5:2]][23:16] <= dat_i[7:0];
+	  if(sel_int[1])
+	    atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8];
+	  if(sel_int[0])
+	    atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
+       end // if (we_i & stb_i & cyc_i)
+
+   always @(posedge clk_i)
+     dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0];
+   
+   always @(posedge clk_i)
+     ack_o <= stb_i & cyc_i & ~ack_o;
+
+   // Control side of DP RAM
+   assign     ctrl_lines = atr_ram[state];
+
+   // Put a more complex state machine with time delays and multiple states here
+   //  if daughterboard requires more complex sequencing
+   localparam ATR_IDLE = 4'd0;
+   localparam ATR_TX = 4'd1;
+   localparam ATR_RX = 4'd2;
+   localparam ATR_FULL_DUPLEX = 4'd3;
+   
+   always @(posedge clk_i)
+     if(rst_i)
+       state <= ATR_IDLE;
+     else
+       case ({run_rx,run_tx})
+	 2'b00 : state <= ATR_IDLE;
+	 2'b01 : state <= ATR_TX;
+	 2'b10 : state <= ATR_RX;
+	 2'b11 : state <= ATR_FULL_DUPLEX;
+       endcase // case({run_rx,run_tx})
+   
+endmodule // atr_controller16
diff --git a/fpga/usrp2/control_lib/bootram.v b/fpga/usrp2/control_lib/bootram.v
new file mode 100644
index 000000000..668012504
--- /dev/null
+++ b/fpga/usrp2/control_lib/bootram.v
@@ -0,0 +1,250 @@
+
+// Boot RAM for S3A, 8KB, dual port
+
+// RAMB16BWE_S36_S36: 512 x 32 + 4 Parity bits byte-wide write Dual-Port RAM
+//      Spartan-3A Xilinx HDL Libraries Guide, version 10.1.1
+
+module bootram
+  (input clk, input reset,
+   input [12:0] if_adr,
+   output [31:0] if_data,
+
+   input [12:0] dwb_adr_i,
+   input [31:0] dwb_dat_i,
+   output [31:0] dwb_dat_o,
+   input dwb_we_i,
+   output reg dwb_ack_o,
+   input dwb_stb_i,
+   input [3:0] dwb_sel_i);
+
+   wire [31:0] DOA0, DOA1, DOA2, DOA3;
+   wire [31:0] DOB0, DOB1, DOB2, DOB3;
+   wire        ENB0, ENB1, ENB2, ENB3;
+   wire [3:0]  WEB;
+
+   reg [1:0]   delayed_if_bank;
+   always @(posedge clk)
+     delayed_if_bank <= if_adr[12:11];
+   
+   assign if_data = delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA3 : DOA2) : (delayed_if_bank[0] ? DOA1 : DOA0);
+   assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0);
+
+   always @(posedge clk)
+     if(reset)
+       dwb_ack_o <= 0;
+     else
+       dwb_ack_o <= dwb_stb_i & ~dwb_ack_o;
+   
+   assign ENB0 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b00);
+   assign ENB1 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b01);
+   assign ENB2 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b10);
+   assign ENB3 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b11);
+
+   assign WEB = {4{dwb_we_i}} & dwb_sel_i;
+   
+   RAMB16BWE_S36_S36 
+     #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+       .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+       .SRVAL_A(36'h000000000), // Port       A output value upon SSR    assertion
+       .SRVAL_B(36'h000000000), // Port       B output value upon SSR    assertion
+       .WRITE_MODE_A("WRITE_FIRST"), //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+       .WRITE_MODE_B("WRITE_FIRST")) //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+   RAM0
+     (.DOA(DOA0),           // Port A 32-bit Data Output
+      .DOPA(),              // Port A 4-bit Parity Output
+      .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+      .CLKA(clk),           // Port A 1-bit Clock
+      .DIA(32'd0),          // Port A 32-bit Data Input
+      .DIPA(4'd0),          // Port A 4-bit parity Input
+      .ENA(1'b1),           // Port A 1-bit RAM Enable Input
+      .SSRA(1'b0),          // Port A 1-bit Synchronous Set/Reset Input
+      .WEA(1'b0),           // Port A 4-bit Write Enable Input
+
+      .DOB(DOB0),              // Port B 32-bit Data Output
+      .DOPB(),                 // Port B 4-bit Parity Output
+      .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+      .CLKB(clk),              // Port B 1-bit Clock
+      .DIB(dwb_dat_i),         // Port B 32-bit Data Input
+      .DIPB(4'd0),             // Port-B 4-bit parity Input
+      .ENB(ENB0),              // Port B 1-bit RAM Enable Input
+      .SSRB(1'b0),             // Port B 1-bit Synchronous Set/Reset Input
+      .WEB(WEB)                // Port B 4-bit Write Enable Input
+      );   // End of RAMB16BWE_S36_S36_inst instantiation
+
+   RAMB16BWE_S36_S36 
+     #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+       .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+       .SRVAL_A(36'h000000000), // Port       A output value upon SSR    assertion
+       .SRVAL_B(36'h000000000), // Port       B output value upon SSR    assertion
+       .WRITE_MODE_A("WRITE_FIRST"), //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+       .WRITE_MODE_B("WRITE_FIRST")) //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+   RAM1
+     (.DOA(DOA1),           // Port A 32-bit Data Output
+      .DOPA(),              // Port A 4-bit Parity Output
+      .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+      .CLKA(clk),           // Port A 1-bit Clock
+      .DIA(32'd0),          // Port A 32-bit Data Input
+      .DIPA(4'd0),          // Port A 4-bit parity Input
+      .ENA(1'b1),           // Port A 1-bit RAM Enable Input
+      .SSRA(1'b0),          // Port A 1-bit Synchronous Set/Reset Input
+      .WEA(1'b0),           // Port A 4-bit Write Enable Input
+
+      .DOB(DOB1),              // Port B 32-bit Data Output
+      .DOPB(),                 // Port B 4-bit Parity Output
+      .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+      .CLKB(clk),              // Port B 1-bit Clock
+      .DIB(dwb_dat_i),         // Port B 32-bit Data Input
+      .DIPB(4'd0),             // Port-B 4-bit parity Input
+      .ENB(ENB1),              // Port B 1-bit RAM Enable Input
+      .SSRB(1'b0),             // Port B 1-bit Synchronous Set/Reset Input
+      .WEB(WEB)                // Port B 4-bit Write Enable Input
+      );   // End of RAMB16BWE_S36_S36_inst instantiation
+
+   RAMB16BWE_S36_S36 
+     #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+       .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+       .SRVAL_A(36'h000000000), // Port       A output value upon SSR    assertion
+       .SRVAL_B(36'h000000000), // Port       B output value upon SSR    assertion
+       .WRITE_MODE_A("WRITE_FIRST"), //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+       .WRITE_MODE_B("WRITE_FIRST")) //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+   RAM2
+     (.DOA(DOA2),           // Port A 32-bit Data Output
+      .DOPA(),              // Port A 4-bit Parity Output
+      .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+      .CLKA(clk),           // Port A 1-bit Clock
+      .DIA(32'd0),          // Port A 32-bit Data Input
+      .DIPA(4'd0),          // Port A 4-bit parity Input
+      .ENA(1'b1),           // Port A 1-bit RAM Enable Input
+      .SSRA(1'b0),          // Port A 1-bit Synchronous Set/Reset Input
+      .WEA(1'b0),           // Port A 4-bit Write Enable Input
+
+      .DOB(DOB2),              // Port B 32-bit Data Output
+      .DOPB(),                 // Port B 4-bit Parity Output
+      .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+      .CLKB(clk),              // Port B 1-bit Clock
+      .DIB(dwb_dat_i),         // Port B 32-bit Data Input
+      .DIPB(4'd0),             // Port-B 4-bit parity Input
+      .ENB(ENB2),              // Port B 1-bit RAM Enable Input
+      .SSRB(1'b0),             // Port B 1-bit Synchronous Set/Reset Input
+      .WEB(WEB)                // Port B 4-bit Write Enable Input
+      );   // End of RAMB16BWE_S36_S36_inst instantiation
+
+   RAMB16BWE_S36_S36 
+     #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+       .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+       .SRVAL_A(36'h000000000), // Port       A output value upon SSR    assertion
+       .SRVAL_B(36'h000000000), // Port       B output value upon SSR    assertion
+       .WRITE_MODE_A("WRITE_FIRST"), //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+       .WRITE_MODE_B("WRITE_FIRST")) //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+   RAM3
+     (.DOA(DOA3),           // Port A 32-bit Data Output
+      .DOPA(),              // Port A 4-bit Parity Output
+      .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+      .CLKA(clk),           // Port A 1-bit Clock
+      .DIA(32'd0),          // Port A 32-bit Data Input
+      .DIPA(4'd0),          // Port A 4-bit parity Input
+      .ENA(1'b1),           // Port A 1-bit RAM Enable Input
+      .SSRA(1'b0),          // Port A 1-bit Synchronous Set/Reset Input
+      .WEA(1'b0),           // Port A 4-bit Write Enable Input
+
+      .DOB(DOB3),              // Port B 32-bit Data Output
+      .DOPB(),                 // Port B 4-bit Parity Output
+      .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+      .CLKB(clk),              // Port B 1-bit Clock
+      .DIB(dwb_dat_i),         // Port B 32-bit Data Input
+      .DIPB(4'd0),             // Port-B 4-bit parity Input
+      .ENB(ENB3),              // Port B 1-bit RAM Enable Input
+      .SSRB(1'b0),             // Port B 1-bit Synchronous Set/Reset Input
+      .WEB(WEB)                // Port B 4-bit Write Enable Input
+      );   // End of RAMB16BWE_S36_S36_inst instantiation
+
+endmodule // bootram
+
+/*
+       // The following INIT_xx declarations specify the initial contents of the RAM
+       // Address 0 to 127
+       .INIT_00(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_01(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_02(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_03(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_04(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_05(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_06(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_07(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_08(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_09(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_0A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_0B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_0C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_0D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_0E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_0F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       // Address 128 to 255
+       .INIT_10(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_11(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_12(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_13(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_14(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_15(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_16(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_17(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_18(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_19(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_1A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_1B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_1C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_1D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_1E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_1F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       // Address 256 to 383
+       .INIT_20(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_21(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_22(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_23(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_24(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_25(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_26(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_27(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_28(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_29(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_2A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_2B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_2C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_2D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_2E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_2F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       // Address 384 to 511
+       .INIT_30(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_31(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_32(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_33(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_34(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_35(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_36(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_37(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_38(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_39(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_3A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_3B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_3C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_3D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_3E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       .INIT_3F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
+       // The next set of INITP_xx are for the parity bits
+       // Address 0 to 127
+       .INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000),
+       .INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000),
+       // Address 128 to 255
+       .INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000),
+       .INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000),
+       // Address 256 to 383
+       .INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000),
+       .INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000),
+       // Address 384 to 511
+       .INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000),
+       .INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000)
+*/
diff --git a/fpga/usrp2/control_lib/newfifo/fifo_pacer.v b/fpga/usrp2/control_lib/newfifo/fifo_pacer.v
new file mode 100644
index 000000000..1bf03ab6e
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo_pacer.v
@@ -0,0 +1,24 @@
+
+
+module fifo_pacer
+  (input clk,
+   input reset,
+   input [7:0] rate,
+   input enable,
+   input src1_rdy_i, output dst1_rdy_o,
+   output src2_rdy_o, input dst2_rdy_i,
+   output underrun, overrun);
+
+   wire   strobe;
+   
+   cic_strober strober (.clock(clk), .reset(reset), .enable(enable),
+			.rate(rate), .strobe_fast(1), .strobe_slow(strobe));
+
+   wire   all_ready = src1_rdy_i & dst2_rdy_i;
+   assign dst1_rdy_o = all_ready & strobe;
+   assign src2_rdy_o = dst1_rdy_o;
+
+   assign underrun = strobe & ~src1_rdy_i;
+   assign overrun = strobe & ~dst2_rdy_i;
+   
+endmodule // fifo_pacer
diff --git a/fpga/usrp2/control_lib/newfifo/packet32_tb.v b/fpga/usrp2/control_lib/newfifo/packet32_tb.v
new file mode 100644
index 000000000..82bb09c29
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet32_tb.v
@@ -0,0 +1,27 @@
+
+
+module packet32_tb();
+
+   wire [35:0] data;
+   wire       src_rdy, dst_rdy;
+
+   wire       clear = 0;
+   reg 	      clk = 0;
+   reg 	      reset = 1;
+
+   always #10 clk <= ~clk;
+   initial #1000 reset <= 0;
+
+   initial $dumpfile("packet32_tb.vcd");
+   initial $dumpvars(0,packet32_tb);
+
+   wire [31:0] total, crc_err, seq_err, len_err;
+   
+   packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear),
+			       .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+   packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear),
+			      .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+			      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet32_tb
diff --git a/fpga/usrp2/control_lib/newfifo/packet_generator.v b/fpga/usrp2/control_lib/newfifo/packet_generator.v
new file mode 100644
index 000000000..6e8b45ccd
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_generator.v
@@ -0,0 +1,59 @@
+
+
+module packet_generator
+  (input clk, input reset, input clear,
+   output reg [7:0] data_o, output sof_o, output eof_o, 
+   output src_rdy_o, input dst_rdy_i);
+
+   localparam len = 32'd2000;
+
+   reg [31:0] state;
+   reg [31:0] seq;
+   wire [31:0] crc_out;
+   wire        calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF);
+   
+	
+   always @(posedge clk)
+     if(reset | clear)
+       seq <= 0;
+     else
+       if(eof_o & src_rdy_o & dst_rdy_i)
+	 seq <= seq + 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state <= 0;
+     else
+       if(src_rdy_o & dst_rdy_i)
+	 if(state == (len - 1))
+	   state <= 32'hFFFF_FFFC;
+	 else
+	   state <= state + 1;
+
+   always @*
+     case(state)
+       0 :   data_o <= len[7:0];
+       1 :   data_o <= len[15:8];
+       2 :   data_o <= len[23:16];
+       3 :   data_o <= len[31:24];
+       4 :   data_o <= seq[7:0];
+       5 :   data_o <= seq[15:8];
+       6 :   data_o <= seq[23:16];
+       7 :   data_o <= seq[31:24];
+       32'hFFFF_FFFC : data_o <= crc_out[31:24];
+       32'hFFFF_FFFD : data_o <= crc_out[23:16];
+       32'hFFFF_FFFE : data_o <= crc_out[15:8];
+       32'hFFFF_FFFF : data_o <= crc_out[7:0];
+       default : data_o <= state[7:0];
+     endcase // case (state)
+   
+   assign src_rdy_o = 1;
+   assign sof_o = (state == 0);
+   assign eof_o = (state == 32'hFFFF_FFFF);
+
+   wire        clear_crc = eof_o & src_rdy_o & dst_rdy_i;
+   
+   crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), 
+	   .calc(calc_crc), .crc_out(crc_out), .match());
+   
+endmodule // packet_generator
diff --git a/fpga/usrp2/control_lib/newfifo/packet_generator32.v b/fpga/usrp2/control_lib/newfifo/packet_generator32.v
new file mode 100644
index 000000000..6f8004964
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_generator32.v
@@ -0,0 +1,21 @@
+
+
+module packet_generator32
+  (input clk, input reset, input clear,
+   output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+   wire [7:0] 	     ll_data;
+   wire 	     ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy_n;
+   
+   packet_generator pkt_gen
+     (.clk(clk), .reset(reset), .clear(clear),
+      .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
+      .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n));
+
+   ll8_to_fifo36 ll8_to_f36
+     (.clk(clk), .reset(reset), .clear(clear),
+      .ll_data(ll_data), .ll_sof_n(~ll_sof), .ll_eof_n(~ll_eof),
+      .ll_src_rdy_n(~ll_src_rdy), .ll_dst_rdy_n(ll_dst_rdy_n),
+      .f36_data(data_o), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i));
+   
+endmodule // packet_generator32
diff --git a/fpga/usrp2/control_lib/newfifo/packet_tb.v b/fpga/usrp2/control_lib/newfifo/packet_tb.v
new file mode 100644
index 000000000..3c423d2ba
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_tb.v
@@ -0,0 +1,29 @@
+
+
+module packet_tb();
+
+   wire [7:0] data;
+   wire       sof, eof, src_rdy, dst_rdy;
+
+   wire       clear = 0;
+   reg 	      clk = 0;
+   reg 	      reset = 1;
+
+   always #10 clk <= ~clk;
+   initial #1000 reset <= 0;
+
+   initial $dumpfile("packet_tb.vcd");
+   initial $dumpvars(0,packet_tb);
+
+   wire [31:0] total, crc_err, seq_err, len_err;
+   
+   packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear),
+			     .data_o(data), .sof_o(sof), .eof_o(eof),
+			     .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+   packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear),
+			    .data_i(data), .sof_i(sof), .eof_i(eof),
+			    .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+			    .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet_tb
diff --git a/fpga/usrp2/control_lib/newfifo/packet_verifier.v b/fpga/usrp2/control_lib/newfifo/packet_verifier.v
new file mode 100644
index 000000000..b49ad1bbb
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_verifier.v
@@ -0,0 +1,61 @@
+
+
+// Packet format --
+//    Line 1 -- Length, 32 bits
+//    Line 2 -- Sequence number, 32 bits
+//    Last line -- CRC, 32 bits
+
+module packet_verifier
+  (input clk, input reset, input clear,
+   input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o,
+
+   output reg [31:0] total, 
+   output reg [31:0] crc_err, 
+   output reg [31:0] seq_err, 
+   output reg [31:0] len_err);
+
+   reg [31:0] 	     seq_num;
+   reg [31:0] 	     length;
+   wire 	     first_byte, last_byte;
+   reg 		     second_byte, last_byte_d1;
+
+   wire 	     calc_crc = src_rdy_i & dst_rdy_o;
+   
+   crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), 
+	   .calc(calc_crc), .crc_out(), .match(match_crc));
+
+   assign first_byte = src_rdy_i & dst_rdy_o & sof_i;
+   assign last_byte = src_rdy_i & dst_rdy_o & eof_i;
+   assign dst_rdy_o = ~last_byte_d1;
+
+   // stubs for now
+   wire 	     match_seq = 1;
+   wire 	     match_len = 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       last_byte_d1 <= 0;
+     else 
+       last_byte_d1 <= last_byte;
+
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  total <= 0;
+	  crc_err <= 0;
+	  seq_err <= 0;
+	  len_err <= 0;
+       end
+     else
+       if(last_byte_d1)
+	 begin
+	    total <= total + 1;
+	    if(~match_crc)
+	      crc_err <= crc_err + 1;
+	    else if(~match_seq)
+	      seq_err <= seq_err + 1;
+	    else if(~match_len)
+	      seq_err <= len_err + 1;
+	 end
+   
+endmodule // packet_verifier
diff --git a/fpga/usrp2/control_lib/newfifo/packet_verifier32.v b/fpga/usrp2/control_lib/newfifo/packet_verifier32.v
new file mode 100644
index 000000000..06a13d242
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_verifier32.v
@@ -0,0 +1,30 @@
+
+
+module packet_verifier32
+  (input clk, input reset, input clear,
+   input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
+   output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err);
+
+   wire [7:0] 	     ll_data;
+   wire 	     ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy;
+   wire [35:0] 	     data_int;
+   wire 	     src_rdy_int, dst_rdy_int;
+   
+   fifo_short #(.WIDTH(36)) fifo_short
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int));
+   
+   fifo36_to_ll8 f36_to_ll8
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f36_data(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int),
+      .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n),
+      .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy));
+   
+   packet_verifier pkt_ver
+     (.clk(clk), .reset(reset), .clear(clear),
+      .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n),
+      .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy),
+      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet_verifier32
diff --git a/fpga/usrp2/control_lib/nsgpio16LE.v b/fpga/usrp2/control_lib/nsgpio16LE.v
new file mode 100644
index 000000000..8aef0c7ae
--- /dev/null
+++ b/fpga/usrp2/control_lib/nsgpio16LE.v
@@ -0,0 +1,123 @@
+// Modified from code originally by Richard Herveille, his copyright is below
+
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  OpenCores Simple General Purpose IO core                   ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+
+module nsgpio16LE
+  (input clk_i, input rst_i, 
+   input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [15:0] dat_i, 
+   output reg [15:0] dat_o, output reg ack_o,
+   input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, 
+   inout [31:0] gpio
+   );
+
+   reg [31:0] 	ctrl, line, ddr, dbg, lgpio;
+   
+   wire 	wb_acc = cyc_i & stb_i;            // WISHBONE access
+   wire 	wb_wr  = wb_acc & we_i;            // WISHBONE write access
+
+   always @(posedge clk_i or posedge rst_i)
+     if (rst_i)
+       begin
+          ctrl <= 32'h0;
+          line <= 32'h0;
+	  ddr <= 32'h0;
+	  dbg <= 32'h0;
+       end
+     else if (wb_wr)
+       case( adr_i[3:1] )
+	 3'b000 : 
+           line[15:0] <= dat_i;
+	 3'b001 : 
+           line[31:16] <= dat_i;
+	 3'b010 :
+	   ddr[15:0] <= dat_i;
+	 3'b011 :
+	   ddr[31:16] <= dat_i;
+	 3'b100 :
+	   ctrl[15:0] <= dat_i;
+	 3'b101 :
+	   ctrl[31:16] <= dat_i;
+	 3'b110 :
+	   dbg[15:0] <= dat_i;
+	 3'b111 :
+	   dbg[31:16] <= dat_i;
+       endcase // case ( adr_i[3:1] )
+   
+   always @(posedge clk_i)
+     case (adr_i[3:1])
+       3'b000 :
+	 dat_o <= lgpio[15:0];
+       3'b001 :
+	 dat_o <= lgpio[31:16];
+       3'b010 :
+	 dat_o <= ddr[15:0];
+       3'b011 :
+	 dat_o <= ddr[31:16];
+       3'b100 :
+	 dat_o <= ctrl[15:0];
+       3'b101 :
+	 dat_o <= ctrl[31:16];
+       3'b110 :
+	 dat_o <= dbg[15:0];
+       3'b111 :
+	 dat_o <= dbg[31:16];
+     endcase // case (adr_i[3:1])
+   
+   
+   always @(posedge clk_i or posedge rst_i)
+     if (rst_i)
+       ack_o <= 1'b0;
+     else
+       ack_o <= wb_acc & !ack_o;
+   
+   // latch GPIO input pins
+   always @(posedge clk_i)
+     lgpio <= gpio;
+   
+   // assign GPIO outputs
+   integer   n;
+   reg [31:0] igpio; // temporary internal signal
+   
+   always @(ctrl or line or debug_1 or debug_0 or atr or ddr or dbg)
+     for(n=0;n<32;n=n+1)
+       igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : 
+			     (ctrl[n] ?  atr[n] : line[n]) )
+	 : 1'bz;
+   
+   assign     gpio = igpio;
+   
+endmodule
+
diff --git a/fpga/usrp2/control_lib/quad_uart.v b/fpga/usrp2/control_lib/quad_uart.v
new file mode 100644
index 000000000..afa6fae1d
--- /dev/null
+++ b/fpga/usrp2/control_lib/quad_uart.v
@@ -0,0 +1,71 @@
+
+module quad_uart
+  #(parameter TXDEPTH = 1,
+    parameter RXDEPTH = 1)
+    (input clk_i, input rst_i,
+     input we_i, input stb_i, input cyc_i, output reg ack_o,
+     input [4:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+     output [3:0] rx_int_o, output [3:0] tx_int_o, 
+     output [3:0] tx_o, input [3:0] rx_i, output [3:0] baud_o
+     );
+   
+   // Register Map
+   localparam SUART_CLKDIV = 0;
+   localparam SUART_TXLEVEL = 1;
+   localparam SUART_RXLEVEL = 2;
+   localparam SUART_TXCHAR = 3;
+   localparam SUART_RXCHAR = 4;
+   
+   wire       wb_acc = cyc_i & stb_i;            // WISHBONE access
+   wire       wb_wr  = wb_acc & we_i;            // WISHBONE write access
+   
+   reg [15:0] clkdiv[0:3];
+   wire [7:0] rx_char[0:3];
+   wire  [3:0] tx_fifo_full, rx_fifo_empty;   
+   wire [7:0] tx_fifo_level[0:3], rx_fifo_level[0:3];
+
+   always @(posedge clk_i)
+     if (rst_i)
+       ack_o 			    <= 1'b0;
+     else
+       ack_o 			    <= wb_acc & ~ack_o;
+
+   integer    i;
+   always @(posedge clk_i)
+     if (rst_i)
+       for(i=0;i<4;i=i+1)
+	 clkdiv[i] <= 0;
+     else if (wb_wr)
+       case(adr_i[2:0])
+	 SUART_CLKDIV : clkdiv[adr_i[4:3]] <= dat_i[15:0];
+       endcase // case(adr_i)
+   
+   always @(posedge clk_i)
+     case (adr_i[2:0])
+       SUART_TXLEVEL : dat_o <= tx_fifo_level[adr_i[4:3]];
+       SUART_RXLEVEL : dat_o <= rx_fifo_level[adr_i[4:3]];
+       SUART_RXCHAR : dat_o <= rx_char[adr_i[4:3]];
+     endcase // case(adr_i)
+
+   genvar     j;
+   generate
+      for(j=0;j<4;j=j+1)
+	begin : gen_uarts
+	   simple_uart_tx #(.DEPTH(TXDEPTH)) simple_uart_tx
+	    (.clk(clk_i),.rst(rst_i),
+	     .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i[2:0] == SUART_TXCHAR) && (adr_i[4:3]==j)),
+	     .fifo_level(tx_fifo_level[j]),.fifo_full(tx_fifo_full[j]),
+	     .clkdiv(clkdiv[j]),.baudclk(baud_o[j]),.tx(tx_o[j]));
+	   
+	   simple_uart_rx #(.DEPTH(RXDEPTH)) simple_uart_rx
+	     (.clk(clk_i),.rst(rst_i),
+	      .fifo_out(rx_char[j]),.fifo_read(ack_o && ~wb_wr && (adr_i[2:0] == SUART_RXCHAR) && (adr_i[4:3]==j)),
+	      .fifo_level(rx_fifo_level[j]),.fifo_empty(rx_fifo_empty[j]),
+	      .clkdiv(clkdiv[j]),.rx(rx_i[j]));
+	end // block: gen_uarts
+   endgenerate
+   
+   assign     tx_int_o 	= ~tx_fifo_full;  // Interrupt for those that have space
+   assign     rx_int_o 	= ~rx_fifo_empty; // Interrupt for those that have data
+   
+endmodule // quad_uart
diff --git a/fpga/usrp2/control_lib/ram_2port_mixed_width.v b/fpga/usrp2/control_lib/ram_2port_mixed_width.v
new file mode 100644
index 000000000..fae7d8de3
--- /dev/null
+++ b/fpga/usrp2/control_lib/ram_2port_mixed_width.v
@@ -0,0 +1,120 @@
+
+module ram_2port_mixed_width
+  (input clk16,
+   input en16,
+   input we16,
+   input [10:0] addr16,
+   input [15:0] di16,
+   output [15:0] do16,
+   input clk32,
+   input en32,
+   input we32,
+   input [9:0] addr32,
+   input [31:0] di32,
+   output [31:0] do32);
+
+   wire 	 en32a = en32 & ~addr32[9];
+   wire 	 en32b = en32 & addr32[9];
+   wire 	 en16a = en16 & ~addr16[10];
+   wire 	 en16b = en16 & addr16[10];
+
+   wire [31:0] 	 do32a, do32b;
+   wire [15:0] 	 do16a, do16b;
+   
+   assign do32 = addr32[9] ? do32b : do32a;
+   assign do16 = addr16[10] ? do16b : do16a;
+   
+   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
+		       .INIT_B(18'h00000),
+		       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+		       .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+		       .SRVAL_B(18'h00000),      // Port B output value upon SSR assertion
+		       .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       ) 
+   RAMB16BWE_S36_S18_0 (.DOA(do32a),       // Port A 32-bit Data Output
+			.DOB(do16a),       // Port B 16-bit Data Output
+			.DOPA(),     // Port A 4-bit Parity Output
+			.DOPB(),     // Port B 2-bit Parity Output
+			.ADDRA(addr32[8:0]),   // Port A 9-bit Address Input
+			.ADDRB(addr16[9:0]),   // Port B 10-bit Address Input
+			.CLKA(clk32),     // Port A 1-bit Clock
+			.CLKB(clk16),     // Port B 1-bit Clock
+			.DIA(di32),       // Port A 32-bit Data Input
+			.DIB(di16),       // Port B 16-bit Data Input
+			.DIPA(0),     // Port A 4-bit parity Input
+			.DIPB(0),     // Port-B 2-bit parity Input
+			.ENA(en32a),       // Port A 1-bit RAM Enable Input
+			.ENB(en16a),       // Port B 1-bit RAM Enable Input
+			.SSRA(0),     // Port A 1-bit Synchronous Set/Reset Input
+			.SSRB(0),     // Port B 1-bit Synchronous Set/Reset Input
+			.WEA({4{we32}}),       // Port A 4-bit Write Enable Input
+			.WEB({2{we16}})        // Port B 2-bit Write Enable Input
+			);
+
+   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
+		       .INIT_B(18'h00000),
+		       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+		       .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+		       .SRVAL_B(18'h00000),      // Port B output value upon SSR assertion
+		       .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       ) 
+   RAMB16BWE_S36_S18_1 (.DOA(do32b),       // Port A 32-bit Data Output
+			.DOB(do16b),       // Port B 16-bit Data Output
+			.DOPA(),     // Port A 4-bit Parity Output
+			.DOPB(),     // Port B 2-bit Parity Output
+			.ADDRA(addr32[8:0]),   // Port A 9-bit Address Input
+			.ADDRB(addr16[9:0]),   // Port B 10-bit Address Input
+			.CLKA(clk32),     // Port A 1-bit Clock
+			.CLKB(clk16),     // Port B 1-bit Clock
+			.DIA(di32),       // Port A 32-bit Data Input
+			.DIB(di16),       // Port B 16-bit Data Input
+			.DIPA(0),     // Port A 4-bit parity Input
+			.DIPB(0),     // Port-B 2-bit parity Input
+			.ENA(en32b),       // Port A 1-bit RAM Enable Input
+			.ENB(en16b),       // Port B 1-bit RAM Enable Input
+			.SSRA(0),     // Port A 1-bit Synchronous Set/Reset Input
+			.SSRB(0),     // Port B 1-bit Synchronous Set/Reset Input
+			.WEA({4{we32}}),       // Port A 4-bit Write Enable Input
+			.WEB({2{we16}})        // Port B 2-bit Write Enable Input
+			);
+
+endmodule // ram_2port_mixed_width
+
+
+
+   
+// ISE 10.1.03 chokes on the following
+   
+/*
+   
+   reg [31:0] 	       ram [(1<<AWIDTH)-1:0];
+   integer 	       i;
+   initial
+     for(i=0;i<512;i=i+1)
+       ram[i] <= 32'b0;
+   
+   always @(posedge clk16)
+     if (en16)
+       begin
+          if (we16)
+            if(addr16[0])
+	      ram[addr16[10:1]][15:0] <= di16;
+	    else
+	      ram[addr16[10:1]][31:16] <= di16;
+	  do16 <= addr16[0] ? ram[addr16[10:1]][15:0] : ram[addr16[10:1]][31:16];
+       end
+
+   always @(posedge clk32)
+     if (en32)
+       begin
+          if (we32)
+            ram[addr32] <= di32;
+          do32 <= ram[addr32];
+       end
+
+endmodule // ram_2port_mixed_width
+
+ 
+ */
diff --git a/fpga/usrp2/control_lib/ram_harvard2.v b/fpga/usrp2/control_lib/ram_harvard2.v
new file mode 100644
index 000000000..67777af2a
--- /dev/null
+++ b/fpga/usrp2/control_lib/ram_harvard2.v
@@ -0,0 +1,77 @@
+
+
+// Dual ported, Harvard architecture
+
+module ram_harvard2
+  #(parameter AWIDTH=15,
+    parameter RAM_SIZE=32768)
+   (input wb_clk_i, 
+    input wb_rst_i,
+    // Instruction fetch port.
+    input [AWIDTH-1:0] if_adr,
+    output reg [31:0] if_data,
+    // Data access port.
+    input [AWIDTH-1:0] dwb_adr_i,
+    input [31:0] dwb_dat_i, 
+    output reg [31:0] dwb_dat_o,
+    input dwb_we_i,
+    output dwb_ack_o,
+    input dwb_stb_i,
+    input [3:0] dwb_sel_i);
+   
+   reg 	  ack_d1;
+   reg 	  stb_d1;
+   
+   assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1));
+
+   always @(posedge wb_clk_i) 
+     if(wb_rst_i)
+       ack_d1 <= 1'b0;
+     else 
+       ack_d1 <= dwb_ack_o;
+
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       stb_d1 <= 0;
+     else
+       stb_d1 <= dwb_stb_i;
+
+   reg [7:0] ram0 [0:(RAM_SIZE/4)-1];
+   reg [7:0] ram1 [0:(RAM_SIZE/4)-1];
+   reg [7:0] ram2 [0:(RAM_SIZE/4)-1];
+   reg [7:0] ram3 [0:(RAM_SIZE/4)-1];
+   
+   // Port 1, Read only
+   always @(posedge wb_clk_i)
+     if_data[31:24] <= ram3[if_adr[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     if_data[23:16] <= ram2[if_adr[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     if_data[15:8] <= ram1[if_adr[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     if_data[7:0] <= ram0[if_adr[AWIDTH-1:2]];
+
+   // Port 2, R/W
+   always @(posedge wb_clk_i)
+     if(dwb_stb_i) dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     if(dwb_stb_i) dwb_dat_o[23:16] <= ram2[dwb_adr_i[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     if(dwb_stb_i) dwb_dat_o[15:8] <= ram1[dwb_adr_i[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     if(dwb_stb_i) dwb_dat_o[7:0] <= ram0[dwb_adr_i[AWIDTH-1:2]];
+   
+   always @(posedge wb_clk_i)
+     if(dwb_we_i & dwb_stb_i & dwb_sel_i[3])
+       ram3[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[31:24];
+   always @(posedge wb_clk_i)
+     if(dwb_we_i & dwb_stb_i & dwb_sel_i[2])
+       ram2[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[23:16];
+   always @(posedge wb_clk_i)
+     if(dwb_we_i & dwb_stb_i & dwb_sel_i[1])
+       ram1[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[15:8];
+   always @(posedge wb_clk_i)
+     if(dwb_we_i & dwb_stb_i & dwb_sel_i[0])
+       ram0[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[7:0];
+   
+endmodule // ram_harvard
diff --git a/fpga/usrp2/control_lib/s3a_icap_wb.v b/fpga/usrp2/control_lib/s3a_icap_wb.v
new file mode 100644
index 000000000..83d9f775e
--- /dev/null
+++ b/fpga/usrp2/control_lib/s3a_icap_wb.v
@@ -0,0 +1,59 @@
+
+
+module s3a_icap_wb
+  (input clk, input reset,
+   input cyc_i, input stb_i, input we_i, output ack_o,
+   input [31:0] dat_i, output [31:0] dat_o);//, output [31:0] debug_out);
+
+   assign dat_o[31:8] = 24'd0;
+   
+   wire 	BUSY, CE, WRITE, ICAPCLK;
+   
+   //changed this to gray-ish code to prevent glitching
+   reg [2:0] 	icap_state;
+   localparam ICAP_IDLE  = 0;
+   localparam ICAP_WR0 	 = 1;
+   localparam ICAP_WR1 	 = 5;
+   localparam ICAP_RD0 	 = 2;
+   localparam ICAP_RD1 	 = 3;
+
+   always @(posedge clk)
+     if(reset)
+       icap_state 	<= ICAP_IDLE;
+     else
+       case(icap_state)
+	 ICAP_IDLE :
+	   begin
+	      if(stb_i & cyc_i)
+		if(we_i)
+		  icap_state <= ICAP_WR0;
+		else
+		  icap_state <= ICAP_RD0;
+	   end
+	 ICAP_WR0 :
+	   icap_state <= ICAP_WR1;
+	 ICAP_WR1 :
+	   icap_state <= ICAP_IDLE;
+	 ICAP_RD0 :
+	   icap_state <= ICAP_RD1;
+	 ICAP_RD1 :
+	   icap_state <= ICAP_IDLE;
+       endcase // case (icap_state)
+
+   assign WRITE 	 = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1);
+   assign CE 		 = (icap_state == ICAP_WR0) | (icap_state == ICAP_RD0);
+   assign ICAPCLK        = CE & (~clk);
+
+   assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1);
+   //assign debug_out = {17'd0, BUSY, dat_i[7:0], ~CE, ICAPCLK, ~WRITE, icap_state};
+   
+   ICAP_SPARTAN3A ICAP_SPARTAN3A_inst 
+     (.BUSY(BUSY),          // Busy output
+      .O(dat_o[7:0]),            // 32-bit data output
+      .CE(~CE),              // Clock enable input
+      .CLK(ICAPCLK),            // Clock input
+      .I(dat_i[7:0]),            // 32-bit data input
+      .WRITE(~WRITE)         // Write input
+      );
+
+endmodule // s3a_icap_wb
diff --git a/fpga/usrp2/control_lib/settings_bus.v b/fpga/usrp2/control_lib/settings_bus.v
index fc960e456..aec179516 100644
--- a/fpga/usrp2/control_lib/settings_bus.v
+++ b/fpga/usrp2/control_lib/settings_bus.v
@@ -10,7 +10,7 @@ module settings_bus
      input wb_stb_i,
      input wb_we_i,
      output reg wb_ack_o,
-     output strobe,
+     output reg strobe,
      output reg [7:0] addr,
      output reg [31:0] data);
 
@@ -19,18 +19,18 @@ module settings_bus
    always @(posedge wb_clk)
      if(wb_rst)
        begin
-	  stb_int <= 1'b0;
+	  strobe <= 1'b0;
 	  addr <= 8'd0;
 	  data <= 32'd0;
        end
-     else if(wb_we_i & wb_stb_i)
+     else if(wb_we_i & wb_stb_i & ~wb_ack_o)
        begin
-	  stb_int <= 1'b1;
+	  strobe <= 1'b1;
 	  addr <= wb_adr_i[9:2];
 	  data <= wb_dat_i;
        end
      else
-       stb_int <= 1'b0;
+       strobe <= 1'b0;
 
    always @(posedge wb_clk)
      if(wb_rst)
@@ -38,11 +38,4 @@ module settings_bus
      else
        wb_ack_o <= wb_stb_i & ~wb_ack_o;
 
-   always @(posedge wb_clk)
-     stb_int_d1 <= stb_int;
-
-   //assign strobe = stb_int & ~stb_int_d1;
-   assign strobe = stb_int & wb_ack_o;
-          
 endmodule // settings_bus
-
diff --git a/fpga/usrp2/control_lib/settings_bus_16LE.v b/fpga/usrp2/control_lib/settings_bus_16LE.v
new file mode 100644
index 000000000..76061e9e0
--- /dev/null
+++ b/fpga/usrp2/control_lib/settings_bus_16LE.v
@@ -0,0 +1,54 @@
+
+// Grab settings off the wishbone bus, send them out to settings bus
+// 16 bits little endian, but all registers need to be written 32 bits at a time.
+// This means that you write the low 16 bits first and then the high 16 bits.
+// The setting regs are strobed when the high 16 bits are written
+
+module settings_bus_16LE
+  #(parameter AWIDTH=16, RWIDTH=8)
+    (input wb_clk, 
+     input wb_rst, 
+     input [AWIDTH-1:0] wb_adr_i,
+     input [15:0] wb_dat_i,
+     input wb_stb_i,
+     input wb_we_i,
+     output reg wb_ack_o,
+     output strobe,
+     output reg [7:0] addr,
+     output reg [31:0] data);
+
+   reg 		       stb_int;
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       begin
+	  stb_int <= 1'b0;
+	  addr <= 8'd0;
+	  data <= 32'd0;
+       end
+     else if(wb_we_i & wb_stb_i)
+       begin
+	  addr <= wb_adr_i[RWIDTH+1:2];  // Zero pad high bits
+	  if(wb_adr_i[1])
+	    begin
+	       stb_int <= 1'b1;     // We now have both halves
+	       data[31:16] <= wb_dat_i;
+	    end
+	  else
+	    begin
+	       stb_int <= 1'b0;     // Don't strobe, we need other half
+	       data[15:0] <= wb_dat_i;
+	    end
+       end
+     else
+       stb_int <= 1'b0;
+
+   always @(posedge wb_clk)
+     if(wb_rst)
+       wb_ack_o <= 0;
+     else
+       wb_ack_o <= wb_stb_i & ~wb_ack_o;
+
+   assign strobe = stb_int & wb_ack_o;
+          
+endmodule // settings_bus_16LE
diff --git a/fpga/usrp2/control_lib/simple_uart.v b/fpga/usrp2/control_lib/simple_uart.v
index 22f0e70a2..0dd58b5f5 100644
--- a/fpga/usrp2/control_lib/simple_uart.v
+++ b/fpga/usrp2/control_lib/simple_uart.v
@@ -1,11 +1,12 @@
 
 module simple_uart
   #(parameter TXDEPTH = 1,
-    parameter RXDEPTH = 1)
-    (input clk_i, input rst_i,
-     input we_i, input stb_i, input cyc_i, output reg ack_o,
-     input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
-     output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
+    parameter RXDEPTH = 1,
+    parameter CLKDIV_DEFAULT = 16'd0)
+   (input clk_i, input rst_i,
+    input we_i, input stb_i, input cyc_i, output reg ack_o,
+    input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+    output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
    
    // Register Map
    localparam SUART_CLKDIV = 0;
@@ -30,7 +31,7 @@ module simple_uart
    
    always @(posedge clk_i)
      if (rst_i)
-       clkdiv <= 0;
+       clkdiv <= CLKDIV_DEFAULT;
      else if (wb_wr)
        case(adr_i)
 	 SUART_CLKDIV : clkdiv <= dat_i[15:0];
diff --git a/fpga/usrp2/control_lib/v5icap_wb.v b/fpga/usrp2/control_lib/v5icap_wb.v
new file mode 100644
index 000000000..c8800285a
--- /dev/null
+++ b/fpga/usrp2/control_lib/v5icap_wb.v
@@ -0,0 +1,54 @@
+
+
+module v5icap_wb
+  (input clk, input reset,
+   input cyc_i, input stb_i, input we_i, output ack_o,
+   input [31:0] dat_i, output [31:0] dat_o);
+
+   wire 	BUSY, CE, WRITE;
+   
+   reg [2:0] 	icap_state;
+   localparam ICAP_IDLE  = 0;
+   localparam ICAP_WR0 	 = 1;
+   localparam ICAP_WR1 	 = 2;
+   localparam ICAP_RD0 	 = 3;
+   localparam ICAP_RD1 	 = 4;
+
+   always @(posedge clk)
+     if(reset)
+       icap_state 	<= ICAP_IDLE;
+     else
+       case(icap_state)
+	 ICAP_IDLE :
+	   begin
+	      if(stb_i & cyc_i)
+		if(we_i)
+		  icap_state <= ICAP_WR0;
+		else
+		  icap_state <= ICAP_RD0;
+	   end
+	 ICAP_WR0 :
+	   icap_state <= ICAP_WR1;
+	 ICAP_WR1 :
+	   icap_state <= ICAP_IDLE;
+	 ICAP_RD0 :
+	   icap_state <= ICAP_RD1;
+	 ICAP_RD1 :
+	   icap_state <= ICAP_IDLE;
+       endcase // case (icap_state)
+
+   assign WRITE 	 = (icap_state == ICAP_WR0) | (icap_state == ICAP_WR1);
+   assign CE 		 = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD0);
+
+   assign ack_o = (icap_state == ICAP_WR1) | (icap_state == ICAP_RD1);
+   
+   ICAP_VIRTEX5 #(.ICAP_WIDTH("X32")) ICAP_VIRTEX5_inst 
+     (.BUSY(BUSY),          // Busy output
+      .O(dat_o),            // 32-bit data output
+      .CE(~CE),              // Clock enable input
+      .CLK(clk),            // Clock input
+      .I(dat_i),            // 32-bit data input
+      .WRITE(~WRITE)         // Write input
+      );
+
+endmodule // v5icap_wb
diff --git a/fpga/usrp2/coregen/Makefile.srcs b/fpga/usrp2/coregen/Makefile.srcs
index a59696d15..a3a5d826d 100644
--- a/fpga/usrp2/coregen/Makefile.srcs
+++ b/fpga/usrp2/coregen/Makefile.srcs
@@ -16,8 +16,12 @@ fifo_xlnx_16x19_2clk.v \
 fifo_xlnx_16x19_2clk.xco \
 fifo_xlnx_16x40_2clk.v \
 fifo_xlnx_16x40_2clk.xco \
+fifo_xlnx_32x36_2clk.v \
+fifo_xlnx_32x36_2clk.xco \
 fifo_xlnx_512x36_2clk_36to18.v \
 fifo_xlnx_512x36_2clk_36to18.xco \
 fifo_xlnx_512x36_2clk_18to36.v \
 fifo_xlnx_512x36_2clk_18to36.xco \
+fifo_xlnx_512x36_2clk_prog_full.v \
+fifo_xlnx_512x36_2clk_prog_full.xco \
 ))
diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp
index 4c9201aff..dd85a7f50 100644
--- a/fpga/usrp2/coregen/coregen.cgp
+++ b/fpga/usrp2/coregen/coregen.cgp
@@ -1,4 +1,4 @@
-# Date: Mon Jul 26 21:55:33 2010
+# Date: Fri Oct 15 07:50:19 2010
 
 SET addpads = false
 SET asysymbol = false
@@ -13,10 +13,10 @@ SET foundationsym = false
 SET implementationfiletype = Ngc
 SET package = fg456
 SET removerpms = false
-SET simulationfiles = Behavioral
+SET simulationfiles = Structural
 SET speedgrade = -5
 SET verilogsim = true
 SET vhdlsim = false
 SET workingdirectory = /tmp/
 
-# CRC: 394da717
+# CRC: 983b9b45
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise
new file mode 100644
index 000000000..70ee54054
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.gise
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_32x36_2clk.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_32x36_2clk.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ncf
new file mode 100644
index 000000000..e69de29bb
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc
new file mode 100644
index 000000000..d1ed419a7
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v
new file mode 100644
index 000000000..68a8caaf6
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.v
@@ -0,0 +1,3839 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: M.63c
+//  \   \         Application: netgen
+//  /   /         Filename: fifo_xlnx_32x36_2clk.v
+// /___/   /\     Timestamp: Fri Oct 15 00:50:08 2010
+// \   \  /  \ 
+//  \___\/\___\
+//             
+// Command	: -intstyle ise -w -sim -ofmt verilog /tmp/_cg/fifo_xlnx_32x36_2clk.ngc /tmp/_cg/fifo_xlnx_32x36_2clk.v 
+// Device	: 3s2000fg456-5
+// Input file	: /tmp/_cg/fifo_xlnx_32x36_2clk.ngc
+// Output file	: /tmp/_cg/fifo_xlnx_32x36_2clk.v
+// # of Modules	: 1
+// Design Name	: fifo_xlnx_32x36_2clk
+// Xilinx        : /opt/Xilinx/12.2/ISE_DS/ISE/
+//             
+// Purpose:    
+//     This verilog netlist is a verification model and uses simulation 
+//     primitives which may not represent the true implementation of the 
+//     device, however the netlist is functionally correct and should not 
+//     be modified. This file cannot be synthesized and should only be used 
+//     with supported simulation tools.
+//             
+// Reference:  
+//     Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//             
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module fifo_xlnx_32x36_2clk (
+  rd_en, almost_full, prog_full, wr_en, full, empty, wr_clk, rst, rd_clk, dout, din
+)/* synthesis syn_black_box syn_noprune=1 */;
+  input rd_en;
+  output almost_full;
+  output prog_full;
+  input wr_en;
+  output full;
+  output empty;
+  input wr_clk;
+  input rst;
+  input rd_clk;
+  output [35 : 0] dout;
+  input [35 : 0] din;
+  
+  // synthesis translate_off
+  
+  wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ;
+  wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ;
+  wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ;
+  wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ;
+  wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ;
+  wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ;
+  wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ;
+  wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ;
+  wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ;
+  wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ;
+  wire \BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ;
+  wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ;
+  wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ;
+  wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ;
+  wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ;
+  wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ;
+  wire \BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ;
+  wire \BU2/U0/grf.rf/gl0.rd/rpntr/N11 ;
+  wire \BU2/U0/grf.rf/gl0.wr/wpntr/N11 ;
+  wire \BU2/N16 ;
+  wire \BU2/N14 ;
+  wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ;
+  wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ;
+  wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ;
+  wire \BU2/U0/grf.rf/mem/dout_i_not0001 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N147 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N145 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N143 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N141 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N137 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N135 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N139 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N133 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N131 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N129 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N127 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N123 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N121 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N125 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N119 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N117 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N115 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N113 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N109 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N107 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N111 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N103 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N101 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N105 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N97 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N95 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N99 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N93 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N91 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N89 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N87 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N83 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N81 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N85 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N79 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N77 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N75 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N73 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N69 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N67 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N71 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N65 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N63 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N61 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N59 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N55 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N53 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N57 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N51 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N49 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N47 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N45 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N41 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N39 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N43 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N37 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N35 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N33 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N31 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N27 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N25 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N29 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N23 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N21 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N19 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N17 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N13 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N11 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N15 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N9 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N7 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/N5 ;
+  wire \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ;
+  wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ;
+  wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ;
+  wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ;
+  wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ;
+  wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ;
+  wire \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ;
+  wire \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ;
+  wire \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ;
+  wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ;
+  wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ;
+  wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ;
+  wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ;
+  wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ;
+  wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ;
+  wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ;
+  wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ;
+  wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ;
+  wire \BU2/U0/grf.rf/rstblk/wr_rst_comb ;
+  wire \BU2/U0/grf.rf/rstblk/rd_rst_comb ;
+  wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ;
+  wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ;
+  wire \BU2/U0/grf.rf/rstblk/rst_d1_93 ;
+  wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ;
+  wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ;
+  wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ;
+  wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ;
+  wire \BU2/U0/grf.rf/rstblk/rst_d2_88 ;
+  wire \BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ;
+  wire \BU2/U0/grf.rf/rstblk/rst_d3_86 ;
+  wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ;
+  wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ;
+  wire \BU2/N1 ;
+  wire NLW_VCC_P_UNCONNECTED;
+  wire NLW_GND_G_UNCONNECTED;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ;
+  wire \NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ;
+  wire [35 : 0] din_2;
+  wire [35 : 0] dout_3;
+  wire [35 : 0] \BU2/U0/grf.rf/mem/gdm.dm/dout_i ;
+  wire [35 : 0] \BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 ;
+  wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 ;
+  wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 ;
+  wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 ;
+  wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count ;
+  wire [5 : 4] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad ;
+  wire [5 : 1] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut ;
+  wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy ;
+  wire [5 : 4] \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 ;
+  wire [1 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state ;
+  wire [1 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 ;
+  wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 ;
+  wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count ;
+  wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc ;
+  wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc ;
+  wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 ;
+  wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg ;
+  wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 ;
+  wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg ;
+  wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin ;
+  wire [4 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin ;
+  wire [1 : 0] \BU2/U0/grf.rf/rstblk/wr_rst_reg ;
+  wire [2 : 0] \BU2/U0/grf.rf/rstblk/rd_rst_reg ;
+  wire [0 : 0] \BU2/rd_data_count ;
+  assign
+    dout[35] = dout_3[35],
+    dout[34] = dout_3[34],
+    dout[33] = dout_3[33],
+    dout[32] = dout_3[32],
+    dout[31] = dout_3[31],
+    dout[30] = dout_3[30],
+    dout[29] = dout_3[29],
+    dout[28] = dout_3[28],
+    dout[27] = dout_3[27],
+    dout[26] = dout_3[26],
+    dout[25] = dout_3[25],
+    dout[24] = dout_3[24],
+    dout[23] = dout_3[23],
+    dout[22] = dout_3[22],
+    dout[21] = dout_3[21],
+    dout[20] = dout_3[20],
+    dout[19] = dout_3[19],
+    dout[18] = dout_3[18],
+    dout[17] = dout_3[17],
+    dout[16] = dout_3[16],
+    dout[15] = dout_3[15],
+    dout[14] = dout_3[14],
+    dout[13] = dout_3[13],
+    dout[12] = dout_3[12],
+    dout[11] = dout_3[11],
+    dout[10] = dout_3[10],
+    dout[9] = dout_3[9],
+    dout[8] = dout_3[8],
+    dout[7] = dout_3[7],
+    dout[6] = dout_3[6],
+    dout[5] = dout_3[5],
+    dout[4] = dout_3[4],
+    dout[3] = dout_3[3],
+    dout[2] = dout_3[2],
+    dout[1] = dout_3[1],
+    dout[0] = dout_3[0],
+    din_2[35] = din[35],
+    din_2[34] = din[34],
+    din_2[33] = din[33],
+    din_2[32] = din[32],
+    din_2[31] = din[31],
+    din_2[30] = din[30],
+    din_2[29] = din[29],
+    din_2[28] = din[28],
+    din_2[27] = din[27],
+    din_2[26] = din[26],
+    din_2[25] = din[25],
+    din_2[24] = din[24],
+    din_2[23] = din[23],
+    din_2[22] = din[22],
+    din_2[21] = din[21],
+    din_2[20] = din[20],
+    din_2[19] = din[19],
+    din_2[18] = din[18],
+    din_2[17] = din[17],
+    din_2[16] = din[16],
+    din_2[15] = din[15],
+    din_2[14] = din[14],
+    din_2[13] = din[13],
+    din_2[12] = din[12],
+    din_2[11] = din[11],
+    din_2[10] = din[10],
+    din_2[9] = din[9],
+    din_2[8] = din[8],
+    din_2[7] = din[7],
+    din_2[6] = din[6],
+    din_2[5] = din[5],
+    din_2[4] = din[4],
+    din_2[3] = din[3],
+    din_2[2] = din[2],
+    din_2[1] = din[1],
+    din_2[0] = din[0];
+  VCC   VCC_0 (
+    .P(NLW_VCC_P_UNCONNECTED)
+  );
+  GND   GND_1 (
+    .G(NLW_GND_G_UNCONNECTED)
+  );
+  LUT3_L #(
+    .INIT ( 8'h90 ))
+  \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]),
+    .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 ),
+    .LO(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 )
+  );
+  LUT4_L #(
+    .INIT ( 16'h9000 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
+    .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 ),
+    .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 ),
+    .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 )
+  );
+  LUT4_L #(
+    .INIT ( 16'h9000 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+    .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 ),
+    .I3(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 )
+  );
+  LUT4_L #(
+    .INIT ( 16'h8421 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]),
+    .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
+    .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
+    .LO(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 )
+  );
+  LUT4_L #(
+    .INIT ( 16'h8241 ))
+  \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]),
+    .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+    .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+    .LO(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 )
+  );
+  LUT3_L #(
+    .INIT ( 8'h7F ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>111  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+    .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+    .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+    .LO(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 )
+  );
+  LUT3_L #(
+    .INIT ( 8'h7F ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>111  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+    .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+    .LO(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 )
+  );
+  LUT2_L #(
+    .INIT ( 4'h6 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_SW0  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
+    .LO(\BU2/N16 )
+  );
+  LUT2_L #(
+    .INIT ( 4'h6 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_SW0  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
+    .LO(\BU2/N14 )
+  );
+  INV   \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<0>11_INV_0  (
+    .I(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+    .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count )
+  );
+  INV   \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<0>11_INV_0  (
+    .I(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+    .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count )
+  );
+  LUT2 #(
+    .INIT ( 4'h2 ))
+  \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_1  (
+    .I0(wr_en),
+    .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+    .O(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 )
+  );
+  LUT4 #(
+    .INIT ( 16'h2333 ))
+  \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_1  (
+    .I0(rd_en),
+    .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
+    .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+    .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+    .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 )
+  );
+  LUT4 #(
+    .INIT ( 16'h6AAA ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3>12  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
+    .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+    .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+    .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+    .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 )
+  );
+  LUT4 #(
+    .INIT ( 16'h6AAA ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3>12  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+    .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+    .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+    .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 )
+  );
+  LUT3 #(
+    .INIT ( 8'h08 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1  (
+    .I0(wr_en),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
+    .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 )
+  );
+  LUT3 #(
+    .INIT ( 8'h10 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/write_ctrl  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
+    .I2(wr_en),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 )
+  );
+  LUT2 #(
+    .INIT ( 4'h9 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<5>  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5])
+  );
+  LUT4 #(
+    .INIT ( 16'h9000 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i78  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
+    .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i62_392 ),
+    .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 ),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 )
+  );
+  LUT4 #(
+    .INIT ( 16'h9000 ))
+  \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]),
+    .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+    .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000156_391 ),
+    .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 ),
+    .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 )
+  );
+  LUT2 #(
+    .INIT ( 4'h9 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<4>  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4])
+  );
+  LUT2 #(
+    .INIT ( 4'h9 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<3>  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3])
+  );
+  LUT2 #(
+    .INIT ( 4'h9 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<2>  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2])
+  );
+  LUT2 #(
+    .INIT ( 4'h9 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut<1>  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1])
+  );
+  LUT4 #(
+    .INIT ( 16'h5450 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000105  (
+    .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 ),
+    .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000079_390 ),
+    .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 )
+  );
+  LUT4 #(
+    .INIT ( 16'h9009 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
+    .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
+    .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000063_389 )
+  );
+  LUT4 #(
+    .INIT ( 16'h9009 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
+    .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
+    .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux000027_388 )
+  );
+  LUT4 #(
+    .INIT ( 16'h8421 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]),
+    .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
+    .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/dout_i26_387 )
+  );
+  LUT4 #(
+    .INIT ( 16'h5450 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000107  (
+    .I0(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
+    .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 ),
+    .I2(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ),
+    .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000069_386 ),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 )
+  );
+  LUT4 #(
+    .INIT ( 16'h9009 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+    .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
+    .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000067_384 )
+  );
+  LUT4 #(
+    .INIT ( 16'h9009 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
+    .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
+    .I3(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000026_383 )
+  );
+  LUT2 #(
+    .INIT ( 4'h2 ))
+  \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1  (
+    .I0(wr_en),
+    .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+    .O(\BU2/U0/grf.rf/gl0.wr/wpntr/count_not0001 )
+  );
+  LUT4 #(
+    .INIT ( 16'hECA0 ))
+  \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000183  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 ),
+    .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 ),
+    .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000158_380 ),
+    .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000063_381 ),
+    .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 )
+  );
+  LUT4 #(
+    .INIT ( 16'h9009 ))
+  \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]),
+    .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
+    .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]),
+    .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000115_379 )
+  );
+  LUT4 #(
+    .INIT ( 16'h8421 ))
+  \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]),
+    .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000062_378 )
+  );
+  LUT4 #(
+    .INIT ( 16'h8241 ))
+  \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]),
+    .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000026_377 )
+  );
+  LUT4 #(
+    .INIT ( 16'h2333 ))
+  \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21  (
+    .I0(rd_en),
+    .I1(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
+    .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+    .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+    .O(\BU2/U0/grf.rf/gl0.rd/rpntr/count_not0001 )
+  );
+  LUT3 #(
+    .INIT ( 8'hA6 ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<4>11  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
+    .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
+    .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/N11 ),
+    .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 )
+  );
+  LUT3 #(
+    .INIT ( 8'hA6 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<4>11  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
+    .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/N11 ),
+    .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 )
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N5 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N7 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1011  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N45 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N47 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1111  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N9 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N11 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX11111  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N49 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N51 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1211  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N53 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N55 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1311  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N57 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N59 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1411  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N61 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N63 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1511  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N65 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N67 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1611  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N69 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N71 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1711  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N73 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N75 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1811  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N77 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N79 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX1911  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N81 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N83 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2011  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N85 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N87 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2111  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N13 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N15 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX21111  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N89 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N91 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2211  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N93 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N95 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2311  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N97 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N99 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2411  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N101 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N103 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2511  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N105 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N107 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2611  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N109 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N111 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2711  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N113 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N115 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2811  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N117 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N119 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX2911  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N121 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N123 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3011  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N125 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N127 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3111  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N17 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N19 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX31111  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N129 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N131 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3211  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N133 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N135 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3311  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N137 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N139 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3411  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N141 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N143 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX3511  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N145 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N147 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX411  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N21 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N23 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX511  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N25 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N27 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX611  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N29 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N31 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX711  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N33 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N35 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX811  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N37 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N39 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8])
+  );
+  LUT3 #(
+    .INIT ( 8'hE4 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/inst_LPM_MUX911  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/mem/gdm.dm/N41 ),
+    .I2(\BU2/U0/grf.rf/mem/gdm.dm/N43 ),
+    .O(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9])
+  );
+  LUT4 #(
+    .INIT ( 16'h6996 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]),
+    .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+    .I3(\BU2/N16 ),
+    .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 )
+  );
+  LUT4 #(
+    .INIT ( 16'h6996 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]),
+    .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+    .I3(\BU2/N14 ),
+    .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 )
+  );
+  LUT3 #(
+    .INIT ( 8'hA2 ))
+  \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_REGOUT_EN11  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+    .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+    .I2(rd_en),
+    .O(\BU2/U0/grf.rf/mem/dout_i_not0001 )
+  );
+  LUT2 #(
+    .INIT ( 4'hD ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_not00011  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 ),
+    .I1(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 )
+  );
+  LUT4 #(
+    .INIT ( 16'h8E8A ))
+  \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux00001  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 ),
+    .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+    .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+    .I3(rd_en),
+    .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 )
+  );
+  LUT4 #(
+    .INIT ( 16'h6996 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00021  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]),
+    .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+    .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
+    .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 )
+  );
+  LUT4 #(
+    .INIT ( 16'h6996 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00021  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]),
+    .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+    .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
+    .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 )
+  );
+  LUT4 #(
+    .INIT ( 16'h40FF ))
+  \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<0>1  (
+    .I0(rd_en),
+    .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+    .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+    .I3(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 ),
+    .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0])
+  );
+  LUT3 #(
+    .INIT ( 8'h6A ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<2>11  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+    .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+    .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+    .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 )
+  );
+  LUT3 #(
+    .INIT ( 8'h6A ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<2>11  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+    .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+    .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 )
+  );
+  LUT3 #(
+    .INIT ( 8'h96 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00011  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
+    .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
+    .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 )
+  );
+  LUT3 #(
+    .INIT ( 8'h96 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00011  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
+    .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
+    .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 )
+  );
+  LUT3 #(
+    .INIT ( 8'hF2 ))
+  \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001<1>1  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0]),
+    .I1(rd_en),
+    .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1]),
+    .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1])
+  );
+  LUT3 #(
+    .INIT ( 8'h08 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux00031  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5]),
+    .I2(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 ),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 )
+  );
+  LUT2 #(
+    .INIT ( 4'h6 ))
+  \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0000_Result1  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 )
+  );
+  LUT2 #(
+    .INIT ( 4'h6 ))
+  \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0001_Result1  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 )
+  );
+  LUT2 #(
+    .INIT ( 4'h6 ))
+  \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0002_Result1  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 )
+  );
+  LUT2 #(
+    .INIT ( 4'h6 ))
+  \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0003_Result1  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 )
+  );
+  LUT2 #(
+    .INIT ( 4'h6 ))
+  \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0000_Result1  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 )
+  );
+  LUT2 #(
+    .INIT ( 4'h6 ))
+  \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0001_Result1  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 )
+  );
+  LUT2 #(
+    .INIT ( 4'h6 ))
+  \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0002_Result1  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 )
+  );
+  LUT2 #(
+    .INIT ( 4'h6 ))
+  \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0003_Result1  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 )
+  );
+  LUT2 #(
+    .INIT ( 4'h6 ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<1>11  (
+    .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+    .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+    .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 )
+  );
+  LUT2 #(
+    .INIT ( 4'h6 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<1>11  (
+    .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+    .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+    .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 )
+  );
+  LUT2 #(
+    .INIT ( 4'h6 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00001  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+    .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 )
+  );
+  LUT2 #(
+    .INIT ( 4'h6 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00001  (
+    .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
+    .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+    .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 )
+  );
+  LUT2 #(
+    .INIT ( 4'h4 ))
+  \BU2/U0/grf.rf/rstblk/rd_rst_comb1  (
+    .I0(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 ),
+    .I1(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ),
+    .O(\BU2/U0/grf.rf/rstblk/rd_rst_comb )
+  );
+  LUT2 #(
+    .INIT ( 4'h4 ))
+  \BU2/U0/grf.rf/rstblk/wr_rst_comb1  (
+    .I0(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 ),
+    .I1(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ),
+    .O(\BU2/U0/grf.rf/rstblk/wr_rst_comb )
+  );
+  FDPE #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ),
+    .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000 ),
+    .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+    .Q(almost_full)
+  );
+  FDP #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i  (
+    .C(wr_clk),
+    .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ),
+    .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+    .Q(full)
+  );
+  FDP #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i  (
+    .C(wr_clk),
+    .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_mux0000 ),
+    .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+    .Q(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_370 )
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_0  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0]),
+    .Q(dout_3[0])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_1  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1]),
+    .Q(dout_3[1])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_2  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2]),
+    .Q(dout_3[2])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_3  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3]),
+    .Q(dout_3[3])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_4  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4]),
+    .Q(dout_3[4])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_5  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5]),
+    .Q(dout_3[5])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_6  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6]),
+    .Q(dout_3[6])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_7  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7]),
+    .Q(dout_3[7])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_8  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8]),
+    .Q(dout_3[8])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_9  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9]),
+    .Q(dout_3[9])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_10  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10]),
+    .Q(dout_3[10])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_11  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11]),
+    .Q(dout_3[11])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_12  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12]),
+    .Q(dout_3[12])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_13  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13]),
+    .Q(dout_3[13])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_14  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14]),
+    .Q(dout_3[14])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_15  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15]),
+    .Q(dout_3[15])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_16  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16]),
+    .Q(dout_3[16])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_17  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17]),
+    .Q(dout_3[17])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_18  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18]),
+    .Q(dout_3[18])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_19  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19]),
+    .Q(dout_3[19])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_20  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20]),
+    .Q(dout_3[20])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_21  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21]),
+    .Q(dout_3[21])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_22  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22]),
+    .Q(dout_3[22])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_23  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23]),
+    .Q(dout_3[23])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_24  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24]),
+    .Q(dout_3[24])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_25  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25]),
+    .Q(dout_3[25])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_26  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26]),
+    .Q(dout_3[26])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_27  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27]),
+    .Q(dout_3[27])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_28  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28]),
+    .Q(dout_3[28])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_29  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29]),
+    .Q(dout_3[29])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_30  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30]),
+    .Q(dout_3[30])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_31  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31]),
+    .Q(dout_3[31])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_32  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32]),
+    .Q(dout_3[32])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_33  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33]),
+    .Q(dout_3[33])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_34  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34]),
+    .Q(dout_3[34])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/dout_i_35  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/mem/dout_i_not0001 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35]),
+    .Q(dout_3[35])
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[35]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM72_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N147 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[35]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM71_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N145 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[34]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM70_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N143 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[34]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM69_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N141 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[33]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM67_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N137 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[32]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM66_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N135 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[33]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM68_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N139 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[32]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM65_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N133 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[31]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM64_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N131 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[31]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM63_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N129 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[30]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM62_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N127 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[29]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM60_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N123 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[29]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM59_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N121 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[30]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM61_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N125 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[28]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM58_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N119 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[28]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM57_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N117 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[27]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM56_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N115 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[27]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM55_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N113 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[26]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM53_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N109 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[25]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM52_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N107 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[26]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM54_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N111 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[24]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM50_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N103 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[24]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM49_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N101 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[25]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM51_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N105 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[23]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM47_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N97 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[22]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM46_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N95 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[23]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM48_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N99 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[22]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM45_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N93 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[21]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM44_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N91 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[21]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM43_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N89 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[20]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM42_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N87 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[19]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM40_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N83 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[19]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM39_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N81 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[20]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM41_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N85 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[18]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM38_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N79 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[18]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM37_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N77 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[17]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM36_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N75 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[17]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM35_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N73 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[16]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM33_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N69 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[15]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM32_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N67 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[16]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM34_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N71 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[15]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM31_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N65 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[14]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM30_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N63 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[14]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM29_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N61 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[13]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM28_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N59 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[12]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM26_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N55 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[12]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM25_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N53 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[13]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM27_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N57 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[11]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM24_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N51 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[11]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM23_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N49 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[10]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM22_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N47 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[10]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM21_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N45 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[9]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM19_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N41 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[8]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM18_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N39 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[9]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM20_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N43 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[8]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM17_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N37 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[7]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM16_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N35 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[7]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM15_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N33 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[6]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM14_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N31 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[5]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM12_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N27 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[5]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM11_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N25 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[6]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM13_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N29 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[4]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM10_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N23 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[4]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM9_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N21 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[3]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N19 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[3]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM7_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N17 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[2]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM5_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N13 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[1]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM4_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N11 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[2]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM6_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N15 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[1]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM3_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N9 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[0]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl1_296 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N7 )
+  );
+  RAM16X1D   \BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1  (
+    .A0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0]),
+    .A1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1]),
+    .A2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2]),
+    .A3(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3]),
+    .D(din_2[0]),
+    .DPRA0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
+    .DPRA1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
+    .DPRA2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
+    .DPRA3(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
+    .WCLK(wr_clk),
+    .WE(\BU2/U0/grf.rf/mem/gdm.dm/write_ctrl_294 ),
+    .SPO(\NLW_BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_SPO_UNCONNECTED ),
+    .DPO(\BU2/U0/grf.rf/mem/gdm.dm/N5 )
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_35  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [35]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [35])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_34  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [34]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [34])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_33  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [33]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [33])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_32  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [32]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [32])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_31  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [31]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [31])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_30  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [30]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [30])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_29  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [29]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [29])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_28  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [28]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [28])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_27  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [27]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [27])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_26  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [26]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [26])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_25  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [25]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [25])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_24  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [24]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [24])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_23  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [23]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [23])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_22  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [22]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [22])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_21  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [21]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [21])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_20  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [20]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [20])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_19  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [19]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [19])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_18  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [18]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [18])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_17  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [17]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [17])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_16  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [16]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [16])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_15  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [15]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [15])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_14  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [14]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [14])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_13  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [13]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [13])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_12  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [12]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [12])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_11  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [11]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [11])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_10  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [10]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [10])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_9  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [9]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [9])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_8  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [8]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [8])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_7  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [7]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [7])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_6  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [6]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [6])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_5  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [5]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [5])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_4  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [4]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [4])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_3  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [3]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [3])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_2  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [2]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [2])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_1  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [1]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [1])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/mem/gdm.dm/dout_i_0  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/mem/gdm.dm/_varindex0000 [0]),
+    .Q(\BU2/U0/grf.rf/mem/gdm.dm/dout_i [0])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_0  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [0])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_1  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [1])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_2  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [2])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_3  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [3])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_4  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_4  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_3  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_1  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1])
+  );
+  FDPE #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_0  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]),
+    .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_2  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_4  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_3  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3])
+  );
+  FDPE #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_1  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
+    .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_0  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_2  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_2  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2])
+  );
+  FDPE #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_0  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ),
+    .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0])
+  );
+  FDPE #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_1  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ),
+    .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_3  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/wpntr/count_4  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ),
+    .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4])
+  );
+  FDPE #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_not0001 ),
+    .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i_mux0003 ),
+    .PRE(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+    .Q(prog_full)
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_4  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [4])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_5  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5]),
+    .Q(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad [5])
+  );
+  MUXCY   \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<0>  (
+    .CI(\BU2/N1 ),
+    .DI(\BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1_197 ),
+    .S(\BU2/rd_data_count [0]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0])
+  );
+  MUXCY   \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<1>  (
+    .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [0]),
+    .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
+    .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [1]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1])
+  );
+  MUXCY   \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<2>  (
+    .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [1]),
+    .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
+    .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [2]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2])
+  );
+  MUXCY   \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<3>  (
+    .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [2]),
+    .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
+    .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [3]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3])
+  );
+  MUXCY   \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy<4>  (
+    .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]),
+    .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
+    .S(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4])
+  );
+  XORCY   \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<4>  (
+    .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [3]),
+    .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [4]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [4])
+  );
+  XORCY   \BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_xor<5>  (
+    .CI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_cy [4]),
+    .LI(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/Madd_diff_pntr_pad_add0000_lut [5]),
+    .O(\BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_add0000 [5])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_0  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [1]),
+    .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [0])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_1  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_mux0001 [0]),
+    .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state [1])
+  );
+  FDP #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i  (
+    .C(rd_clk),
+    .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ),
+    .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .Q(empty)
+  );
+  FDP #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb  (
+    .C(rd_clk),
+    .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ),
+    .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_176 )
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
+    .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_1  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
+    .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_2  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
+    .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_3  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
+    .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_4  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
+    .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/count_2  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ),
+    .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2])
+  );
+  FDPE #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/count_0  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ),
+    .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/count_1  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ),
+    .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/count_3  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ),
+    .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3])
+  );
+  FDCE #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gl0.rd/rpntr/count_4  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/Mmux_RAM_RD_EN_FWFT21_160 ),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ),
+    .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_0  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_1  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_3  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_4  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d3 [4]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_2  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_4  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_0  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_2  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_0  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_3  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_4  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_0  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_1  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_2  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_3  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_4  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_0  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_3  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_4  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_0  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003_120 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_1  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_2  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_3  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_4  (
+    .C(rd_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003_110 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_1  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_2  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_3  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3])
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_4  (
+    .C(wr_clk),
+    .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
+    .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
+    .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4])
+  );
+  FDP #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/rstblk/wr_rst_reg_0  (
+    .C(wr_clk),
+    .D(\BU2/rd_data_count [0]),
+    .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ),
+    .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0])
+  );
+  FDP #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/rstblk/wr_rst_reg_1  (
+    .C(wr_clk),
+    .D(\BU2/rd_data_count [0]),
+    .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ),
+    .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1])
+  );
+  FDP #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/rstblk/rd_rst_reg_0  (
+    .C(rd_clk),
+    .D(\BU2/rd_data_count [0]),
+    .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
+    .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0])
+  );
+  FDP #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/rstblk/rd_rst_reg_1  (
+    .C(rd_clk),
+    .D(\BU2/rd_data_count [0]),
+    .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
+    .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1])
+  );
+  FDP #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/rstblk/rd_rst_reg_2  (
+    .C(rd_clk),
+    .D(\BU2/rd_data_count [0]),
+    .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
+    .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2])
+  );
+  FDP #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/rstblk/rst_d1  (
+    .C(wr_clk),
+    .D(\BU2/rd_data_count [0]),
+    .PRE(rst),
+    .Q(\BU2/U0/grf.rf/rstblk/rst_d1_93 )
+  );
+  FDPE   \BU2/U0/grf.rf/rstblk/rd_rst_asreg  (
+    .C(rd_clk),
+    .CE(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ),
+    .D(\BU2/rd_data_count [0]),
+    .PRE(rst),
+    .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 )
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1  (
+    .C(wr_clk),
+    .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 ),
+    .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 )
+  );
+  FDPE   \BU2/U0/grf.rf/rstblk/wr_rst_asreg  (
+    .C(wr_clk),
+    .CE(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ),
+    .D(\BU2/rd_data_count [0]),
+    .PRE(rst),
+    .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_95 )
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1  (
+    .C(rd_clk),
+    .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_94 ),
+    .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 )
+  );
+  FDP #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/rstblk/rst_d2  (
+    .C(wr_clk),
+    .D(\BU2/U0/grf.rf/rstblk/rst_d1_93 ),
+    .PRE(rst),
+    .Q(\BU2/U0/grf.rf/rstblk/rst_d2_88 )
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2  (
+    .C(wr_clk),
+    .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_91 ),
+    .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_92 )
+  );
+  FD #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2  (
+    .C(rd_clk),
+    .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_89 ),
+    .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_90 )
+  );
+  FDP #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/rstblk/rst_d3  (
+    .C(wr_clk),
+    .D(\BU2/U0/grf.rf/rstblk/rst_d2_88 ),
+    .PRE(rst),
+    .Q(\BU2/U0/grf.rf/rstblk/rst_d3_86 )
+  );
+  FDC #(
+    .INIT ( 1'b0 ))
+  \BU2/U0/grf.rf/rstblk/RST_FULL_GEN  (
+    .C(wr_clk),
+    .CLR(rst),
+    .D(\BU2/U0/grf.rf/rstblk/rst_d3_86 ),
+    .Q(\BU2/U0/grf.rf/rstblk/RST_FULL_GEN_87 )
+  );
+  FDP #(
+    .INIT ( 1'b1 ))
+  \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i  (
+    .C(rd_clk),
+    .D(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ),
+    .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
+    .Q(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_85 )
+  );
+  VCC   \BU2/XST_VCC  (
+    .P(\BU2/N1 )
+  );
+  GND   \BU2/XST_GND  (
+    .G(\BU2/rd_data_count [0])
+  );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo
new file mode 100644
index 000000000..eb98a2b70
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.veo
@@ -0,0 +1,47 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_32x36_2clk YourInstanceName (
+	.rst(rst),
+	.wr_clk(wr_clk),
+	.rd_clk(rd_clk),
+	.din(din), // Bus [35 : 0] 
+	.wr_en(wr_en),
+	.rd_en(rd_en),
+	.dout(dout), // Bus [35 : 0] 
+	.full(full),
+	.almost_full(almost_full),
+	.empty(empty),
+	.prog_full(prog_full));
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco
new file mode 100644
index 000000000..1cf4c8ba5
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xco
@@ -0,0 +1,84 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.2
+# Date: Fri Oct 15 07:50:15 2010
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = false
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -5
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.1
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=true
+CSET component_name=fifo_xlnx_32x36_2clk
+CSET data_count=false
+CSET data_count_width=5
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Independent_Clocks_Distributed_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=24
+CSET full_threshold_negate_value=23
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=36
+CSET input_depth=32
+CSET output_data_width=36
+CSET output_depth=32
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=5
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=5
+# END Parameters
+GENERATE
+# CRC: 8e84ee7f
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise
new file mode 100644
index 000000000..b9eb7bd1a
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk.xise
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="fifo_xlnx_32x36_2clk.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="fifo_xlnx_32x36_2clk.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="PostMapSimulation"/>
+      <association xil_pn:name="PostRouteSimulation"/>
+      <association xil_pn:name="PostTranslateSimulation"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_32x36_2clk.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_32x36_2clk" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-10-15T00:50:17" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F8449944117490A53CFE9CD2127BE2AA" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt
new file mode 100644
index 000000000..b8c69a9f7
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_flist.txt
@@ -0,0 +1,12 @@
+# Output products list for <fifo_xlnx_32x36_2clk>
+_xmsgs/pn_parser.xmsgs
+fifo_generator_ug175.pdf
+fifo_xlnx_32x36_2clk.gise
+fifo_xlnx_32x36_2clk.ngc
+fifo_xlnx_32x36_2clk.v
+fifo_xlnx_32x36_2clk.veo
+fifo_xlnx_32x36_2clk.xco
+fifo_xlnx_32x36_2clk.xise
+fifo_xlnx_32x36_2clk_flist.txt
+fifo_xlnx_32x36_2clk_readme.txt
+fifo_xlnx_32x36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt
new file mode 100644
index 000000000..8ab5679fd
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_readme.txt
@@ -0,0 +1,46 @@
+The following files were generated for 'fifo_xlnx_32x36_2clk' in directory 
+/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/
+
+fifo_generator_ug175.pdf:
+   Please see the core data sheet.
+
+fifo_xlnx_32x36_2clk.gise:
+   ISE Project Navigator support file. This is a generated file and should
+   not be edited directly.
+
+fifo_xlnx_32x36_2clk.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_32x36_2clk.v:
+   Unisim Verilog file containing the information required to simulate
+   the module.
+
+fifo_xlnx_32x36_2clk.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_32x36_2clk.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+fifo_xlnx_32x36_2clk.xise:
+   ISE Project Navigator support file. This is a generated file and should
+   not be edited directly.
+
+fifo_xlnx_32x36_2clk_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+fifo_xlnx_32x36_2clk_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+fifo_xlnx_32x36_2clk_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl
new file mode 100644
index 000000000..ec9426357
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_32x36_2clk_xmdf.tcl
@@ -0,0 +1,68 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_32x36_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_32x36_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_32x36_2clk
+}
+# ::fifo_xlnx_32x36_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_32x36_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_32x36_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_32x36_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise
new file mode 100644
index 000000000..9abec8c3e
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.gise
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.veo" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc
new file mode 100644
index 000000000..9cb73d5ce
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v
new file mode 100644
index 000000000..6ec1e3f88
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v
@@ -0,0 +1,173 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_xlnx_512x36_2clk_prog_full.v when simulating
+// the core, fifo_xlnx_512x36_2clk_prog_full. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_xlnx_512x36_2clk_prog_full(
+	rst,
+	wr_clk,
+	rd_clk,
+	din,
+	wr_en,
+	rd_en,
+	dout,
+	full,
+	almost_full,
+	empty,
+	prog_full);
+
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [35 : 0] din;
+input wr_en;
+input rd_en;
+output [35 : 0] dout;
+output full;
+output almost_full;
+output empty;
+output prog_full;
+
+// synthesis translate_off
+
+      FIFO_GENERATOR_V6_1 #(
+		.C_COMMON_CLOCK(0),
+		.C_COUNT_TYPE(0),
+		.C_DATA_COUNT_WIDTH(9),
+		.C_DEFAULT_VALUE("BlankString"),
+		.C_DIN_WIDTH(36),
+		.C_DOUT_RST_VAL("0"),
+		.C_DOUT_WIDTH(36),
+		.C_ENABLE_RLOCS(0),
+		.C_ENABLE_RST_SYNC(1),
+		.C_ERROR_INJECTION_TYPE(0),
+		.C_FAMILY("spartan3"),
+		.C_FULL_FLAGS_RST_VAL(1),
+		.C_HAS_ALMOST_EMPTY(0),
+		.C_HAS_ALMOST_FULL(1),
+		.C_HAS_BACKUP(0),
+		.C_HAS_DATA_COUNT(0),
+		.C_HAS_INT_CLK(0),
+		.C_HAS_MEMINIT_FILE(0),
+		.C_HAS_OVERFLOW(0),
+		.C_HAS_RD_DATA_COUNT(0),
+		.C_HAS_RD_RST(0),
+		.C_HAS_RST(1),
+		.C_HAS_SRST(0),
+		.C_HAS_UNDERFLOW(0),
+		.C_HAS_VALID(0),
+		.C_HAS_WR_ACK(0),
+		.C_HAS_WR_DATA_COUNT(0),
+		.C_HAS_WR_RST(0),
+		.C_IMPLEMENTATION_TYPE(2),
+		.C_INIT_WR_PNTR_VAL(0),
+		.C_MEMORY_TYPE(1),
+		.C_MIF_FILE_NAME("BlankString"),
+		.C_MSGON_VAL(1),
+		.C_OPTIMIZATION_MODE(0),
+		.C_OVERFLOW_LOW(0),
+		.C_PRELOAD_LATENCY(0),
+		.C_PRELOAD_REGS(1),
+		.C_PRIM_FIFO_TYPE("512x36"),
+		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+		.C_PROG_EMPTY_TYPE(0),
+		.C_PROG_FULL_THRESH_ASSERT_VAL(500),
+		.C_PROG_FULL_THRESH_NEGATE_VAL(499),
+		.C_PROG_FULL_TYPE(1),
+		.C_RD_DATA_COUNT_WIDTH(9),
+		.C_RD_DEPTH(512),
+		.C_RD_FREQ(1),
+		.C_RD_PNTR_WIDTH(9),
+		.C_UNDERFLOW_LOW(0),
+		.C_USE_DOUT_RST(1),
+		.C_USE_ECC(0),
+		.C_USE_EMBEDDED_REG(0),
+		.C_USE_FIFO16_FLAGS(0),
+		.C_USE_FWFT_DATA_COUNT(0),
+		.C_VALID_LOW(0),
+		.C_WR_ACK_LOW(0),
+		.C_WR_DATA_COUNT_WIDTH(9),
+		.C_WR_DEPTH(512),
+		.C_WR_FREQ(1),
+		.C_WR_PNTR_WIDTH(9),
+		.C_WR_RESPONSE_LATENCY(1))
+	inst (
+		.RST(rst),
+		.WR_CLK(wr_clk),
+		.RD_CLK(rd_clk),
+		.DIN(din),
+		.WR_EN(wr_en),
+		.RD_EN(rd_en),
+		.DOUT(dout),
+		.FULL(full),
+		.ALMOST_FULL(almost_full),
+		.EMPTY(empty),
+		.PROG_FULL(prog_full),
+		.BACKUP(),
+		.BACKUP_MARKER(),
+		.CLK(),
+		.SRST(),
+		.WR_RST(),
+		.RD_RST(),
+		.PROG_EMPTY_THRESH(),
+		.PROG_EMPTY_THRESH_ASSERT(),
+		.PROG_EMPTY_THRESH_NEGATE(),
+		.PROG_FULL_THRESH(),
+		.PROG_FULL_THRESH_ASSERT(),
+		.PROG_FULL_THRESH_NEGATE(),
+		.INT_CLK(),
+		.INJECTDBITERR(),
+		.INJECTSBITERR(),
+		.WR_ACK(),
+		.OVERFLOW(),
+		.ALMOST_EMPTY(),
+		.VALID(),
+		.UNDERFLOW(),
+		.DATA_COUNT(),
+		.RD_DATA_COUNT(),
+		.WR_DATA_COUNT(),
+		.PROG_EMPTY(),
+		.SBITERR(),
+		.DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo
new file mode 100644
index 000000000..64e6769d6
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.veo
@@ -0,0 +1,53 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_512x36_2clk_prog_full YourInstanceName (
+	.rst(rst),
+	.wr_clk(wr_clk),
+	.rd_clk(rd_clk),
+	.din(din), // Bus [35 : 0] 
+	.wr_en(wr_en),
+	.rd_en(rd_en),
+	.dout(dout), // Bus [35 : 0] 
+	.full(full),
+	.almost_full(almost_full),
+	.empty(empty),
+	.prog_full(prog_full));
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_xlnx_512x36_2clk_prog_full.v when simulating
+// the core, fifo_xlnx_512x36_2clk_prog_full. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco
new file mode 100644
index 000000000..f99c3c6fb
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xco
@@ -0,0 +1,84 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.2
+# Date: Thu Nov 11 17:27:10 2010
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = false
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.1
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=true
+CSET component_name=fifo_xlnx_512x36_2clk_prog_full
+CSET data_count=false
+CSET data_count_width=9
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=500
+CSET full_threshold_negate_value=499
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=36
+CSET input_depth=512
+CSET output_data_width=36
+CSET output_depth=512
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=9
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=9
+# END Parameters
+GENERATE
+# CRC: 6b9f6232
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise
new file mode 100644
index 000000000..91dbf5819
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.xise
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="12.1" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="fifo_xlnx_512x36_2clk_prog_full.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+      <association xil_pn:name="PostMapSimulation"/>
+      <association xil_pn:name="PostRouteSimulation"/>
+      <association xil_pn:name="PostTranslateSimulation"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc3s2000" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_xlnx_512x36_2clk_prog_full" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_xlnx_512x36_2clk_prog_full.ngc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_xlnx_512x36_2clk_prog_full" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="fg456" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_xlnx_512x36_2clk_prog_full" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-11-11T09:27:12" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="96435AE73456681FC0EF5839C85C4C97" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt
new file mode 100644
index 000000000..2eb837a3f
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_flist.txt
@@ -0,0 +1,12 @@
+# Output products list for <fifo_xlnx_512x36_2clk_prog_full>
+_xmsgs/pn_parser.xmsgs
+fifo_generator_ug175.pdf
+fifo_xlnx_512x36_2clk_prog_full.gise
+fifo_xlnx_512x36_2clk_prog_full.ngc
+fifo_xlnx_512x36_2clk_prog_full.v
+fifo_xlnx_512x36_2clk_prog_full.veo
+fifo_xlnx_512x36_2clk_prog_full.xco
+fifo_xlnx_512x36_2clk_prog_full.xise
+fifo_xlnx_512x36_2clk_prog_full_flist.txt
+fifo_xlnx_512x36_2clk_prog_full_readme.txt
+fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt
new file mode 100644
index 000000000..33d50a91d
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_readme.txt
@@ -0,0 +1,47 @@
+The following files were generated for 'fifo_xlnx_512x36_2clk_prog_full' in directory 
+/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/
+
+fifo_generator_ug175.pdf:
+   Please see the core data sheet.
+
+fifo_xlnx_512x36_2clk_prog_full.gise:
+   ISE Project Navigator support file. This is a generated file and should
+   not be edited directly.
+
+fifo_xlnx_512x36_2clk_prog_full.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_512x36_2clk_prog_full.v:
+   Verilog wrapper file provided to support functional simulation.
+   This file contains simulation model customization data that is
+   passed to a parameterized simulation model for the core.
+
+fifo_xlnx_512x36_2clk_prog_full.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_512x36_2clk_prog_full.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+fifo_xlnx_512x36_2clk_prog_full.xise:
+   ISE Project Navigator support file. This is a generated file and should
+   not be edited directly.
+
+fifo_xlnx_512x36_2clk_prog_full_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+fifo_xlnx_512x36_2clk_prog_full_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl
new file mode 100644
index 000000000..e1aecccff
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl
@@ -0,0 +1,68 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_512x36_2clk_prog_full_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_512x36_2clk_prog_full_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk_prog_full
+}
+# ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_512x36_2clk_prog_full_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_prog_full_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk_prog_full
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/extramfifo/ext_fifo.v b/fpga/usrp2/extramfifo/ext_fifo.v
index 6888617a7..80f82fc63 100644
--- a/fpga/usrp2/extramfifo/ext_fifo.v
+++ b/fpga/usrp2/extramfifo/ext_fifo.v
@@ -45,9 +45,7 @@ module ext_fifo
    wire [EXT_WIDTH-1:0] write_data;
    wire [EXT_WIDTH-1:0] read_data;
    wire 		full1, empty1;
-   wire 		almost_full2, full2, empty2;
-   wire [INT_WIDTH-1:0] data_to_fifo;
-   wire [INT_WIDTH-1:0] data_from_fifo;
+   wire 		almost_full2, almost_full2_spread, full2, empty2;
    wire [FIFO_DEPTH-1:0] capacity;
    wire 		 space_avail;
    wire 		 data_avail;
@@ -134,17 +132,17 @@ module ext_fifo
 						       .empty(empty1));
 	 
 	 // FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP.
-	 fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk_i2 (
-						       .rst(rst),
-						       .wr_clk(ext_clk),
-						       .rd_clk(int_clk),
-						       .din(read_data), // Bus [35 : 0] 
-						       .wr_en(write_output_fifo),
-						       .rd_en(dst_rdy_i),
-						       .dout(dataout), // Bus [35 : 0] 
-						       .full(full2),
-						       .empty(empty2),
-						       .prog_full(almost_full2));
+	 fifo_xlnx_512x36_2clk_prog_full fifo_xlnx_32x36_2clk_prog_full_i1 (
+									    .rst(rst),
+									    .wr_clk(ext_clk),
+									    .rd_clk(int_clk),
+									    .din(read_data), // Bus [35 : 0] 
+									    .wr_en(write_output_fifo),
+									    .rd_en(dst_rdy_i),
+									    .dout(dataout), // Bus [35 : 0] 
+									    .full(full2),
+									    .empty(empty2),
+									    .prog_full(almost_full2));
 
       end    
    endgenerate
@@ -158,13 +156,14 @@ module ext_fifo
 			   .full_out(almost_full2_spread)
 			   );
    
-   
-   always @ (posedge int_clk)
-     debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i };
+//   always @ (posedge int_clk)
+//     debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i };
    
    always @ (posedge ext_clk)
-     debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 };
-
+ //    debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 };
+     debug[31:0] <= {7'h0,src_rdy_i,read_input_fifo,write_output_fifo,dst_rdy_i,full2,almost_full2,empty2,full1,empty1,write_data[7:0],read_data[7:0]};
+   
+     
    always@ (posedge ext_clk)
      //     debug2[31:0] <= {write_data[15:0],read_data[15:0]};
      debug2[31:0] <= 0;
diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.sh b/fpga/usrp2/extramfifo/ext_fifo_tb.sh
old mode 100644
new mode 100755
diff --git a/fpga/usrp2/extramfifo/nobl_fifo.v b/fpga/usrp2/extramfifo/nobl_fifo.v
index 4c009d980..0b63768fc 100644
--- a/fpga/usrp2/extramfifo/nobl_fifo.v
+++ b/fpga/usrp2/extramfifo/nobl_fifo.v
@@ -70,26 +70,27 @@ module nobl_fifo
    // Simple NoBL SRAM interface, 4 cycle read latency.
    // Read/Write arbitration via temprary application of empty/full flags.
    //
-   nobl_if nobl_if_i1
-     (
-      .clk(clk),
-      .rst(rst),
-      .RAM_D_pi(RAM_D_pi),
-      .RAM_D_po(RAM_D_po),
-      .RAM_D_poe(RAM_D_poe),
-      .RAM_A(RAM_A),
-      .RAM_WEn(RAM_WEn),
-      .RAM_CENn(RAM_CENn),
-      .RAM_LDn(RAM_LDn),
-      .RAM_OEn(RAM_OEn),
-      .RAM_CE1n(RAM_CE1n),
-      .address(address),
-      .data_out(write_data),
-      .data_in(read_data),
-      .data_in_valid(data_avail),
-      .write(write),
-      .enable(enable)
-      );
+   nobl_if #(.WIDTH(WIDTH),.DEPTH(RAM_DEPTH))
+     nobl_if_i1
+       (
+	.clk(clk),
+	.rst(rst),
+	.RAM_D_pi(RAM_D_pi),
+	.RAM_D_po(RAM_D_po),
+	.RAM_D_poe(RAM_D_poe),
+	.RAM_A(RAM_A),
+	.RAM_WEn(RAM_WEn),
+	.RAM_CENn(RAM_CENn),
+	.RAM_LDn(RAM_LDn),
+	.RAM_OEn(RAM_OEn),
+	.RAM_CE1n(RAM_CE1n),
+	.address(address),
+	.data_out(write_data),
+	.data_in(read_data),
+	.data_in_valid(data_avail),
+	.write(write),
+	.enable(enable)
+	);
 
    
 
diff --git a/fpga/usrp2/extramfifo/nobl_if.v b/fpga/usrp2/extramfifo/nobl_if.v
index adf9f165b..b5ebe9c6b 100644
--- a/fpga/usrp2/extramfifo/nobl_if.v
+++ b/fpga/usrp2/extramfifo/nobl_if.v
@@ -56,18 +56,21 @@ module nobl_if
 	  address_pipe1 <= 0;
 	  write_pipe1 <= 0;
 	  data_out_pipe1  <= 0;
+	  RAM_WEn <= 1;
+	  RAM_CE1n <= 1;
+	  
        end
      else
        begin
 	  enable_pipe1 <= enable;
-	  RAM_CE1n <= ~enable;  // Creates IOB flob
-	  
+	  RAM_CE1n <= ~enable;  // Creates IOB flop
+	  RAM_WEn <= ~write;  // Creates IOB flop
 	  
 	  if (enable)
 	    begin
 	       address_pipe1 <= address_gray;
 	       write_pipe1 <= write;
-	       RAM_WEn <= ~write;  // Creates IOB flob
+//	       RAM_WEn <= ~write;  // Creates IOB flop
 	       
 	       
 	       if (write)
diff --git a/fpga/usrp2/fifo/.gitignore b/fpga/usrp2/fifo/.gitignore
index cba7efc8e..866f1faad 100644
--- a/fpga/usrp2/fifo/.gitignore
+++ b/fpga/usrp2/fifo/.gitignore
@@ -1 +1,3 @@
+*.vcd
+*.lxt
 a.out
diff --git a/fpga/usrp2/fifo/fifo19_to_fifo36.v b/fpga/usrp2/fifo/fifo19_to_fifo36.v
index 5f9aeff9b..2f530109f 100644
--- a/fpga/usrp2/fifo/fifo19_to_fifo36.v
+++ b/fpga/usrp2/fifo/fifo19_to_fifo36.v
@@ -1,26 +1,32 @@
 
+// Parameter LE tells us if we are little-endian.  
+// Little-endian means send lower 16 bits first.
+// Default is big endian (network order), send upper bits first.
+
 module fifo19_to_fifo36
-  (input clk, input reset, input clear,
-   input [18:0] f19_datain,
-   input f19_src_rdy_i,
-   output f19_dst_rdy_o,
+  #(parameter LE=0)
+   (input clk, input reset, input clear,
+    input [18:0] f19_datain,
+    input f19_src_rdy_i,
+    output f19_dst_rdy_o,
 
-   output [35:0] f36_dataout,
-   output f36_src_rdy_o,
-   input f36_dst_rdy_i,
-   output [31:0] debug
-   );
+    output [35:0] f36_dataout,
+    output f36_src_rdy_o,
+    input f36_dst_rdy_i,
+    output [31:0] debug
+    );
 
-   reg 	 f36_sof, f36_eof, f36_occ;
+   reg 		  f36_sof, f36_eof;
+   reg [1:0] 	  f36_occ;
    
-   reg [1:0] state;
-   reg [15:0] dat0, dat1;
+   reg [1:0] 	  state;
+   reg [15:0] 	  dat0, dat1;
 
-   wire f19_sof  = f19_datain[16];
-   wire f19_eof  = f19_datain[17];
-   wire f19_occ  = f19_datain[18];
+   wire 	  f19_sof  = f19_datain[16];
+   wire 	  f19_eof  = f19_datain[17];
+   wire 	  f19_occ  = f19_datain[18];
 
-   wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
+   wire 	  xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
 
    always @(posedge clk)
      if(f19_src_rdy_i & ((state==0)|xfer_out))
@@ -68,7 +74,8 @@ module fifo19_to_fifo36
        dat0 		   <= f19_datain;
    
    assign    f19_dst_rdy_o  = xfer_out | (state != 2);
-   assign    f36_dataout    = {f36_occ,f36_eof,f36_sof,dat0,dat1};
+   assign    f36_dataout    = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} :
+			      {f36_occ,f36_eof,f36_sof,dat0,dat1};
    assign    f36_src_rdy_o  = (state == 2);
 
    assign    debug = state;
diff --git a/fpga/usrp2/fifo/fifo36_to_fifo18.v b/fpga/usrp2/fifo/fifo36_to_fifo18.v
deleted file mode 100644
index b636ab9ca..000000000
--- a/fpga/usrp2/fifo/fifo36_to_fifo18.v
+++ /dev/null
@@ -1,40 +0,0 @@
-
-module fifo36_to_fifo18
-  (input clk, input reset, input clear,
-   input [35:0] f36_datain,
-   input f36_src_rdy_i,
-   output f36_dst_rdy_o,
-   
-   output [17:0] f18_dataout,
-   output f18_src_rdy_o,
-   input f18_dst_rdy_i );
-
-   wire   f36_sof  = f36_datain[32];
-   wire   f36_eof  = f36_datain[33];
-   wire   f36_occ  = f36_datain[35:34];
-
-   reg phase;
-
-   wire half_line 	   = f36_eof & ((f36_occ==1)|(f36_occ==2));
-   
-   assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
-   assign f18_dataout[16]  = phase ? 0 : f36_sof;
-   assign f18_dataout[17]  = phase ? f36_eof : half_line;
-   
-   assign f18_src_rdy_o    = f36_src_rdy_i;
-   assign f36_dst_rdy_o    = (phase | half_line) & f18_dst_rdy_i;
-	
-   wire f18_xfer 	   = f18_src_rdy_o & f18_dst_rdy_i;
-   wire f36_xfer 	   = f36_src_rdy_i & f36_dst_rdy_o;
-
-   always @(posedge clk)
-     if(reset)
-       phase 		  <= 0;
-     else if(f36_xfer)
-       phase 		  <= 0;
-     else if(f18_xfer)
-       phase 		  <= 1;
-   
-       
-endmodule // fifo36_to_fifo18
-
diff --git a/fpga/usrp2/fifo/fifo36_to_fifo19.v b/fpga/usrp2/fifo/fifo36_to_fifo19.v
index de249aaeb..517a2a476 100644
--- a/fpga/usrp2/fifo/fifo36_to_fifo19.v
+++ b/fpga/usrp2/fifo/fifo36_to_fifo19.v
@@ -1,33 +1,38 @@
 
-module fifo36_to_fifo19
-  (input clk, input reset, input clear,
-   input [35:0] f36_datain,
-   input f36_src_rdy_i,
-   output f36_dst_rdy_o,
-   
-   output [18:0] f19_dataout,
-   output f19_src_rdy_o,
-   input f19_dst_rdy_i );
+// Parameter LE tells us if we are little-endian.  
+// Little-endian means send lower 16 bits first.
+// Default is big endian (network order), send upper bits first.
 
+module fifo36_to_fifo19
+  #(parameter LE=0)
+   (input clk, input reset, input clear,
+    input [35:0] f36_datain,
+    input f36_src_rdy_i,
+    output f36_dst_rdy_o,
+    
+    output [18:0] f19_dataout,
+    output f19_src_rdy_o,
+    input f19_dst_rdy_i );
+   
    wire   f36_sof  = f36_datain[32];
    wire   f36_eof  = f36_datain[33];
    wire   f36_occ  = f36_datain[35:34];
-
-   reg phase;
-
-   wire half_line 	   = f36_eof & ((f36_occ==1)|(f36_occ==2));
    
-   assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
+   reg 	  phase;
+   
+   wire   half_line 	   = f36_eof & ((f36_occ==1)|(f36_occ==2));
+   
+   assign f19_dataout[15:0] = (LE ^ phase) ? f36_datain[15:0] : f36_datain[31:16];
    assign f19_dataout[16]  = phase ? 0 : f36_sof;
    assign f19_dataout[17]  = phase ? f36_eof : half_line;
    assign f19_dataout[18]  = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3));
    
    assign f19_src_rdy_o    = f36_src_rdy_i;
    assign f36_dst_rdy_o    = (phase | half_line) & f19_dst_rdy_i;
-	
-   wire f19_xfer 	   = f19_src_rdy_o & f19_dst_rdy_i;
-   wire f36_xfer 	   = f36_src_rdy_i & f36_dst_rdy_o;
-
+   
+   wire   f19_xfer 	   = f19_src_rdy_o & f19_dst_rdy_i;
+   wire   f36_xfer 	   = f36_src_rdy_i & f36_dst_rdy_o;
+   
    always @(posedge clk)
      if(reset)
        phase 		  <= 0;
@@ -36,6 +41,5 @@ module fifo36_to_fifo19
      else if(f19_xfer)
        phase 		  <= 1;
    
-       
+   
 endmodule // fifo36_to_fifo19
-
diff --git a/fpga/usrp2/fifo/fifo36_to_ll8.v b/fpga/usrp2/fifo/fifo36_to_ll8.v
index 0dee1dfc6..9604d0e38 100644
--- a/fpga/usrp2/fifo/fifo36_to_ll8.v
+++ b/fpga/usrp2/fifo/fifo36_to_ll8.v
@@ -55,6 +55,5 @@ module fifo36_to_ll8
 
    assign advance 	 = ll_src_rdy & ll_dst_rdy;
    assign f36_dst_rdy_o  = advance & ((state==3)|ll_eof);
-   assign debug 	 = state;
    
 endmodule // ll8_to_fifo36
diff --git a/fpga/usrp2/gpmc/.gitignore b/fpga/usrp2/gpmc/.gitignore
new file mode 100644
index 000000000..3e14fa4f7
--- /dev/null
+++ b/fpga/usrp2/gpmc/.gitignore
@@ -0,0 +1,2 @@
+*.gif
+
diff --git a/fpga/usrp2/gpmc/Makefile.srcs b/fpga/usrp2/gpmc/Makefile.srcs
new file mode 100644
index 000000000..bff6ae3e0
--- /dev/null
+++ b/fpga/usrp2/gpmc/Makefile.srcs
@@ -0,0 +1,20 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# SERDES Sources
+##################################################
+GPMC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpmc/, \
+dbsm.v \
+edge_sync.v \
+fifo_to_gpmc_async.v \
+fifo_to_gpmc_sync.v \
+fifo_watcher.v \
+gpmc_async.v \
+gpmc_sync.v \
+gpmc_to_fifo_async.v \
+gpmc_to_fifo_sync.v \
+gpmc_wb.v \
+ram_to_fifo.v \
+))
diff --git a/fpga/usrp2/gpmc/burst_data_write.txt b/fpga/usrp2/gpmc/burst_data_write.txt
new file mode 100644
index 000000000..3b5dfc785
--- /dev/null
+++ b/fpga/usrp2/gpmc/burst_data_write.txt
@@ -0,0 +1,16 @@
+# OMAP burst writes to FPGA
+
+CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z.
+CLK=1.
+CLK=0,nWE=0,nCS=0,DATA=WR_DATA1.
+CLK=1.
+CLK=0,nWE=0,nCS=0,DATA=WR_DATA2.
+CLK=1.
+CLK=0,nWE=0,nCS=0,DATA=WR_DATA3.
+CLK=1.
+CLK=0,nWE=0,nCS=0,DATA=WR_DATA4.
+CLK=1.
+CLK=0,nWE=1,nCS=1,DATA=Z.
+CLK=1.
+
+
diff --git a/fpga/usrp2/gpmc/dbsm.v b/fpga/usrp2/gpmc/dbsm.v
new file mode 100644
index 000000000..530af7205
--- /dev/null
+++ b/fpga/usrp2/gpmc/dbsm.v
@@ -0,0 +1,80 @@
+
+module bsm
+  (input clk, input reset, input clear,
+   input write_done,
+   input read_done,
+   output readable,
+   output writeable);
+
+   reg 	  state;
+   localparam ST_WRITEABLE = 0;
+   localparam ST_READABLE = 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state <= ST_WRITEABLE;
+     else
+       case(state)
+	 ST_WRITEABLE :
+	   if(write_done)
+	     state <= ST_READABLE;
+	 ST_READABLE :
+	   if(read_done)
+	     state <= ST_WRITEABLE;
+       endcase // case (state)
+
+   assign readable = (state == ST_READABLE);
+   assign writeable = (state == ST_WRITEABLE);
+   
+endmodule // bsm
+
+module dbsm
+  (input clk, input reset, input clear,
+   output reg read_sel, output read_ready, input read_done,
+   output reg write_sel, output write_ready, input write_done);
+
+   localparam NUM_BUFS = 2;
+
+   wire       [NUM_BUFS-1:0] readable, writeable, read_done_buf, write_done_buf;
+   
+   // Two of these buffer state machines
+   genvar     i;
+   generate
+      for(i=0;i<NUM_BUFS;i=i+1)
+	begin : BSMS
+	   bsm bsm(.clk(clk), .reset(reset), .clear(clear),
+		   .write_done((write_sel == i) & write_done),
+		   .read_done((read_sel == i) & read_done),
+		   .readable(readable[i]), .writeable(writeable[i]));
+	end
+   endgenerate
+   
+   reg 	 full;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  write_sel <= 0;
+	  full <= 0;
+       end
+     else
+       if(write_done & writeable[write_sel])
+	 if(write_sel ==(NUM_BUFS-1))
+	   write_sel <= 0;
+	 else
+	   write_sel <= write_sel + 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       read_sel <= 0;
+     else
+       if(read_done & readable[read_sel])
+	 if(read_sel==(NUM_BUFS-1))
+	   read_sel <= 0;
+	 else
+	   read_sel <= read_sel + 1;
+          
+   assign write_ready = writeable[write_sel];
+   assign read_ready = readable[read_sel];
+
+endmodule // dbsm
diff --git a/fpga/usrp2/gpmc/edge_sync.v b/fpga/usrp2/gpmc/edge_sync.v
new file mode 100644
index 000000000..5d9417c08
--- /dev/null
+++ b/fpga/usrp2/gpmc/edge_sync.v
@@ -0,0 +1,22 @@
+
+
+module edge_sync
+  #(parameter POSEDGE = 1)
+   (input clk,
+    input rst,
+    input sig,
+    output trig);
+   
+   reg [1:0] delay;
+   
+   always @(posedge clk)
+     if(rst)
+       delay <= 2'b00;
+     else
+       delay <= {delay[0],sig};
+   
+   assign trig = POSEDGE ? (delay==2'b01) : (delay==2'b10);
+   
+endmodule // edge_sync
+
+
diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc_async.v b/fpga/usrp2/gpmc/fifo_to_gpmc_async.v
new file mode 100644
index 000000000..cf8b6e861
--- /dev/null
+++ b/fpga/usrp2/gpmc/fifo_to_gpmc_async.v
@@ -0,0 +1,37 @@
+
+// Assumes an asynchronous GPMC cycle
+//   If a packet bigger or smaller than we are told is sent, behavior is undefined.
+//   If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
+//   If there is a bus error, we should be reset
+
+module fifo_to_gpmc_async
+  (input clk, input reset, input clear,
+   input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
+   output [15:0] EM_D, input EM_NCS, input EM_NOE,
+   input [15:0] frame_len);
+
+   // Synchronize the async control signals
+   reg [2:0] 	cs_del, oe_del;
+   reg [15:0] 	counter;
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  cs_del <= 3'b11;
+	  oe_del <= 3'b11;
+       end
+     else
+       begin
+	  cs_del <= { cs_del[1:0], EM_NCS };
+	  oe_del <= { oe_del[1:0], EM_NOE };
+       end
+
+   wire do_read = ( (~cs_del[1] | ~cs_del[2]) & (oe_del[1:0] == 2'b01));  // change output on trailing edge
+   wire first_read = (counter == 0);
+   wire last_read = ((counter+1) == frame_len);
+
+   assign EM_D = data_i[15:0];
+
+   assign dst_rdy_o = do_read;
+
+endmodule // fifo_to_gpmc_async
diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v b/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v
new file mode 100644
index 000000000..ef59d7137
--- /dev/null
+++ b/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v
@@ -0,0 +1,26 @@
+
+// Assumes a GPMC cycle with GPMC clock, as in the timing diagrams
+//   If a packet bigger or smaller than we are told is sent, behavior is undefined.
+//   If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
+//   If there is a bus error, we should be reset
+
+module fifo_to_gpmc_sync
+  (input arst,
+   input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
+   input EM_CLK, output [15:0] EM_D, input EM_NCS, input EM_NOE,
+   output fifo_ready, 
+   output reg bus_error);
+
+   assign EM_D = data_i[15:0];
+   wire       read_access = ~EM_NCS & ~EM_NOE;
+
+   assign dst_rdy_o = read_access;
+
+   always @(posedge EM_CLK or posedge arst)
+     if(arst)
+       bus_error <= 0;
+     else if(dst_rdy_o & ~src_rdy_i)
+       bus_error <= 1;
+   
+
+endmodule // fifo_to_gpmc_sync
diff --git a/fpga/usrp2/gpmc/fifo_watcher.v b/fpga/usrp2/gpmc/fifo_watcher.v
new file mode 100644
index 000000000..fe4e35de3
--- /dev/null
+++ b/fpga/usrp2/gpmc/fifo_watcher.v
@@ -0,0 +1,56 @@
+
+
+module fifo_watcher
+  (input clk, input reset, input clear,
+   input src_rdy1, input dst_rdy1, input sof1, input eof1,
+   input src_rdy2, input dst_rdy2, input sof2, input eof2,
+   output reg have_packet, output [15:0] length, output reg bus_error,
+   output [31:0] debug);
+
+   wire   write = src_rdy1 & dst_rdy1 & eof1;
+   wire   read = src_rdy2 & dst_rdy2 & eof2;
+   wire   have_packet_int;
+   reg [15:0] counter;
+   wire [4:0] pkt_count;
+   assign debug = pkt_count;
+   
+   fifo_short #(.WIDTH(16)) frame_lengths
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(counter), .src_rdy_i(write), .dst_rdy_o(),
+      .dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read),
+      .occupied(pkt_count), .space());
+
+   always @(posedge clk)
+     if(reset | clear)
+       counter <= 1;   // Start at 1
+     else if(src_rdy1 & dst_rdy1)
+       if(eof1)
+	 counter <= 1;
+       else
+	 counter <= counter + 1;
+
+   always @(posedge clk)
+     if(reset | clear)
+       bus_error <= 0;
+     else if(dst_rdy2 & ~src_rdy2)
+       bus_error <= 1;
+     else if(read & ~have_packet_int)
+       bus_error <= 1;
+
+   reg 	      in_packet;
+   always @(posedge clk)
+     if(reset | clear)
+       have_packet <= 0;
+     else 
+       have_packet <= (have_packet_int & ~in_packet) | (pkt_count>1) ;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       in_packet <= 0;
+     else if(src_rdy2 & dst_rdy2)
+       if(eof2)
+	 in_packet <= 0;
+       else
+	 in_packet <= 1;
+   
+endmodule // fifo_watcher
diff --git a/fpga/usrp2/gpmc/gpmc_async.v b/fpga/usrp2/gpmc/gpmc_async.v
new file mode 100644
index 000000000..23bad56ae
--- /dev/null
+++ b/fpga/usrp2/gpmc/gpmc_async.v
@@ -0,0 +1,130 @@
+//////////////////////////////////////////////////////////////////////////////////
+
+module gpmc_async
+  #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11)
+   (// GPMC signals
+    input arst,
+    input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+    input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
+    
+    // GPIOs for FIFO signalling
+    output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset,
+    
+    // Wishbone signals
+    input wb_clk, input wb_rst,
+    output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
+    output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
+    
+    // FIFO interface
+    input fifo_clk, input fifo_rst, input clear_tx, input clear_rx,
+    output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
+    input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
+    
+    input [15:0] tx_frame_len, output [15:0] rx_frame_len,
+    
+    output [31:0] debug
+    );
+
+   wire 	  EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
+   wire [15:0] 	  EM_D_fifo;
+   wire [15:0] 	  EM_D_wb;
+   
+   assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb;
+   
+   wire 	  bus_error_tx, bus_error_rx;
+   
+   always @(posedge fifo_clk)
+     if(fifo_rst | clear_tx | clear_rx)
+       bus_error <= 0;
+     else
+       bus_error <= bus_error_tx | bus_error_rx;
+   
+   // CS4 is RAM_2PORT for DATA PATH (high-speed data)
+   //    Writes go into one RAM, reads come from the other
+   // CS6 is for CONTROL PATH (wishbone)
+
+   // ////////////////////////////////////////////
+   // TX Data Path
+
+   wire [17:0] 	  tx18_data, tx18b_data;
+   wire 	  tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
+   wire [15:0] 	  tx_fifo_space;
+   wire [35:0] 	  tx36_data;
+   wire 	  tx36_src_rdy, tx36_dst_rdy;
+   
+   gpmc_to_fifo_async gpmc_to_fifo_async
+     (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
+      .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .clear(clear_tx),
+      .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
+      .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space),
+      .bus_error(bus_error_tx) );
+   
+   fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+      .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space),
+      .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied());
+
+   fifo19_to_fifo36 #(.LE(1)) f19_to_f36   // Little endian because ARM is LE
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+      .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
+      .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
+      .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
+      .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
+
+   // ////////////////////////////////////////////
+   // RX Data Path
+   
+   wire [17:0] 	  rx18_data, rx18b_data;
+   wire 	  rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
+   wire [15:0] 	  rx_fifo_space;
+   wire [35:0] 	  rx36_data;
+   wire 	  rx36_src_rdy, rx36_dst_rdy;
+   wire 	  dummy;
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
+      .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
+      .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
+
+   fifo36_to_fifo19 #(.LE(1)) f36_to_f19   // Little endian because ARM is LE
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
+      .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
+
+   fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space),
+      .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied());
+
+   fifo_to_gpmc_async fifo_to_gpmc_async
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy),
+      .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE),
+      .frame_len(rx_frame_len) );
+
+   wire [31:0] 	pkt_count;
+   
+   fifo_watcher fifo_watcher
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]),
+      .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]),
+      .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx),
+      .debug(pkt_count));
+
+   // ////////////////////////////////////////////
+   // Control path on CS6
+   
+   gpmc_wb gpmc_wb
+     (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE),
+      .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
+      .wb_clk(wb_clk), .wb_rst(wb_rst),
+      .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso),
+      .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
+      .wb_ack_i(wb_ack_i) );
+   
+      assign debug = pkt_count;
+   
+endmodule // gpmc_async
diff --git a/fpga/usrp2/gpmc/gpmc_sync.v b/fpga/usrp2/gpmc/gpmc_sync.v
new file mode 100644
index 000000000..61c54a793
--- /dev/null
+++ b/fpga/usrp2/gpmc/gpmc_sync.v
@@ -0,0 +1,108 @@
+//////////////////////////////////////////////////////////////////////////////////
+
+module gpmc_sync
+  (// GPMC signals
+   input arst,
+   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+   input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
+   
+   // GPIOs for FIFO signalling
+   output rx_have_data, output tx_have_space, output bus_error, input bus_reset,
+   
+   // Wishbone signals
+   input wb_clk, input wb_rst,
+   output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
+   output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
+
+   // FIFO interface
+   input fifo_clk, input fifo_rst,
+   output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
+   input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
+
+   output [31:0] debug
+   );
+
+   wire 	EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
+   wire [15:0] 	EM_D_fifo;
+   wire [15:0] 	EM_D_wb;
+
+   assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb;
+
+   wire 	bus_error_tx, bus_error_rx;
+   assign bus_error = bus_error_tx | bus_error_rx;
+   
+   // CS4 is RAM_2PORT for DATA PATH (high-speed data)
+   //    Writes go into one RAM, reads come from the other
+   // CS6 is for CONTROL PATH (wishbone)
+
+   // ////////////////////////////////////////////
+   // TX Data Path
+
+   wire [17:0] 	tx18_data, tx18b_data;
+   wire 	tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
+   wire [15:0] 	tx_fifo_space, tx_frame_len;
+   
+   assign tx_frame_len = 10;
+   
+   gpmc_to_fifo_sync gpmc_to_fifo_sync
+     (.arst(arst),
+      .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
+      .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
+      .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space),
+      .bus_error(bus_error_tx) );
+   
+   fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) tx_fifo
+     (.wclk(EM_CLK), .datain(tx18_data), 
+      .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space),
+      .rclk(fifo_clk), .dataout(tx18b_data), 
+      .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst));
+
+   fifo19_to_fifo36 #(.LE(1)) f19_to_f36   // Little endian because ARM is LE
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
+      .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i));
+   
+   // ////////////////////////////////////////////
+   // RX Data Path
+
+   wire [17:0] 	rx18_data, rx18b_data;
+   wire 	rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
+   wire [15:0] 	rx_fifo_space, rx_frame_len;
+   wire 	dummy;
+   
+   fifo36_to_fifo19 #(.LE(1)) f36_to_f19   // Little endian because ARM is LE
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o),
+      .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
+
+   fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo
+     (.wclk(fifo_clk), .datain(rx18_data), 
+      .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space),
+      .rclk(EM_CLK), .dataout(rx18b_data), 
+      .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied(), .arst(arst));
+
+   fifo_to_gpmc_sync fifo_to_gpmc_sync
+     (.arst(arst),
+      .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy),
+      .EM_CLK(EM_CLK), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE),
+      .fifo_ready(rx_have_data) );
+
+   fifo_watcher fifo_watcher
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .src_rdy(rx18_src_rdy), .dst_rdy(rx18_dst_rdy), .sof(rx18_data[16]), .eof(rx18_data[17]),
+      .have_packet(), .length(), .next() );
+   
+   // ////////////////////////////////////////////
+   // Control path on CS6
+   
+   gpmc_wb gpmc_wb
+     (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE),
+      .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
+      .wb_clk(wb_clk), .wb_rst(wb_rst),
+      .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso),
+      .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
+      .wb_ack_i(wb_ack_i) );
+   
+      assign debug = 0;
+   
+endmodule // gpmc_sync
diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo_async.v b/fpga/usrp2/gpmc/gpmc_to_fifo_async.v
new file mode 100644
index 000000000..55c0cef50
--- /dev/null
+++ b/fpga/usrp2/gpmc/gpmc_to_fifo_async.v
@@ -0,0 +1,68 @@
+
+module gpmc_to_fifo_async
+  (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE,
+
+   input fifo_clk, input fifo_rst, input clear,
+   output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i,
+
+   input [15:0] frame_len, input [15:0] fifo_space, output reg fifo_ready,
+   output reg bus_error );
+
+   reg [15:0] counter;
+   // Synchronize the async control signals
+   reg [1:0] 	cs_del, we_del;
+   always @(posedge fifo_clk)
+     if(fifo_rst)
+       begin
+	  cs_del <= 2'b11;
+	  we_del <= 2'b11;
+       end
+     else
+       begin
+	  cs_del <= { cs_del[0], EM_NCS };
+	  we_del <= { we_del[0], EM_NWE };
+       end
+
+   wire do_write = (~cs_del[0] & (we_del == 2'b10));
+   wire first_write = (counter == 0);
+   wire last_write = ((counter+1) == frame_len);
+
+   always @(posedge fifo_clk)
+     if(do_write)
+       begin
+	  data_o[15:0] <= EM_D;
+	  data_o[16] <= first_write;
+	  data_o[17] <= last_write;
+	  //  no byte writes data_o[18] <= |EM_NBE;  // mark half full if either is not enabled  FIXME
+       end
+
+   always @(posedge fifo_clk)
+     if(fifo_rst | clear)
+       src_rdy_o <= 0;
+     else if(do_write)
+       src_rdy_o <= 1;
+     else
+       src_rdy_o <= 0;    // Assume it was taken
+
+   always @(posedge fifo_clk)
+     if(fifo_rst | clear)
+       counter <= 0;
+     else if(do_write)
+       if(last_write)
+	 counter <= 0;
+       else
+	 counter <= counter + 1;
+
+   always @(posedge fifo_clk)
+     if(fifo_rst | clear)
+       fifo_ready <= 0;
+     else
+       fifo_ready <= /* first_write & */ (fifo_space > 16'd1023);
+
+   always @(posedge fifo_clk)
+     if(fifo_rst | clear)
+       bus_error <= 0;
+     else if(src_rdy_o & ~dst_rdy_i)
+       bus_error <= 1;
+   
+endmodule // gpmc_to_fifo_async
diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v b/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v
new file mode 100644
index 000000000..688de0e17
--- /dev/null
+++ b/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v
@@ -0,0 +1,57 @@
+
+// Assumes a GPMC cycle with GPMC clock, as in the timing diagrams
+//   If a packet bigger or smaller than we are told is sent, behavior is undefined.
+//   If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
+//   If there is a bus error, we should be reset
+
+module gpmc_to_fifo_sync
+  (input arst,
+   input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE,
+   input EM_NCS, input EM_NWE,
+   output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i,
+   input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready, 
+   output reg bus_error);
+   
+   reg [10:0] 	counter;
+   wire 	first_write = (counter == 0);
+   wire 	last_write = ((counter+1) == frame_len);
+   wire 	do_write = ~EM_NCS & ~EM_NWE;
+   
+   always @(posedge EM_CLK or posedge arst)
+     if(arst)
+       data_o <= 0;
+     else if(do_write)
+       begin
+	  data_o[15:0] <= EM_D;
+	  data_o[16] <= first_write;
+	  data_o[17] <= last_write;
+	  //  no byte writes data_o[18] <= |EM_NBE;  // mark half full if either is not enabled  FIXME
+       end
+
+   always @(posedge EM_CLK or posedge arst)
+     if(arst)
+       src_rdy_o <= 0;
+     else if(do_write & ~bus_error)  // Don't put junk in if there is a bus error
+       src_rdy_o <= 1;
+     else
+       src_rdy_o <= 0;    // Assume it was taken, ignore dst_rdy_i
+
+   always @(posedge EM_CLK or posedge arst)
+     if(arst)
+       counter <= 0;
+     else if(do_write)
+       if(last_write)
+	 counter <= 0;
+       else
+	 counter <= counter + 1;
+
+   assign fifo_ready = first_write & (fifo_space > frame_len);
+   
+   always @(posedge EM_CLK or posedge arst)
+     if(arst)
+       bus_error <= 0;
+     else if(src_rdy_o & ~dst_rdy_i)
+       bus_error <= 1;
+   // must be reset to make the error go away
+
+endmodule // gpmc_to_fifo_sync
diff --git a/fpga/usrp2/gpmc/gpmc_wb.v b/fpga/usrp2/gpmc/gpmc_wb.v
new file mode 100644
index 000000000..db6fbc6e9
--- /dev/null
+++ b/fpga/usrp2/gpmc/gpmc_wb.v
@@ -0,0 +1,57 @@
+
+
+module gpmc_wb
+  (input EM_CLK, input [15:0] EM_D_in, output [15:0] EM_D_out, input [10:1] EM_A, input [1:0] EM_NBE,
+   input EM_NCS, input EM_NWE, input EM_NOE,
+
+   input wb_clk, input wb_rst,
+   output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
+   output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i);
+   
+   // ////////////////////////////////////////////
+   // Control Path, Wishbone bus bridge (wb master)
+   reg [1:0] 	cs_del, we_del, oe_del;
+
+   // Synchronize the async control signals
+   always @(posedge wb_clk)
+     begin
+	cs_del <= { cs_del[0], EM_NCS };
+	we_del <= { we_del[0], EM_NWE };
+	oe_del <= { oe_del[0], EM_NOE };
+     end
+
+   always @(posedge wb_clk)
+     if(cs_del == 2'b10)  // Falling Edge
+       wb_adr_o <= { EM_A, 1'b0 };
+
+   always @(posedge wb_clk)
+     if(we_del == 2'b10)  // Falling Edge
+       begin
+	  wb_dat_mosi <= EM_D_in;
+	  wb_sel_o <= ~EM_NBE;
+       end
+
+   reg [15:0] EM_D_hold;
+   
+   always @(posedge wb_clk)
+     if(wb_ack_i)
+       EM_D_hold <= wb_dat_miso;
+
+   assign EM_D_out = wb_ack_i ? wb_dat_miso : EM_D_hold;
+   
+   assign wb_cyc_o = wb_stb_o;
+
+   always @(posedge wb_clk)
+     if(~cs_del[0] & (we_del == 2'b10) )
+       wb_we_o <= 1;
+     else if(wb_ack_i)  // Turn off we when done.  Could also use we_del[0], others...
+       wb_we_o <= 0;
+
+   // FIXME should this look at cs_del[1]?
+   always @(posedge wb_clk)
+     if(~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10)))
+       wb_stb_o <= 1;
+     else if(wb_ack_i)
+       wb_stb_o <= 0;
+   
+endmodule // gpmc_wb
diff --git a/fpga/usrp2/gpmc/make_timing_diag b/fpga/usrp2/gpmc/make_timing_diag
new file mode 100755
index 000000000..03166ad35
--- /dev/null
+++ b/fpga/usrp2/gpmc/make_timing_diag
@@ -0,0 +1,6 @@
+#!/bin/sh
+drawtiming -o single_data_write.gif single_data_write.txt
+drawtiming -o single_data_read.gif single_data_read.txt
+drawtiming -o burst_data_write.gif burst_data_write.txt
+#drawtiming -o burst_data_read.gif burst_data_read.txt
+
diff --git a/fpga/usrp2/gpmc/ram_to_fifo.v b/fpga/usrp2/gpmc/ram_to_fifo.v
new file mode 100644
index 000000000..8549dcc35
--- /dev/null
+++ b/fpga/usrp2/gpmc/ram_to_fifo.v
@@ -0,0 +1,46 @@
+
+
+module ram_to_fifo
+  (input clk, input reset,
+   input [10:0] read_length,  // From the dbsm (?)
+   output read_en, output reg [8:0] read_addr, input [31:0] read_data, input read_ready, output read_done,
+   output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+   // read_length/2 = number of 32 bit lines, numbered 0 through read_length/2-1
+   wire [8:0] 	 last_line = (read_length[10:1]-1); 
+
+   reg 		 read_phase, sop;
+
+   assign read_en = (read_phase == 0) | dst_rdy_i;
+   assign src_rdy_o = (read_phase == 1);
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  read_addr <= 0;
+	  read_phase <= 0;
+	  sop <= 1;
+       end
+     else
+       if(read_phase == 0)
+	 begin
+	    read_addr <= read_ready;
+	    read_phase <= read_ready;
+	 end
+       else if(dst_rdy_i)
+	 begin
+	    sop <= 0;
+	    if(read_addr == last_line)
+	      begin
+		 read_addr <= 0;
+		 read_phase <= 0;
+	      end
+	    else
+	      read_addr <= read_addr + 1;
+	 end
+   
+   assign read_done = (read_phase == 1) & (read_addr == last_line) & dst_rdy_i;
+   wire eop = (read_addr == last_line);
+   assign data_o = { 2'b00, eop, sop, read_data };
+   
+endmodule // ram_to_fifo
diff --git a/fpga/usrp2/gpmc/single_data_read.txt b/fpga/usrp2/gpmc/single_data_read.txt
new file mode 100644
index 000000000..1dc0e3a78
--- /dev/null
+++ b/fpga/usrp2/gpmc/single_data_read.txt
@@ -0,0 +1,12 @@
+# OMAP writes to FPGA
+# initialize the signals
+CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z.
+CLK=1.
+CLK=0,nOE=0,nCS=0,DATA=RD_DATA.
+CLK=1.
+CLK=0.
+CLK=1.
+CLK=0,nOE=1,nCS=1,DATA=Z.
+CLK=1.
+
+
diff --git a/fpga/usrp2/gpmc/single_data_write.txt b/fpga/usrp2/gpmc/single_data_write.txt
new file mode 100644
index 000000000..287e3e2c1
--- /dev/null
+++ b/fpga/usrp2/gpmc/single_data_write.txt
@@ -0,0 +1,10 @@
+# OMAP writes to FPGA
+# initialize the signals
+CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z.
+CLK=1.
+CLK=0,nWE=0,nCS=0,DATA=WR_DATA.
+CLK=1.
+CLK=0,nWE=1,nCS=1,DATA=Z.
+CLK=1.
+
+
diff --git a/fpga/usrp2/models/gpmc_model_async.v b/fpga/usrp2/models/gpmc_model_async.v
new file mode 100644
index 000000000..beeaee028
--- /dev/null
+++ b/fpga/usrp2/models/gpmc_model_async.v
@@ -0,0 +1,130 @@
+`timescale 1ps/1ps
+
+module gpmc_model_async
+  (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
+   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
+   output reg EM_NWE, output reg EM_NOE );
+
+   assign EM_CLK = 0;
+   reg [15:0] EM_D_int;
+   assign EM_D = EM_D_int;
+   
+   initial
+     begin
+	EM_A <= 10'bz;
+	EM_NBE <= 2'b11;
+	EM_NWE <= 1;
+	EM_NOE <= 1;
+	EM_NCS4 <= 1;
+	EM_NCS6 <= 1;
+	EM_D_int <= 16'bz;
+ 	EM_WAIT0 <= 0;  // FIXME this is actually an input
+     end
+   
+   task GPMC_Write;
+      input ctrl;
+      input [10:0] addr;
+      input [15:0] data;
+      begin
+	 #23000;
+	 EM_A <= addr[10:1];
+	 EM_D_int <= data;
+	 #20100;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 #14000;
+	 EM_NWE <= 0;
+	 #77500;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 //#1.5;
+	 EM_NWE <= 1;
+	 #60000;
+	 EM_A <= 10'bz;
+	 EM_D_int <= 16'bz;
+      end
+   endtask // GPMC_Write
+
+   task GPMC_Read;
+      input ctrl;
+      input [10:0] addr;
+      begin
+	 #13000;
+	 EM_A <= addr[10:1];
+	 #3000;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 #14000;
+	 EM_NOE <= 0;
+	 #77500;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 //#1.5;
+	 $display("Data Read from GPMC: %X",EM_D);
+	 EM_NOE <= 1;
+	 #254000;
+	 EM_A <= 10'bz;
+      end
+   endtask // GPMC_Read
+   
+   initial
+     begin
+	#1000000;
+	GPMC_Write(1,36,16'hF00D);
+	#1000000;
+	GPMC_Read(1,36);
+	#1000000;
+	GPMC_Write(0,0,16'h1234);
+	GPMC_Write(0,0,16'h5678);
+	GPMC_Write(0,0,16'h9abc);
+	GPMC_Write(0,0,16'hF00D);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	#1000000;
+	GPMC_Write(0,0,16'h1234);
+	GPMC_Write(0,0,16'h5678);
+	GPMC_Write(0,0,16'h9abc);
+	GPMC_Write(0,0,16'hF00D);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'h9876);
+	#1000000;
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	#1000000;
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	#1000000;
+	GPMC_Read(0,0);
+	#100000000;
+	$finish;
+     end
+   
+endmodule // gpmc_model_async
diff --git a/fpga/usrp2/models/gpmc_model_sync.v b/fpga/usrp2/models/gpmc_model_sync.v
new file mode 100644
index 000000000..641720c15
--- /dev/null
+++ b/fpga/usrp2/models/gpmc_model_sync.v
@@ -0,0 +1,97 @@
+
+
+module gpmc_model_sync
+  (output reg EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
+   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
+   output reg EM_NWE, output reg EM_NOE );
+
+   reg [15:0] EM_D_int;
+   assign EM_D = EM_D_int;
+
+   initial
+     begin
+	EM_CLK <= 0;
+	EM_A <= 10'bz;
+	EM_NBE <= 2'b11;
+	EM_NWE <= 1;
+	EM_NOE <= 1;
+	EM_NCS4 <= 1;
+	EM_NCS6 <= 1;
+	EM_D_int <= 16'bz;
+ 	EM_WAIT0 <= 0;  // FIXME this is actually an input
+     end
+   
+   task GPMC_Write;
+      input ctrl;
+      input [10:0] addr;
+      input [15:0] data;
+      begin
+	 EM_CLK <= 1;
+	 #10;
+	 EM_CLK <= 0;
+	 EM_NWE <= 0;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 EM_A <= addr[10:1];
+	 EM_D_int <= data;
+	 #10;
+	 EM_CLK <= 1;
+	 #10;
+	 EM_CLK <= 0;
+	 EM_NWE <= 1;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 EM_A <= 10'bz;
+	 EM_D_int <= 16'bz;
+	 #100;
+      end
+   endtask // GPMC_Write
+
+   task GPMC_Read;
+      input ctrl;
+      input [10:0] addr;
+      begin
+	 #1.3;
+	 EM_A <= addr[10:1];
+	 #3;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 #14;
+	 EM_NOE <= 0;
+	 #77.5;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 //#1.5;
+	 $display("Data Read from GPMC: %X",EM_D);
+	 EM_NOE <= 1;
+	 #254;
+	 EM_A <= 10'bz;
+      end
+   endtask // GPMC_Read
+   
+   initial
+     begin
+	#1000;
+	GPMC_Write(1,36,16'hF00D);
+	#1000;
+	GPMC_Read(1,36);
+	#1000;
+	GPMC_Write(0,36,16'h1234);
+	GPMC_Write(0,38,16'h5678);
+	GPMC_Write(0,40,16'h9abc);
+	GPMC_Write(0,11'h2F4,16'hF00D);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	#100000;
+	$finish;
+     end
+   
+endmodule // gpmc_model
diff --git a/fpga/usrp2/opencores/Makefile.srcs b/fpga/usrp2/opencores/Makefile.srcs
index 30360a17d..284578b39 100644
--- a/fpga/usrp2/opencores/Makefile.srcs
+++ b/fpga/usrp2/opencores/Makefile.srcs
@@ -24,5 +24,5 @@ spi/rtl/verilog/spi_clgen.v \
 spi/rtl/verilog/spi_defines.v \
 spi/rtl/verilog/spi_shift.v \
 spi/rtl/verilog/spi_top.v \
-spi/rtl/verilog/timescale.v \
+spi/rtl/verilog/spi_top16.v \
 ))
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
index 38ca3a023..6c066d5d9 100644
--- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
@@ -11,7 +11,7 @@ module aeMB_core_BE
     (input sys_clk_i,
      input sys_rst_i,
      // Instruction port
-     output [14:0] if_adr,
+     output [ISIZ-1:0] if_adr,
      input [31:0] if_dat,
      // Data port
      output dwb_we_o,
@@ -34,7 +34,7 @@ module aeMB_core_BE
    
    assign dwb_cyc_o = dwb_stb_o;
    assign iwb_ack_i = 1'b1;
-   assign if_adr = iwb_adr_o[14:0];
+   assign if_adr = iwb_adr_o[ISIZ-1:0];
    assign iwb_dat_i = if_dat;
 
    // Note some "wishbone" instruction fetch signals pruned on external interface
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
index 7bc4f6e5e..2d9c34f40 100644
--- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
@@ -39,12 +39,9 @@
 //////////////////////////////////////////////////////////////////////
 
 `include "spi_defines.v"
-`include "timescale.v"
 
 module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); 
 
-  parameter Tp = 1;
-  
   input                            clk_in;   // input clock (system clock)
   input                            rst;      // reset
   input                            enable;   // clock enable
@@ -68,40 +65,40 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
   assign cnt_one  = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
   
   // Counter counts half period
-  always @(posedge clk_in or posedge rst)
+  always @(posedge clk_in)
   begin
     if(rst)
-      cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}};
+      cnt <= {`SPI_DIVIDER_LEN{1'b1}};
     else
       begin
         if(!enable || cnt_zero)
-          cnt <= #Tp divider;
+          cnt <= divider;
         else
-          cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
+          cnt <= cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
       end
   end
   
   // clk_out is asserted every other half period
-  always @(posedge clk_in or posedge rst)
+  always @(posedge clk_in)
   begin
     if(rst)
-      clk_out <= #Tp 1'b0;
+      clk_out <= 1'b0;
     else
-      clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
+      clk_out <= (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
   end
    
   // Pos and neg edge signals
-  always @(posedge clk_in or posedge rst)
+  always @(posedge clk_in)
   begin
     if(rst)
       begin
-        pos_edge  <= #Tp 1'b0;
-        neg_edge  <= #Tp 1'b0;
+        pos_edge  <= 1'b0;
+        neg_edge  <= 1'b0;
       end
     else
       begin
-        pos_edge  <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
-        neg_edge  <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
+        pos_edge  <= (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
+        neg_edge  <= (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
       end
   end
 endmodule
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v
index a6925918e..3e4dd0e3c 100644
--- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v
@@ -43,8 +43,8 @@
 // low frequency of system clock this can be reduced.
 // Use SPI_DIVIDER_LEN for fine tuning theexact number.
 //
-//`define SPI_DIVIDER_LEN_8
-`define SPI_DIVIDER_LEN_16
+`define SPI_DIVIDER_LEN_8
+//`define SPI_DIVIDER_LEN_16
 //`define SPI_DIVIDER_LEN_24
 //`define SPI_DIVIDER_LEN_32
 
@@ -102,8 +102,8 @@
 // Number of device select signals. Use SPI_SS_NB for fine tuning the 
 // exact number.
 //
-`define SPI_SS_NB_8
-//`define SPI_SS_NB_16
+//`define SPI_SS_NB_8
+`define SPI_SS_NB_16
 //`define SPI_SS_NB_24
 //`define SPI_SS_NB_32
 
@@ -137,7 +137,7 @@
 `define SPI_TX_2                2
 `define SPI_TX_3                3
 `define SPI_CTRL                4
-`define SPI_DEVIDE              5
+`define SPI_DIVIDE              5
 `define SPI_SS                  6
 
 //
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v
index b17ac8b1f..ac3bb3f48 100644
--- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v
@@ -39,15 +39,12 @@
 //////////////////////////////////////////////////////////////////////
 
 `include "spi_defines.v"
-`include "timescale.v"
 
 module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
                   pos_edge, neg_edge, rx_negedge, tx_negedge,
                   tip, last, 
                   p_in, p_out, s_clk, s_in, s_out);
 
-  parameter Tp = 1;
-  
   input                          clk;          // system clock
   input                          rst;          // reset
   input                    [3:0] latch;        // latch signal for storing the data in shift register
@@ -89,149 +86,149 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
   assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
   
   // Character bit counter
-  always @(posedge clk or posedge rst)
+  always @(posedge clk)
   begin
     if(rst)
-      cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
+      cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}};
     else
       begin
         if(tip)
-          cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
+          cnt <= pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
         else
-          cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
+          cnt <= !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
       end
   end
   
   // Transfer in progress
-  always @(posedge clk or posedge rst)
+  always @(posedge clk)
   begin
     if(rst)
-      tip <= #Tp 1'b0;
+      tip <= 1'b0;
   else if(go && ~tip)
-    tip <= #Tp 1'b1;
+    tip <= 1'b1;
   else if(tip && last && pos_edge)
-    tip <= #Tp 1'b0;
+    tip <= 1'b0;
   end
   
   // Sending bits to the line
-  always @(posedge clk or posedge rst)
+  always @(posedge clk)
   begin
     if (rst)
-      s_out   <= #Tp 1'b0;
+      s_out   <= 1'b0;
     else
-      s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
+      s_out <= (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
   end
   
   // Receiving bits from the line
-  always @(posedge clk or posedge rst)
+  always @(posedge clk)
   begin
     if (rst)
-      data   <= #Tp {`SPI_MAX_CHAR{1'b0}};
+      data   <= {`SPI_MAX_CHAR{1'b0}};
 `ifdef SPI_MAX_CHAR_128
     else if (latch[0] && !tip)
       begin
         if (byte_sel[3])
-          data[31:24] <= #Tp p_in[31:24];
+          data[31:24] <= p_in[31:24];
         if (byte_sel[2])
-          data[23:16] <= #Tp p_in[23:16];
+          data[23:16] <= p_in[23:16];
         if (byte_sel[1])
-          data[15:8] <= #Tp p_in[15:8];
+          data[15:8] <= p_in[15:8];
         if (byte_sel[0])
-          data[7:0] <= #Tp p_in[7:0];
+          data[7:0] <= p_in[7:0];
       end
     else if (latch[1] && !tip)
       begin
         if (byte_sel[3])
-          data[63:56] <= #Tp p_in[31:24];
+          data[63:56] <= p_in[31:24];
         if (byte_sel[2])
-          data[55:48] <= #Tp p_in[23:16];
+          data[55:48] <= p_in[23:16];
         if (byte_sel[1])
-          data[47:40] <= #Tp p_in[15:8];
+          data[47:40] <= p_in[15:8];
         if (byte_sel[0])
-          data[39:32] <= #Tp p_in[7:0];
+          data[39:32] <= p_in[7:0];
       end
     else if (latch[2] && !tip)
       begin
         if (byte_sel[3])
-          data[95:88] <= #Tp p_in[31:24];
+          data[95:88] <= p_in[31:24];
         if (byte_sel[2])
-          data[87:80] <= #Tp p_in[23:16];
+          data[87:80] <= p_in[23:16];
         if (byte_sel[1])
-          data[79:72] <= #Tp p_in[15:8];
+          data[79:72] <= p_in[15:8];
         if (byte_sel[0])
-          data[71:64] <= #Tp p_in[7:0];
+          data[71:64] <= p_in[7:0];
       end
     else if (latch[3] && !tip)
       begin
         if (byte_sel[3])
-          data[127:120] <= #Tp p_in[31:24];
+          data[127:120] <= p_in[31:24];
         if (byte_sel[2])
-          data[119:112] <= #Tp p_in[23:16];
+          data[119:112] <= p_in[23:16];
         if (byte_sel[1])
-          data[111:104] <= #Tp p_in[15:8];
+          data[111:104] <= p_in[15:8];
         if (byte_sel[0])
-          data[103:96] <= #Tp p_in[7:0];
+          data[103:96] <= p_in[7:0];
       end
 `else
 `ifdef SPI_MAX_CHAR_64
     else if (latch[0] && !tip)
       begin
         if (byte_sel[3])
-          data[31:24] <= #Tp p_in[31:24];
+          data[31:24] <= p_in[31:24];
         if (byte_sel[2])
-          data[23:16] <= #Tp p_in[23:16];
+          data[23:16] <= p_in[23:16];
         if (byte_sel[1])
-          data[15:8] <= #Tp p_in[15:8];
+          data[15:8] <= p_in[15:8];
         if (byte_sel[0])
-          data[7:0] <= #Tp p_in[7:0];
+          data[7:0] <= p_in[7:0];
       end
     else if (latch[1] && !tip)
       begin
         if (byte_sel[3])
-          data[63:56] <= #Tp p_in[31:24];
+          data[63:56] <= p_in[31:24];
         if (byte_sel[2])
-          data[55:48] <= #Tp p_in[23:16];
+          data[55:48] <= p_in[23:16];
         if (byte_sel[1])
-          data[47:40] <= #Tp p_in[15:8];
+          data[47:40] <= p_in[15:8];
         if (byte_sel[0])
-          data[39:32] <= #Tp p_in[7:0];
+          data[39:32] <= p_in[7:0];
       end
 `else
     else if (latch[0] && !tip)
       begin
       `ifdef SPI_MAX_CHAR_8
         if (byte_sel[0])
-          data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0];
+          data[`SPI_MAX_CHAR-1:0] <= p_in[`SPI_MAX_CHAR-1:0];
       `endif
       `ifdef SPI_MAX_CHAR_16
         if (byte_sel[0])
-          data[7:0] <= #Tp p_in[7:0];
+          data[7:0] <= p_in[7:0];
         if (byte_sel[1])
-          data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8];
+          data[`SPI_MAX_CHAR-1:8] <= p_in[`SPI_MAX_CHAR-1:8];
       `endif
       `ifdef SPI_MAX_CHAR_24
         if (byte_sel[0])
-          data[7:0] <= #Tp p_in[7:0];
+          data[7:0] <= p_in[7:0];
         if (byte_sel[1])
-          data[15:8] <= #Tp p_in[15:8];
+          data[15:8] <= p_in[15:8];
         if (byte_sel[2])
-          data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16];
+          data[`SPI_MAX_CHAR-1:16] <= p_in[`SPI_MAX_CHAR-1:16];
       `endif
       `ifdef SPI_MAX_CHAR_32
         if (byte_sel[0])
-          data[7:0] <= #Tp p_in[7:0];
+          data[7:0] <= p_in[7:0];
         if (byte_sel[1])
-          data[15:8] <= #Tp p_in[15:8];
+          data[15:8] <= p_in[15:8];
         if (byte_sel[2])
-          data[23:16] <= #Tp p_in[23:16];
+          data[23:16] <= p_in[23:16];
         if (byte_sel[3])
-          data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24];
+          data[`SPI_MAX_CHAR-1:24] <= p_in[`SPI_MAX_CHAR-1:24];
       `endif
       end
 `endif
 `endif
     else
-      data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
+      data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
   end
   
 endmodule
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v
index 09b2e50e1..8289449a9 100644
--- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v
@@ -1,3 +1,6 @@
+
+// Modified 2010 by Matt Ettus to remove old verilog style
+
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 ////  spi_top.v                                                   ////
@@ -40,7 +43,6 @@
 
 
 `include "spi_defines.v"
-`include "timescale.v"
 
 module spi_top
 (
@@ -52,8 +54,6 @@ module spi_top
   ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
 );
 
-  parameter Tp = 1;
-
   // Wishbone signals
   input                            wb_clk_i;         // master clock input
   input                            wb_rst_i;         // synchronous active high reset
@@ -101,7 +101,7 @@ module spi_top
   wire                             last_bit;         // marks last character bit
   
   // Address decoder
-  assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DEVIDE);
+  assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DIVIDE);
   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);
   assign spi_tx_sel[0]   = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);
   assign spi_tx_sel[1]   = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1);
@@ -132,96 +132,96 @@ module spi_top
 `endif
 `endif
       `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
-      `SPI_DEVIDE:  wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
+      `SPI_DIVIDE:  wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
       `SPI_SS:      wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss};
       default:      wb_dat = 32'bx;
     endcase
   end
   
   // Wb data out
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
-      wb_dat_o <= #Tp 32'b0;
+      wb_dat_o <= 32'b0;
     else
-      wb_dat_o <= #Tp wb_dat;
+      wb_dat_o <= wb_dat;
   end
   
   // Wb acknowledge
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
-      wb_ack_o <= #Tp 1'b0;
+      wb_ack_o <= 1'b0;
     else
-      wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o;
+      wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
   end
   
   // Wb error
   assign wb_err_o = 1'b0;
   
   // Interrupt
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
-      wb_int_o <= #Tp 1'b0;
+      wb_int_o <= 1'b0;
     else if (ie && tip && last_bit && pos_edge)
-      wb_int_o <= #Tp 1'b1;
+      wb_int_o <= 1'b1;
     else if (wb_ack_o)
-      wb_int_o <= #Tp 1'b0;
+      wb_int_o <= 1'b0;
   end
   
   // Divider register
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
-        divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}};
+        divider <= {`SPI_DIVIDER_LEN{1'b0}};
     else if (spi_divider_sel && wb_we_i && !tip)
       begin
       `ifdef SPI_DIVIDER_LEN_8
         if (wb_sel_i[0])
-          divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0];
+          divider <= wb_dat_i[`SPI_DIVIDER_LEN-1:0];
       `endif
       `ifdef SPI_DIVIDER_LEN_16
         if (wb_sel_i[0])
-          divider[7:0] <= #Tp wb_dat_i[7:0];
+          divider[7:0] <= wb_dat_i[7:0];
         if (wb_sel_i[1])
-          divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8];
+          divider[`SPI_DIVIDER_LEN-1:8] <= wb_dat_i[`SPI_DIVIDER_LEN-1:8];
       `endif
       `ifdef SPI_DIVIDER_LEN_24
         if (wb_sel_i[0])
-          divider[7:0] <= #Tp wb_dat_i[7:0];
+          divider[7:0] <= wb_dat_i[7:0];
         if (wb_sel_i[1])
-          divider[15:8] <= #Tp wb_dat_i[15:8];
+          divider[15:8] <= wb_dat_i[15:8];
         if (wb_sel_i[2])
-          divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16];
+          divider[`SPI_DIVIDER_LEN-1:16] <= wb_dat_i[`SPI_DIVIDER_LEN-1:16];
       `endif
       `ifdef SPI_DIVIDER_LEN_32
         if (wb_sel_i[0])
-          divider[7:0] <= #Tp wb_dat_i[7:0];
+          divider[7:0] <= wb_dat_i[7:0];
         if (wb_sel_i[1])
-          divider[15:8] <= #Tp wb_dat_i[15:8];
+          divider[15:8] <= wb_dat_i[15:8];
         if (wb_sel_i[2])
-          divider[23:16] <= #Tp wb_dat_i[23:16];
+          divider[23:16] <= wb_dat_i[23:16];
         if (wb_sel_i[3])
-          divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24];
+          divider[`SPI_DIVIDER_LEN-1:24] <= wb_dat_i[`SPI_DIVIDER_LEN-1:24];
       `endif
       end
   end
   
   // Ctrl register
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
-      ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}};
+      ctrl <= {`SPI_CTRL_BIT_NB{1'b0}};
     else if(spi_ctrl_sel && wb_we_i && !tip)
       begin
         if (wb_sel_i[0])
-          ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]};
+          ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]};
         if (wb_sel_i[1])
-          ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
+          ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
       end
     else if(tip && last_bit && pos_edge)
-      ctrl[`SPI_CTRL_GO] <= #Tp 1'b0;
+      ctrl[`SPI_CTRL_GO] <= 1'b0;
   end
   
   assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
@@ -233,39 +233,39 @@ module spi_top
   assign ass        = ctrl[`SPI_CTRL_ASS];
   
   // Slave select register
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
-      ss <= #Tp {`SPI_SS_NB{1'b0}};
+      ss <= {`SPI_SS_NB{1'b0}};
     else if(spi_ss_sel && wb_we_i && !tip)
       begin
       `ifdef SPI_SS_NB_8
         if (wb_sel_i[0])
-          ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
+          ss <= wb_dat_i[`SPI_SS_NB-1:0];
       `endif
       `ifdef SPI_SS_NB_16
         if (wb_sel_i[0])
-          ss[7:0] <= #Tp wb_dat_i[7:0];
+          ss[7:0] <= wb_dat_i[7:0];
         if (wb_sel_i[1])
-          ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8];
+          ss[`SPI_SS_NB-1:8] <= wb_dat_i[`SPI_SS_NB-1:8];
       `endif
       `ifdef SPI_SS_NB_24
         if (wb_sel_i[0])
-          ss[7:0] <= #Tp wb_dat_i[7:0];
+          ss[7:0] <= wb_dat_i[7:0];
         if (wb_sel_i[1])
-          ss[15:8] <= #Tp wb_dat_i[15:8];
+          ss[15:8] <= wb_dat_i[15:8];
         if (wb_sel_i[2])
-          ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16];
+          ss[`SPI_SS_NB-1:16] <= wb_dat_i[`SPI_SS_NB-1:16];
       `endif
       `ifdef SPI_SS_NB_32
         if (wb_sel_i[0])
-          ss[7:0] <= #Tp wb_dat_i[7:0];
+          ss[7:0] <= wb_dat_i[7:0];
         if (wb_sel_i[1])
-          ss[15:8] <= #Tp wb_dat_i[15:8];
+          ss[15:8] <= wb_dat_i[15:8];
         if (wb_sel_i[2])
-          ss[23:16] <= #Tp wb_dat_i[23:16];
+          ss[23:16] <= wb_dat_i[23:16];
         if (wb_sel_i[3])
-          ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24];
+          ss[`SPI_SS_NB-1:24] <= wb_dat_i[`SPI_SS_NB-1:24];
       `endif
       end
   end
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v
new file mode 100644
index 000000000..ee808a8ab
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v
@@ -0,0 +1,182 @@
+
+// Modified 2010 by Matt Ettus to remove old verilog style and
+// allow 16-bit operation
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_top.v                                                   ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+
+`include "spi_defines.v"
+
+module spi_top16
+  (input wb_clk_i, input wb_rst_i, 
+   input [4:0] wb_adr_i, 
+   input [15:0] wb_dat_i, 
+   output reg [15:0] wb_dat_o, 
+   input [1:0] wb_sel_i,
+   input wb_we_i, input wb_stb_i, input wb_cyc_i, 
+   output reg wb_ack_o, output wb_err_o, output reg wb_int_o,
+   
+   // SPI signals
+   output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i);
+   
+   // Internal signals
+   reg [15:0] divider;          // Divider register
+   reg [`SPI_CTRL_BIT_NB-1:0] ctrl;             // Control and status register
+   reg [15:0] 		      ss;               // Slave select register
+   reg [31:0] 		      wb_dat;           // wb data out
+   wire [31:0] 		      rx;               // Rx register
+   wire 		      rx_negedge;       // miso is sampled on negative edge
+   wire 		      tx_negedge;       // mosi is driven on negative edge
+   wire [`SPI_CHAR_LEN_BITS-1:0] char_len;         // char len
+   wire 			 go;               // go
+   wire 			 lsb;              // lsb first on line
+   wire 			 ie;               // interrupt enable
+   wire 			 ass;              // automatic slave select
+   wire 			 spi_divider_sel;  // divider register select
+   wire 			 spi_ctrl_sel;     // ctrl register select
+   wire [3:0] 			 spi_tx_sel;       // tx_l register select
+   wire 			 spi_ss_sel;       // ss register select
+   wire 			 tip;              // transfer in progress
+   wire 			 pos_edge;         // recognize posedge of sclk
+   wire 			 neg_edge;         // recognize negedge of sclk
+   wire 			 last_bit;         // marks last character bit
+   
+   // Address decoder
+   assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_DIVIDE);
+   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_CTRL);
+   assign spi_tx_sel[0]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_0);
+   assign spi_tx_sel[1]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_1);
+   assign spi_tx_sel[2]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_2);
+   assign spi_tx_sel[3]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_3);
+   assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS);
+   
+   always @(wb_adr_i or rx or ctrl or divider or ss)
+     case (wb_adr_i[4:2])   
+       `SPI_RX_0:    wb_dat = rx[31:0];
+       `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
+       `SPI_DIVIDE:  wb_dat = {16'b0, divider};
+       `SPI_SS:      wb_dat = {16'b0, ss};
+       default : wb_dat = 32'd0;
+     endcase // case (wb_adr_i[4:2])
+   
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       wb_dat_o <= 32'b0;
+     else
+       wb_dat_o <= wb_adr_i[1] ? wb_dat[31:16] : wb_dat[15:0];
+   
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       wb_ack_o <= 1'b0;
+     else
+       wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
+   
+   assign wb_err_o = 1'b0;
+   
+   // Interrupt
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       wb_int_o <= 1'b0;
+     else if (ie && tip && last_bit && pos_edge)
+       wb_int_o <= 1'b1;
+     else if (wb_ack_o)
+       wb_int_o <= 1'b0;
+   
+   // Divider register
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       divider <= 16'b0;
+     else if (spi_divider_sel && wb_we_i && !tip && ~wb_adr_i[1])
+       divider <= wb_dat_i;
+   
+   // Ctrl register
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       ctrl <= {`SPI_CTRL_BIT_NB{1'b0}};
+     else if(spi_ctrl_sel && wb_we_i && !tip && ~wb_adr_i[1])
+       begin
+          if (wb_sel_i[0])
+            ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]};
+          if (wb_sel_i[1])
+            ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
+       end
+     else if(tip && last_bit && pos_edge)
+       ctrl[`SPI_CTRL_GO] <= 1'b0;
+   
+   assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
+   assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
+   assign go         = ctrl[`SPI_CTRL_GO];
+   assign char_len   = ctrl[`SPI_CTRL_CHAR_LEN];
+   assign lsb        = ctrl[`SPI_CTRL_LSB];
+   assign ie         = ctrl[`SPI_CTRL_IE];
+   assign ass        = ctrl[`SPI_CTRL_ASS];
+   
+   // Slave select register
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       ss <= 16'b0;
+     else if(spi_ss_sel && wb_we_i && !tip & ~wb_adr_i[1])
+       begin
+          if (wb_sel_i[0])
+            ss[7:0] <= wb_dat_i[7:0];
+          if (wb_sel_i[1])
+            ss[15:8] <= wb_dat_i[15:8];
+       end
+   
+   assign ss_pad_o = ~((ss & {16{tip & ass}}) | (ss & {16{!ass}}));
+   
+   spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
+                    .divider(divider[`SPI_DIVIDER_LEN-1:0]), .clk_out(sclk_pad_o), .pos_edge(pos_edge), 
+                    .neg_edge(neg_edge));
+
+   wire [3:0] new_sels = { (wb_adr_i[1] & wb_sel_i[1]), (wb_adr_i[1] & wb_sel_i[0]), 
+			   (~wb_adr_i[1] & wb_sel_i[1]), (~wb_adr_i[1] & wb_sel_i[0]) };
+   
+   
+   spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
+                    .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(new_sels), .lsb(lsb), 
+                    .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), 
+                    .rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
+                    .tip(tip), .last(last_bit), 
+                    .p_in({wb_dat_i,wb_dat_i}), .p_out(rx), 
+                    .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
+
+endmodule // spi_top16
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v b/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v
deleted file mode 100644
index 60d4ecbd1..000000000
--- a/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v
+++ /dev/null
@@ -1,2 +0,0 @@
-`timescale 1ns / 10ps
-
diff --git a/fpga/usrp2/timing/time_compare.v b/fpga/usrp2/timing/time_compare.v
index a21c9f8e0..cb2b6d860 100644
--- a/fpga/usrp2/timing/time_compare.v
+++ b/fpga/usrp2/timing/time_compare.v
@@ -14,10 +14,34 @@ module time_compare
 
    wire    tick_match  = (time_now[31:0] == trigger_time[31:0]);
    wire    tick_late   = (time_now[31:0] > trigger_time[31:0]);
-   
+/*   
    assign now 	       = sec_match & tick_match;
    assign late 	       = sec_late | (sec_match & tick_late);
    assign early        = ~now & ~late;
+*/
+
+   /*
+   assign now = (time_now == trigger_time);
+   assign late = (time_now > trigger_time);
+   assign early = (time_now < trigger_time);
+   */
+
+   // Compare fewer bits instead of 64 to speed up logic
+   // Unused bits are not significant
+   //     Top bit of seconds would put us in year 2038, long after
+   //        the warranty has run out :)
+   //     Top 5 bits of ticks are always zero for clocks less than 134MHz
+   //     "late" can drop bottom few bits of ticks, and just delay signaling
+   //        of late.  
+   //     "now" cannot drop those bits, it needs to be exact.
+   
+   wire [57:0] short_now = {time_now[62:32],time_now[26:0]};
+   wire [57:0] short_trig = {trigger_time[62:32],trigger_time[26:0]};
+
+   assign now = (short_now == short_trig);
+   assign late = (short_now[57:5] > short_trig[57:5]);
+   assign early = (short_now < short_trig);
+   
    assign too_early    = (trigger_time[63:32] > (time_now[63:32] + 4));  // Don't wait too long
    
 endmodule // time_compare
diff --git a/fpga/usrp2/top/.gitignore b/fpga/usrp2/top/.gitignore
index bf1b77066..0d90f1698 100644
--- a/fpga/usrp2/top/.gitignore
+++ b/fpga/usrp2/top/.gitignore
@@ -1 +1,2 @@
 /*.sav
+build*
diff --git a/fpga/usrp2/top/Makefile.common b/fpga/usrp2/top/Makefile.common
index 9a180d10e..6f855a070 100644
--- a/fpga/usrp2/top/Makefile.common
+++ b/fpga/usrp2/top/Makefile.common
@@ -13,8 +13,10 @@ else
 endif
 BASE_DIR = $(abspath ..)
 ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl
+SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py
 ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT)
 BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin
+BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit
 MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs
 
 ##################################################
@@ -25,12 +27,13 @@ all: bin
 proj: $(ISE_FILE)
 
 check: $(ISE_FILE)
+	$(SANITY_CHECKER) $(TOP_MODULE).v $(TOP_MODULE).ucf
 	$(ISE_HELPER) "Check Syntax"
 
 synth: $(ISE_FILE)
 	$(ISE_HELPER) "Synthesize - XST"
 
-bin: $(BIN_FILE)
+bin: check $(BIN_FILE)
 	$(ISE_HELPER) "Generate Programming File"
 
 mcs: $(MCS_FILE)
@@ -54,6 +57,6 @@ $(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST)
 	touch $@
 
 $(MCS_FILE): $(BIN_FILE)
-	promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIN_FILE)
+	promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIT_FILE)
 
 .EXPORT_ALL_VARIABLES:
diff --git a/fpga/usrp2/top/python/check_inout.py b/fpga/usrp2/top/python/check_inout.py
new file mode 100755
index 000000000..ff371d378
--- /dev/null
+++ b/fpga/usrp2/top/python/check_inout.py
@@ -0,0 +1,62 @@
+#!/usr/bin/env python
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+# Description:
+# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf.
+# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes
+
+import sys
+import re
+
+if __name__=='__main__':
+  if len(sys.argv) == 2:
+    print "Usage: %s <top level Verilog file> <pin definition UCF>"
+    sys.exit(-1)
+
+  verilog_filename = sys.argv[1]
+  ucf_filename = sys.argv[2]
+
+  verilog_file = open(verilog_filename, 'r')
+  ucf_file = open(ucf_filename, 'r')
+
+  verilog_iolist = list()
+  ucf_iolist = list()
+
+  #read in all input, inout, and output declarations and compile a list
+  for line in verilog_file:
+    for match in re.findall(r"(?:input|inout|output) (?:reg )*(?:\[.*\] )*(\w+)", line.split("//")[0]):
+      verilog_iolist.append(match)
+
+  for line in ucf_file:
+      m = re.search(r"""NET "(\w+).*" """, line.split("#")[0])
+      if m is not None:
+        ucf_iolist.append(m.group(1))
+
+  #now find corresponding matches and error when you don't find one
+  #we search for .v defs without matching .ucf defs since the reverse isn't necessarily a problem
+  err = False
+
+  for item in verilog_iolist:
+    if item not in ucf_iolist:
+      print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item
+      err = True
+
+  if err:
+    sys.exit(-1)
+
+  print "No errors found."
+  sys.exit(0)
diff --git a/fpga/usrp2/top/safe_u2plus/.gitignore b/fpga/usrp2/top/safe_u2plus/.gitignore
new file mode 100644
index 000000000..a96f0be92
--- /dev/null
+++ b/fpga/usrp2/top/safe_u2plus/.gitignore
@@ -0,0 +1,2 @@
+build*
+*impact*
diff --git a/fpga/usrp2/top/safe_u2plus/Makefile b/fpga/usrp2/top/safe_u2plus/Makefile
new file mode 100644
index 000000000..62a02ff40
--- /dev/null
+++ b/fpga/usrp2/top/safe_u2plus/Makefile
@@ -0,0 +1,246 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := safe_u2plus
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd3400a \
+package fg676 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+control_lib/reset_sync.v \
+simple_gemac/simple_gemac_wrapper.v \
+simple_gemac/simple_gemac.v \
+simple_gemac/simple_gemac_wb.v \
+simple_gemac/simple_gemac_tx.v \
+simple_gemac/simple_gemac_rx.v \
+simple_gemac/crc.v \
+simple_gemac/delay_line.v \
+simple_gemac/flow_ctrl_tx.v \
+simple_gemac/flow_ctrl_rx.v \
+simple_gemac/address_filter.v \
+simple_gemac/ll8_to_txmac.v \
+simple_gemac/rxmac_to_ll8.v \
+simple_gemac/miim/eth_miim.v \
+simple_gemac/miim/eth_clockgen.v \
+simple_gemac/miim/eth_outputcontrol.v \
+simple_gemac/miim/eth_shiftreg.v \
+control_lib/newfifo/buffer_int.v \
+control_lib/newfifo/buffer_pool.v \
+control_lib/newfifo/fifo_2clock.v \
+control_lib/newfifo/fifo_2clock_cascade.v \
+control_lib/newfifo/ll8_shortfifo.v \
+control_lib/newfifo/ll8_to_fifo36.v \
+control_lib/newfifo/fifo_short.v \
+control_lib/newfifo/fifo_long.v \
+control_lib/newfifo/fifo_cascade.v \
+control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/longfifo.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+coregen/fifo_xlnx_64x36_2clk.v \
+coregen/fifo_xlnx_64x36_2clk.xco \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u2plus/capture_ddrlvds.v \
+top/safe_u2plus/u2plus.ucf \
+top/safe_u2plus/safe_u2plus.v 
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High 
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+	@echo make proj, check, synth, bin, or clean
+
+proj:
+	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
+
+check:
+	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
+
+synth:
+	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
+
+bin:
+	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+
diff --git a/fpga/usrp2/top/safe_u2plus/safe_u2plus.v b/fpga/usrp2/top/safe_u2plus/safe_u2plus.v
new file mode 100644
index 000000000..dca9688c5
--- /dev/null
+++ b/fpga/usrp2/top/safe_u2plus/safe_u2plus.v
@@ -0,0 +1,23 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module safe_u2plus
+  (
+   input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
+   output [5:1] leds,  // LED4 is shared w/INIT_B
+   output ETH_LED
+   );
+
+   wire   clk_fpga;
+   
+   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+   defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+   reg [31:0] 	ctr;
+
+   always @(posedge clk_fpga)
+     ctr <= ctr + 1;
+
+   assign {leds,ETH_LED} = ~ctr[29:24];
+   
+endmodule // safe_u2plus
diff --git a/fpga/usrp2/top/safe_u2plus/u2plus.ucf b/fpga/usrp2/top/safe_u2plus/u2plus.ucf
new file mode 100755
index 000000000..0a9460d86
--- /dev/null
+++ b/fpga/usrp2/top/safe_u2plus/u2plus.ucf
@@ -0,0 +1,401 @@
+## Main 100 MHz Clock
+NET "CLK_FPGA_P"  LOC = "AA13"  ;
+NET "CLK_FPGA_N"  LOC = "Y13"  ;
+
+## ADC
+#NET "ADC_clkout_p"  LOC = "P1"  ;
+#NET "ADC_clkout_n"  LOC = "P2"  ;
+#NET "ADCA_12_p"  LOC = "Y1"  ;
+#NET "ADCA_12_n"  LOC = "Y2"  ;
+#NET "ADCA_10_p"  LOC = "W3"  ;
+#NET "ADCA_10_n"  LOC = "W4"  ;
+#NET "ADCA_8_p"  LOC = "T7"  ;
+#NET "ADCA_8_n"  LOC = "U6"  ;
+#NET "ADCA_6_p"  LOC = "U5"  ;
+#NET "ADCA_6_n"  LOC = "V5"  ;
+#NET "ADCA_4_p"  LOC = "T10"  ;
+#NET "ADCA_4_n"  LOC = "T9"  ;
+#NET "ADCA_2_p"  LOC = "V1"  ;
+#NET "ADCA_2_n"  LOC = "V2"  ;
+#NET "ADCA_0_p"  LOC = "R8"  ;
+#NET "ADCA_0_n"  LOC = "R7"  ;
+#NET "ADCB_2_p"  LOC = "U7"  ;
+#NET "ADCB_2_n"  LOC = "U8"  ;
+#NET "ADCB_0_p"  LOC = "AA2"  ;
+#NET "ADCB_0_n"  LOC = "AA3"  ;
+#NET "ADCB_4_p"  LOC = "AE1"  ;
+#NET "ADCB_4_n"  LOC = "AE2"  ;
+#NET "ADCB_6_p"  LOC = "W1"  ;
+#NET "ADCB_6_n"  LOC = "W2"  ;
+#NET "ADCB_8_p"  LOC = "U3"  ;
+#NET "ADCB_8_n"  LOC = "V4"  ;
+#NET "ADCB_10_p"  LOC = "J1"  ;
+#NET "ADCB_10_n"  LOC = "K1"  ;
+#NET "ADCB_12_p"  LOC = "J3"  ;
+#NET "ADCB_12_n"  LOC = "J2"  ;
+
+## DAC
+#NET "DAC_LOCK"  LOC = "P4"  ;
+#NET "DACA<0>"  LOC = "P8"  ;
+#NET "DACA<1>"  LOC = "P9"  ;
+#NET "DACA<2>"  LOC = "R5"  ;
+#NET "DACA<3>"  LOC = "R6"  ;
+#NET "DACA<4>"  LOC = "P7"  ;
+#NET "DACA<5>"  LOC = "P6"  ;
+#NET "DACA<6>"  LOC = "T3"  ;
+#NET "DACA<7>"  LOC = "T4"  ;
+#NET "DACA<8>"  LOC = "R3"  ;
+#NET "DACA<9>"  LOC = "R4"  ;
+#NET "DACA<10>"  LOC = "R2"  ;
+#NET "DACA<11>"  LOC = "N1"  ;
+#NET "DACA<12>"  LOC = "N2"  ;
+#NET "DACA<13>"  LOC = "N5"  ;
+#NET "DACA<14>"  LOC = "N4"  ;
+#NET "DACA<15>"  LOC = "M2"  ;
+#NET "DACB<0>"  LOC = "M5"  ;
+#NET "DACB<1>"  LOC = "M6"  ;
+#NET "DACB<2>"  LOC = "M4"  ;
+#NET "DACB<3>"  LOC = "M3"  ;
+#NET "DACB<4>"  LOC = "M8"  ;
+#NET "DACB<5>"  LOC = "M7"  ;
+#NET "DACB<6>"  LOC = "L4"  ;
+#NET "DACB<7>"  LOC = "L3"  ;
+#NET "DACB<8>"  LOC = "K3"  ;
+#NET "DACB<9>"  LOC = "K2"  ;
+#NET "DACB<10>"  LOC = "K5"  ;
+#NET "DACB<11>"  LOC = "K4"  ;
+#NET "DACB<12>"  LOC = "M10"  ;
+#NET "DACB<13>"  LOC = "M9"  ;
+#NET "DACB<14>"  LOC = "J5"  ;
+#NET "DACB<15>"  LOC = "J4"  ;
+
+## TX DB GPIO
+#NET "io_tx<15>"  LOC = "K6"  ;
+#NET "io_tx<14>"  LOC = "L7"  ;
+#NET "io_tx<13>"  LOC = "H2"  ;
+#NET "io_tx<12>"  LOC = "H1"  ;
+#NET "io_tx<11>"  LOC = "L10"  ;
+#NET "io_tx<10>"  LOC = "L9"  ;
+#NET "io_tx<9>"  LOC = "G3"  ;
+#NET "io_tx<8>"  LOC = "F3"  ;
+#NET "io_tx<7>"  LOC = "K7"  ;
+#NET "io_tx<6>"  LOC = "J6"  ;
+#NET "io_tx<5>"  LOC = "E1"  ;
+#NET "io_tx<4>"  LOC = "F2"  ;
+#NET "io_tx<3>"  LOC = "J7"  ;
+#NET "io_tx<2>"  LOC = "H6"  ;
+#NET "io_tx<1>"  LOC = "F5"  ;
+#NET "io_tx<0>"  LOC = "G4"  ;
+
+## RX DB GPIO
+#NET "io_rx<15>"  LOC = "AD1"  ;
+#NET "io_rx<14>"  LOC = "AD2"  ;
+#NET "io_rx<13>"  LOC = "AC2"  ;
+#NET "io_rx<12>"  LOC = "AC3"  ;
+#NET "io_rx<11>"  LOC = "W7"  ;
+#NET "io_rx<10>"  LOC = "W6"  ;
+#NET "io_rx<9>"  LOC = "U9"  ;
+#NET "io_rx<8>"  LOC = "V8"  ;
+#NET "io_rx<7>"  LOC = "AB1"  ;
+#NET "io_rx<6>"  LOC = "AC1"  ;
+#NET "io_rx<5>"  LOC = "V7"  ;
+#NET "io_rx<4>"  LOC = "V6"  ;
+#NET "io_rx<3>"  LOC = "Y5"  ;
+#NET "io_rx<2>"  LOC = "R10"  ;
+#NET "io_rx<1>"  LOC = "R1"  ;
+#NET "io_rx<0>"  LOC = "M1"  ;
+
+## MISC
+NET "leds<5>"  LOC = "AF25"  ;
+NET "leds<4>"  LOC = "AE25"  ;
+NET "leds<3>"  LOC = "AF23"  ;
+NET "leds<2>"  LOC = "AE23"  ;
+NET "leds<1>"  LOC = "AB18"  ;
+#NET "FPGA_RESET"  LOC = "K24"  ;
+
+## Debug
+#NET "debug_clk<0>"  LOC = "AA10"  ;
+#NET "debug_clk<1>"  LOC = "AD11"  ;
+#NET "debug<0>"  LOC = "AC19"  ;
+#NET "debug<1>"  LOC = "AF20"  ;
+#NET "debug<2>"  LOC = "AE20"  ;
+#NET "debug<3>"  LOC = "AC16"  ;
+#NET "debug<4>"  LOC = "AB16"  ;
+#NET "debug<5>"  LOC = "AF19"  ;
+#NET "debug<6>"  LOC = "AE19"  ;
+#NET "debug<7>"  LOC = "V15"  ;
+#NET "debug<8>"  LOC = "U15"  ;
+#NET "debug<9>"  LOC = "AE17"  ;
+#NET "debug<10>"  LOC = "AD17"  ;
+#NET "debug<11>"  LOC = "V14"  ;
+#NET "debug<12>"  LOC = "W15"  ;
+#NET "debug<13>"  LOC = "AC15"  ;
+#NET "debug<14>"  LOC = "AD14"  ;
+#NET "debug<15>"  LOC = "AC14"  ;
+#NET "debug<16>"  LOC = "AC11"  ;
+#NET "debug<17>"  LOC = "AB12"  ;
+#NET "debug<18>"  LOC = "AC12"  ;
+#NET "debug<19>"  LOC = "V13"  ;
+#NET "debug<20>"  LOC = "W13"  ;
+#NET "debug<21>"  LOC = "AE8"  ;
+#NET "debug<22>"  LOC = "AF8"  ;
+#NET "debug<23>"  LOC = "V12"  ;
+#NET "debug<24>"  LOC = "W12"  ;
+#NET "debug<25>"  LOC = "AB9"  ;
+#NET "debug<26>"  LOC = "AC9"  ;
+#NET "debug<27>"  LOC = "AC8"  ;
+#NET "debug<28>"  LOC = "AB7"  ;
+#NET "debug<29>"  LOC = "V11"  ;
+#NET "debug<30>"  LOC = "U11"  ;
+#NET "debug<31>"  LOC = "Y10"  ;
+
+## UARTS
+#NET "TXD<3>"  LOC = "AD20"  ;
+#NET "TXD<2>"  LOC = "AC20"  ;
+#NET "TXD<1>"  LOC = "AD19"  ;
+#NET "RXD<3>"  LOC = "AF17"  ;
+#NET "RXD<2>"  LOC = "AF15"  ;
+#NET "RXD<1>"  LOC = "AD12"  ;
+
+## AD9510
+#NET "CLK_STATUS"  LOC = "AD22"  ;
+#NET "CLK_FUNC"  LOC = "AC21"  ;
+#NET "clk_sel<0>"  LOC = "AE21"  ;
+#NET "clk_sel<1>"  LOC = "AD21"  ;
+#NET "clk_en<1>"  LOC = "AA17"  ;
+#NET "clk_en<0>"  LOC = "Y17"  ;
+
+## I2C
+#NET "SDA"  LOC = "V16"  ;
+#NET "SCL"  LOC = "U16"  ;
+
+## Timing
+#NET "PPS_IN"  LOC = "AB6"  ;
+#NET "PPS2_IN"  LOC = "AA20"  ;
+
+## SPI
+#NET "SEN_CLK"  LOC = "AA18"  ;
+#NET "MOSI_CLK"  LOC = "W17"  ;
+#NET "SCLK_CLK"  LOC = "V17"  ;
+#NET "MISO_CLK"  LOC = "AC10"  ;
+
+#NET "SEN_DAC"  LOC = "AE7"  ;
+#NET "SCLK_DAC"  LOC = "AF5"  ;
+#NET "MOSI_DAC"  LOC = "AE6"  ;
+#NET "MISO_DAC"  LOC = "Y3"  ;
+
+#NET "SCLK_ADC"  LOC = "B1"  ;
+#NET "MOSI_ADC"  LOC = "J8"  ;
+#NET "SEN_ADC"  LOC = "J9"  ;
+
+#NET "MOSI_TX_ADC"  LOC = "V10"  ;
+#NET "SEN_TX_ADC"  LOC = "W10"  ;
+#NET "SCLK_TX_ADC"  LOC = "AC6"  ;
+#NET "MISO_TX_ADC"  LOC = "G1"  ;
+
+#NET "MOSI_TX_DAC"  LOC = "AD6"  ;
+#NET "SEN_TX_DAC"  LOC = "AE4"  ;
+#NET "SCLK_TX_DAC"  LOC = "AF4"  ;
+
+#NET "SCLK_TX_DB"  LOC = "AE3"  ;
+#NET "MOSI_TX_DB"  LOC = "AF3"  ;
+#NET "SEN_TX_DB"  LOC = "W9"  ;
+#NET "MISO_TX_DB"  LOC = "AA5"  ;
+
+#NET "MOSI_RX_ADC"  LOC = "E3"  ;
+#NET "SCLK_RX_ADC"  LOC = "F4"  ;
+#NET "SEN_RX_ADC"  LOC = "D3"  ;
+#NET "MISO_RX_ADC"  LOC = "C1"  ;
+
+#NET "SCLK_RX_DAC"  LOC = "E4"  ;
+#NET "SEN_RX_DAC"  LOC = "K9"  ;
+#NET "MOSI_RX_DAC"  LOC = "K8"  ;
+
+#NET "SCLK_RX_DB"  LOC = "G6"  ;
+#NET "MOSI_RX_DB"  LOC = "H7"  ;
+#NET "SEN_RX_DB"  LOC = "B2"  ;
+#NET "MISO_RX_DB"  LOC = "H4"  ;
+
+## ETH PHY
+#NET "CLK_TO_MAC"  LOC = "P26"  ;
+
+#NET "GMII_TXD<7>"  LOC = "G21"  ;
+#NET "GMII_TXD<6>"  LOC = "C26"  ;
+#NET "GMII_TXD<5>"  LOC = "C25"  ;
+#NET "GMII_TXD<4>"  LOC = "J21"  ;
+#NET "GMII_TXD<3>"  LOC = "H21"  ;
+#NET "GMII_TXD<2>"  LOC = "D25"  ;
+#NET "GMII_TXD<1>"  LOC = "D24"  ;
+#NET "GMII_TXD<0>"  LOC = "E26"  ;
+#NET "GMII_TX_EN"  LOC = "D26"  ;
+#NET "GMII_TX_ER"  LOC = "J19"  ;
+#NET "GMII_GTX_CLK"  LOC = "J20"  ;
+#NET "GMII_TX_CLK"  LOC = "P25"  ;
+
+#NET "GMII_RX_CLK"  LOC = "P21"  ;
+#NET "GMII_RXD<7>"  LOC = "G22"  ;
+#NET "GMII_RXD<6>"  LOC = "K19"  ;
+#NET "GMII_RXD<5>"  LOC = "K18"  ;
+#NET "GMII_RXD<4>"  LOC = "E24"  ;
+#NET "GMII_RXD<3>"  LOC = "F23"  ;
+#NET "GMII_RXD<2>"  LOC = "L18"  ;
+#NET "GMII_RXD<1>"  LOC = "L17"  ;
+#NET "GMII_RXD<0>"  LOC = "F25"  ;
+#NET "GMII_RX_DV"  LOC = "F24"  ;
+#NET "GMII_RX_ER"  LOC = "L20"  ;
+#NET "GMII_CRS"  LOC = "K20"  ;
+#NET "GMII_COL"  LOC = "G23"  ;
+
+#NET "PHY_INTn"  LOC = "L22"  ;
+#NET "MDIO"  LOC = "K21"  ;
+#NET "MDC"  LOC = "J23"  ;
+#NET "PHY_RESETn"  LOC = "J22"  ;
+NET "ETH_LED"  LOC = "H20"  ;
+
+## MIMO Interface
+#NET "exp_time_out_p"  LOC = "Y14"  ;
+#NET "exp_time_out_n"  LOC = "AA14"  ;
+#NET "exp_time_in_p"  LOC = "N18"  ;
+#NET "exp_time_in_n"  LOC = "N17"  ;
+#NET "exp_user_out_p"  LOC = "AF14"  ;
+#NET "exp_user_out_n"  LOC = "AE14"  ;
+#NET "exp_user_in_p"  LOC = "L24"  ;
+#NET "exp_user_in_n"  LOC = "M23"  ;
+
+## SERDES
+#NET "ser_enable"  LOC = "R20"  ;
+#NET "ser_prbsen"  LOC = "U23"  ;
+#NET "ser_loopen"  LOC = "R19"  ;
+#NET "ser_rx_en"  LOC = "Y21"  ;
+#NET "ser_tx_clk"  LOC = "P23"  ;   # SERDES TX CLK
+#NET "ser_t<15>"  LOC = "V23"  ;
+#NET "ser_t<14>"  LOC = "U22"  ;
+#NET "ser_t<13>"  LOC = "V24"  ;
+#NET "ser_t<12>"  LOC = "V25"  ;
+#NET "ser_t<11>"  LOC = "W23"  ;
+#NET "ser_t<10>"  LOC = "V22"  ;
+#NET "ser_t<9>"  LOC = "T18"  ;
+#NET "ser_t<8>"  LOC = "T17"  ;
+#NET "ser_t<7>"  LOC = "Y24"  ;
+#NET "ser_t<6>"  LOC = "Y25"  ;
+#NET "ser_t<5>"  LOC = "U21"  ;
+#NET "ser_t<4>"  LOC = "T20"  ;
+#NET "ser_t<3>"  LOC = "Y22"  ;
+#NET "ser_t<2>"  LOC = "Y23"  ;
+#NET "ser_t<1>"  LOC = "U19"  ;
+#NET "ser_t<0>"  LOC = "U18"  ;
+#NET "ser_tkmsb"  LOC = "AA24"  ;
+#NET "ser_tklsb"  LOC = "AA25"  ;
+#NET "ser_rx_clk"  LOC = "P18"  ;
+#NET "ser_r<15>"  LOC = "V21"  ;
+#NET "ser_r<14>"  LOC = "U20"  ;
+#NET "ser_r<13>"  LOC = "AA22"  ;
+#NET "ser_r<12>"  LOC = "AA23"  ;
+#NET "ser_r<11>"  LOC = "V18"  ;
+#NET "ser_r<10>"  LOC = "V19"  ;
+#NET "ser_r<9>"  LOC = "AB23"  ;
+#NET "ser_r<8>"  LOC = "AC26"  ;
+#NET "ser_r<7>"  LOC = "AB26"  ;
+#NET "ser_r<6>"  LOC = "AD26"  ;
+#NET "ser_r<5>"  LOC = "AC25"  ;
+#NET "ser_r<4>"  LOC = "W20"  ;
+#NET "ser_r<3>"  LOC = "W21"  ;
+#NET "ser_r<2>"  LOC = "AC23"  ;
+#NET "ser_r<1>"  LOC = "AC24"  ;
+#NET "ser_r<0>"  LOC = "AE26"  ;
+#NET "ser_rkmsb"  LOC = "AD25"  ;
+#NET "ser_rklsb"  LOC = "Y20"  ;
+
+## SRAM
+#NET "RAM_D<35>"  LOC = "K16"  ;
+#NET "RAM_D<34>"  LOC = "D20"  ;
+#NET "RAM_D<33>"  LOC = "C20"  ;
+#NET "RAM_D<32>"  LOC = "E21"  ;
+#NET "RAM_D<31>"  LOC = "D21"  ;
+#NET "RAM_D<30>"  LOC = "C21"  ;
+#NET "RAM_D<29>"  LOC = "B21"  ;
+#NET "RAM_D<28>"  LOC = "H17"  ;
+#NET "RAM_D<27>"  LOC = "G17"  ;
+#NET "RAM_D<26>"  LOC = "B23"  ;
+#NET "RAM_D<25>"  LOC = "A22"  ;
+#NET "RAM_D<24>"  LOC = "D23"  ;
+#NET "RAM_D<23>"  LOC = "C23"  ;
+#NET "RAM_D<22>"  LOC = "D22"  ;
+#NET "RAM_D<21>"  LOC = "C22"  ;
+#NET "RAM_D<20>"  LOC = "F19"  ;
+#NET "RAM_D<19>"  LOC = "G20"  ;
+#NET "RAM_D<18>"  LOC = "F20"  ;
+#NET "RAM_D<17>"  LOC = "F7"  ;
+#NET "RAM_D<16>"  LOC = "E7"  ;
+#NET "RAM_D<15>"  LOC = "G9"  ;
+#NET "RAM_D<14>"  LOC = "H9"  ;
+#NET "RAM_D<13>"  LOC = "G10"  ;
+#NET "RAM_D<12>"  LOC = "H10"  ;
+#NET "RAM_D<11>"  LOC = "A4"  ;
+#NET "RAM_D<10>"  LOC = "B4"  ;
+#NET "RAM_D<9>"  LOC = "C5"  ;
+#NET "RAM_D<8>"  LOC = "D6"  ;
+#NET "RAM_D<7>"  LOC = "J11"  ;
+#NET "RAM_D<6>"  LOC = "K11"  ;
+#NET "RAM_D<5>"  LOC = "B7"  ;
+#NET "RAM_D<4>"  LOC = "C7"  ;
+#NET "RAM_D<3>"  LOC = "B6"  ;
+#NET "RAM_D<2>"  LOC = "C6"  ;
+#NET "RAM_D<1>"  LOC = "C8"  ;
+#NET "RAM_D<0>"  LOC = "D8"  ;
+#NET "RAM_A<0>"  LOC = "C11"  ;
+#NET "RAM_A<1>"  LOC = "E12"  ;
+#NET "RAM_A<2>"  LOC = "F12"  ;
+#NET "RAM_A<3>"  LOC = "D13"  ;
+#NET "RAM_A<4>"  LOC = "C12"  ;
+#NET "RAM_A<5>"  LOC = "A12"  ;
+#NET "RAM_A<6>"  LOC = "B12"  ;
+#NET "RAM_A<7>"  LOC = "E14"  ;
+#NET "RAM_A<8>"  LOC = "F14"  ;
+#NET "RAM_A<9>"  LOC = "B15"  ;
+#NET "RAM_A<10>"  LOC = "A15"  ;
+#NET "RAM_A<11>"  LOC = "D16"  ;
+#NET "RAM_A<12>"  LOC = "C15"  ;
+#NET "RAM_A<13>"  LOC = "D17"  ;
+#NET "RAM_A<14>"  LOC = "C16"  ;
+#NET "RAM_A<15>"  LOC = "F15"  ;
+#NET "RAM_A<16>"  LOC = "C17"  ;
+#NET "RAM_A<17>"  LOC = "B17"  ;
+#NET "RAM_A<18>"  LOC = "B18"  ;
+#NET "RAM_A<19>"  LOC = "A18"  ;
+#NET "RAM_A<20>"  LOC = "D18"  ;
+#NET "RAM_BWn<3>"  LOC = "D9"  ;
+#NET "RAM_BWn<2>"  LOC = "A9"  ;
+#NET "RAM_BWn<1>"  LOC = "B9"  ;
+#NET "RAM_BWn<0>"  LOC = "G12"  ;
+#NET "RAM_ZZ"  LOC = "J12"  ;
+#NET "RAM_LDn"  LOC = "H12"  ;
+#NET "RAM_OEn"  LOC = "C10"  ;
+#NET "RAM_WEn"  LOC = "D10"  ;
+#NET "RAM_CENn"  LOC = "B10"  ;
+#NET "RAM_CLK"  LOC = "A10"  ;
+
+## SPI Flash
+#NET "flash_miso"  LOC = "AF24"  ;
+#NET "flash_clk"  LOC = "AE24"  ;
+#NET "flash_mosi"  LOC = "AB15"  ;
+#NET "flash_cs"  LOC = "AA7"  ;
+
+## MISC FPGA, unused for now
+##NET "PROG_B"  LOC = "A2"  ;
+##NET "PUDC_B"  LOC = "G8"  ;
+##NET "DONE"  LOC = "AB21"  ;
+##NET "INIT_B"  LOC = "AA15"  ;
+
+
+##NET "unnamed_net19"  LOC = "AE9"  ;    # VS1
+##NET "unnamed_net18"  LOC = "AF9"  ;    # VS0
+##NET "unnamed_net17"  LOC = "AA12"  ;   # VS2
+##NET "unnamed_net16"  LOC = "Y7"  ;     # M2
+##NET "unnamed_net15"  LOC = "AC4"  ;    # M1
+##NET "unnamed_net14"  LOC = "AD4"  ;    # M0
+##NET "unnamed_net13"  LOC = "D4"  ;     # TMS
+##NET "unnamed_net12"  LOC = "E23"  ;    # TDO
+##NET "unnamed_net11"  LOC = "G7"  ;     # TDI
+##NET "unnamed_net10"  LOC = "A25"  ;    # TCK
+##NET "unnamed_net20"  LOC = "V20"  ;    # SUSPEND
diff --git a/fpga/usrp2/top/u1e/.gitignore b/fpga/usrp2/top/u1e/.gitignore
new file mode 100644
index 000000000..8d872713e
--- /dev/null
+++ b/fpga/usrp2/top/u1e/.gitignore
@@ -0,0 +1,6 @@
+*~
+build
+*.log
+*.cmd
+tb_u1e
+*.lxt
diff --git a/fpga/usrp2/top/u1e/Makefile b/fpga/usrp2/top/u1e/Makefile
new file mode 100644
index 000000000..3cb9fd8f3
--- /dev/null
+++ b/fpga/usrp2/top/u1e/Makefile
@@ -0,0 +1,101 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u1e
+BUILD_DIR = $(abspath build$(ISE))
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
+include ../../gpmc/Makefile.srcs
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+u1e_core.v \
+u1e.v \
+u1e.ucf \
+timing.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(GPMC_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/u1e/README b/fpga/usrp2/top/u1e/README
new file mode 100644
index 000000000..14c7a4955
--- /dev/null
+++ b/fpga/usrp2/top/u1e/README
@@ -0,0 +1,4 @@
+
+make clean
+make sim
+./tb_u1e -lxt2
diff --git a/fpga/usrp2/top/u1e/cmdfile b/fpga/usrp2/top/u1e/cmdfile
new file mode 100644
index 000000000..291c723b8
--- /dev/null
+++ b/fpga/usrp2/top/u1e/cmdfile
@@ -0,0 +1,20 @@
+
+# My stuff
+-y .
+-y ../../control_lib
+-y ../../control_lib/newfifo
+-y ../../sdr_lib
+-y ../../timing
+-y ../../coregen
+-y ../../gpmc
+
+# Models
+-y ../../models
+-y /opt/Xilinx/10.1/ISE/verilog/src/unisims
+
+# Open Cores
+-y ../../opencores/spi/rtl/verilog
++incdir+../../opencores/spi/rtl/verilog
+-y ../../opencores/i2c/rtl/verilog
++incdir+../../opencores/i2c/rtl/verilog
+
diff --git a/fpga/usrp2/top/u1e/make.sim b/fpga/usrp2/top/u1e/make.sim
new file mode 100644
index 000000000..1c163884c
--- /dev/null
+++ b/fpga/usrp2/top/u1e/make.sim
@@ -0,0 +1,7 @@
+all: sim
+
+sim:	
+	iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e
+
+clean:
+	rm -f tb_u1e *.vcd *.lxt a.out
diff --git a/fpga/usrp2/top/u1e/tb_u1e.v b/fpga/usrp2/top/u1e/tb_u1e.v
new file mode 100644
index 000000000..5fc8134fb
--- /dev/null
+++ b/fpga/usrp2/top/u1e/tb_u1e.v
@@ -0,0 +1,41 @@
+`timescale 1ps / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module tb_u1e();
+   
+   wire [2:0] debug_led;
+   wire [31:0] debug;
+   wire [1:0] debug_clk;
+
+   xlnx_glbl glbl (.GSR(),.GTS());
+
+   initial begin
+      $dumpfile("tb_u1e.lxt");
+      $dumpvars(0,tb_u1e);
+   end
+    
+   // GPMC
+   wire       EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE;
+   wire [15:0] EM_D;
+   wire [10:1] EM_A;
+   wire [1:0]  EM_NBE;
+   
+   reg  clk_fpga = 0, rst_fpga = 1;
+   always #15625 clk_fpga = ~clk_fpga;
+
+   initial #200000
+     @(posedge clk_fpga)
+       rst_fpga <= 0;
+   
+   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), 
+		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
+		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+
+   gpmc_model_async gpmc_model_async
+     (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+      .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
+      .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+   
+endmodule // tb_u1e
diff --git a/fpga/usrp2/top/u1e/timing.ucf b/fpga/usrp2/top/u1e/timing.ucf
new file mode 100644
index 000000000..8df28c9d3
--- /dev/null
+++ b/fpga/usrp2/top/u1e/timing.ucf
@@ -0,0 +1,13 @@
+
+NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;
+
+
+
+
+#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
+#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
+#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+
+#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
diff --git a/fpga/usrp2/top/u1e/u1e.ucf b/fpga/usrp2/top/u1e/u1e.ucf
new file mode 100644
index 000000000..0c487a601
--- /dev/null
+++ b/fpga/usrp2/top/u1e/u1e.ucf
@@ -0,0 +1,259 @@
+
+NET "CLK_FPGA_P"  LOC = "Y11"  ;
+NET "CLK_FPGA_N"  LOC = "Y10"  ;
+
+## GPMC
+NET "EM_D<15>"  LOC = "D13"  ;
+NET "EM_D<14>"  LOC = "D15"  ;
+NET "EM_D<13>"  LOC = "C16"  ;
+NET "EM_D<12>"  LOC = "B20"  ;
+NET "EM_D<11>"  LOC = "A19"  ;
+NET "EM_D<10>"  LOC = "A17"  ;
+NET "EM_D<9>"  LOC = "E15"  ;
+NET "EM_D<8>"  LOC = "F15"  ;
+NET "EM_D<7>"  LOC = "E16"  ;
+NET "EM_D<6>"  LOC = "F16"  ;
+NET "EM_D<5>"  LOC = "B17"  ;
+NET "EM_D<4>"  LOC = "C17"  ;
+NET "EM_D<3>"  LOC = "B19"  ;
+NET "EM_D<2>"  LOC = "D19"  ;
+NET "EM_D<1>"  LOC = "C19"  ;
+NET "EM_D<0>"  LOC = "A20"  ;
+
+NET "EM_A<10>"  LOC = "C14"  ;
+NET "EM_A<9>"  LOC = "C10"  ;
+NET "EM_A<8>"  LOC = "C5"  ;
+NET "EM_A<7>"  LOC = "A18"  ;
+NET "EM_A<6>"  LOC = "A15"  ;
+NET "EM_A<5>"  LOC = "A12"  ;
+NET "EM_A<4>"  LOC = "A10"  ;
+NET "EM_A<3>"  LOC = "E7"  ;
+NET "EM_A<2>"  LOC = "A7"  ;
+NET "EM_A<1>"  LOC = "C15"  ;
+
+NET "EM_NCS6"  LOC = "E17"  ;
+NET "EM_NCS5"  LOC = "E10"  ;
+NET "EM_NCS4"  LOC = "E6"  ;
+#NET "EM_NCS1"  LOC = "D18"  ;
+#NET "EM_NCS0"  LOC = "D17"  ;
+
+NET "EM_CLK"  LOC = "F11"  ;
+NET "EM_WAIT0"  LOC = "F14"  ;
+NET "EM_NBE<1>"  LOC = "D14"  ;
+NET "EM_NBE<0>"  LOC = "A13"  ;
+NET "EM_NWE"  LOC = "B13"  ;
+NET "EM_NOE"  LOC = "A14"  ;
+#NET "EM_NADV_ALE"  LOC = "B15"  ;
+#NET "EM_NWP"  LOC = "F13"  ;
+
+## Overo GPIO
+NET "overo_gpio0"  LOC = "F9"  ;  # MISC GPIO for debug
+NET "overo_gpio14"  LOC = "C4"  ;  # MISC GPIO for debug
+NET "overo_gpio21"  LOC = "D5"  ;  # MISC GPIO for debug
+NET "overo_gpio22"  LOC = "A3"  ;  # MISC GPIO for debug
+NET "overo_gpio23"  LOC = "B3"  ;  # MISC GPIO for debug
+NET "overo_gpio64"  LOC = "A4"  ;  # MISC GPIO for debug
+NET "overo_gpio65"  LOC = "F8"  ;  # MISC GPIO for debug
+
+NET "overo_gpio127"  LOC = "C8"  ;  # Changed name to gpio10
+NET "overo_gpio128"  LOC = "G8"  ;  # Changed name to gpio186
+
+NET "overo_gpio144"  LOC = "A5"  ;  # tx_have_space
+NET "overo_gpio145"  LOC = "C7"  ;  # tx_underrun
+NET "overo_gpio146"  LOC = "A6"  ;  # rx_have_data
+NET "overo_gpio147"  LOC = "B6"  ;  # rx_overrun
+NET "overo_gpio163"  LOC = "D7"  ;  # MISC GPIO for debug
+NET "overo_gpio170"  LOC = "E8"  ;  # MISC GPIO for debug
+NET "overo_gpio176"  LOC = "B4"  ;  # MISC GPIO for debug
+
+## Overo UART
+#NET "overo_txd1"  LOC = "C6"  ;
+#NET "overo_rxd1"  LOC = "D6"  ;
+
+## FTDI UART to USB converter
+NET "FPGA_TXD"  LOC = "G19"  ;
+NET "FPGA_RXD"  LOC = "F20"  ;
+
+#NET "SYSEN"  LOC = "C11"  ;
+
+## I2C
+NET "db_scl"  LOC = "F19"  ;
+NET "db_sda"  LOC = "F18"  ;
+
+## SPI
+### DBoard SPI
+NET "db_sclk_rx"  LOC = "D21"  ;
+NET "db_miso_rx"  LOC = "D22"  ;
+NET "db_mosi_rx"  LOC = "D20"  ;
+NET "db_sen_rx"  LOC = "E19"  ;
+NET "db_sclk_tx"  LOC = "F21"  ;
+NET "db_miso_tx"  LOC = "E20"  ;
+NET "db_mosi_tx"  LOC = "G17"  ;
+NET "db_sen_tx"  LOC = "G18"  ;
+
+### AD9862 SPI and aux SPI Interfaces
+#NET "aux_sdi_codec"  LOC = "G3"  ;
+#NET "aux_sdo_codec"  LOC = "F3"  ;
+#NET "aux_sclk_codec"  LOC = "C1"  ;
+NET "sen_codec"  LOC = "F5"  |IOSTANDARD = LVCMOS33;
+NET "mosi_codec"  LOC = "F4"  |IOSTANDARD = LVCMOS33;
+NET "miso_codec"  LOC = "H4"  ;
+NET "sclk_codec"  LOC = "H3"  |IOSTANDARD = LVCMOS33;
+
+### Clock Gen SPI
+NET "cgen_miso"  LOC = "F22"  ;
+NET "cgen_mosi"  LOC = "E22"  ;
+NET "cgen_sclk"  LOC = "J19"  ;
+NET "cgen_sen_b"  LOC = "H20"  ;
+
+## Clock gen control
+NET "cgen_st_status"  LOC = "P20"  ;
+NET "cgen_st_ld"  LOC = "R17"  ;
+NET "cgen_st_refmon"  LOC = "P17"  ;
+NET "cgen_sync_b"  LOC = "U18"  ;
+NET "cgen_ref_sel"  LOC = "U19"  ;
+
+## Debug pins
+NET "debug_led<3>"  LOC = "Y15"  ;
+NET "debug_led<2>"  LOC = "K16"  ;
+NET "debug_led<1>"  LOC = "J17"  ;
+NET "debug_led<0>"  LOC = "H22"  ;
+NET "debug<0>"  LOC = "G22"  ;
+NET "debug<1>"  LOC = "H17"  ;
+NET "debug<2>"  LOC = "H18"  ;
+NET "debug<3>"  LOC = "K20"  ;
+NET "debug<4>"  LOC = "J20"  ;
+NET "debug<5>"  LOC = "K19"  ;
+NET "debug<6>"  LOC = "K18"  ;
+NET "debug<7>"  LOC = "L22"  ;
+NET "debug<8>"  LOC = "K22"  ;
+NET "debug<9>"  LOC = "N22"  ;
+NET "debug<10>"  LOC = "M22"  ;
+NET "debug<11>"  LOC = "N20"  ;
+NET "debug<12>"  LOC = "N19"  ;
+NET "debug<13>"  LOC = "R22"  ;
+NET "debug<14>"  LOC = "P22"  ;
+NET "debug<15>"  LOC = "N17"  ;
+NET "debug<16>"  LOC = "P16"  ;
+NET "debug<17>"  LOC = "U22"  ;
+NET "debug<18>"  LOC = "P19"  ;
+NET "debug<19>"  LOC = "R18"  ;
+NET "debug<20>"  LOC = "U20"  ;
+NET "debug<21>"  LOC = "T20"  ;
+NET "debug<22>"  LOC = "R19"  ;
+NET "debug<23>"  LOC = "R20"  ;
+NET "debug<24>"  LOC = "W22"  ;
+NET "debug<25>"  LOC = "Y22"  ;
+NET "debug<26>"  LOC = "T18"  ;
+NET "debug<27>"  LOC = "T17"  ;
+NET "debug<28>"  LOC = "W19"  ;
+NET "debug<29>"  LOC = "V20"  ;
+NET "debug<30>"  LOC = "Y21"  ;
+NET "debug<31>"  LOC = "AA22"  ;
+NET "debug_clk<0>"  LOC = "N18"  ;
+NET "debug_clk<1>"  LOC = "M17"  ;
+
+NET "debug_pb"  LOC = "C22"  ;
+
+#NET "reset_codec"  LOC = "C2"  ;
+
+NET "RXSYNC"  LOC = "F2"  ;
+NET "DB<11>"  LOC = "G6"  ;
+NET "DB<10>"  LOC = "G5"  ;
+NET "DB<9>"  LOC = "E4"  ;
+NET "DB<8>"  LOC = "E3"  ;
+NET "DB<7>"  LOC = "H6"  ;
+NET "DB<6>"  LOC = "H5"  ;
+NET "DB<5>"  LOC = "H1"  ;
+NET "DB<4>"  LOC = "G1"  ;
+NET "DB<3>"  LOC = "K5"  ;
+NET "DB<2>"  LOC = "K4"  ;
+NET "DB<1>"  LOC = "H2"  ;
+NET "DB<0>"  LOC = "L5"  ;
+
+NET "DA<11>"  LOC = "K6"  ;
+NET "DA<10>"  LOC = "K3"  ;
+NET "DA<9>"  LOC = "K2"  ;
+NET "DA<8>"  LOC = "N1"  ;
+NET "DA<7>"  LOC = "N5"  ;
+NET "DA<6>"  LOC = "N6"  ;
+NET "DA<5>"  LOC = "P2"  ;
+NET "DA<4>"  LOC = "P1"  ;
+NET "DA<3>"  LOC = "R6"  ;
+NET "DA<2>"  LOC = "P6"  ;
+NET "DA<1>"  LOC = "R1"  ;
+NET "DA<0>"  LOC = "R2"  ;
+
+NET "TX<13>"  LOC = "T6"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<12>"  LOC = "U1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<11>"  LOC = "T1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<10>"  LOC = "R5"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<9>"  LOC = "V1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<8>"  LOC = "U2"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<7>"  LOC = "T4"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<6>"  LOC = "R3"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<5>"  LOC = "W1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<4>"  LOC = "Y1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<3>"  LOC = "V3"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<2>"  LOC = "V4"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<1>"  LOC = "W2"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<0>"  LOC = "W3"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TXSYNC"  LOC = "U5"   |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TXBLANK"  LOC = "U4"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+
+NET "PPS_IN"  LOC = "M5"  ;
+
+NET "io_tx<0>"  LOC = "AB20"  ;
+NET "io_tx<1>"  LOC = "Y17"  ;
+NET "io_tx<2>"  LOC = "Y16"  ;
+NET "io_tx<3>"  LOC = "U16"  ;
+NET "io_tx<4>"  LOC = "V16"  ;
+NET "io_tx<5>"  LOC = "AB19"  ;
+NET "io_tx<6>"  LOC = "AA19"  ;
+NET "io_tx<7>"  LOC = "U14"  ;
+NET "io_tx<8>"  LOC = "U15"  ;
+NET "io_tx<9>"  LOC = "AB17"  ;
+NET "io_tx<10>"  LOC = "AB18"  ;
+NET "io_tx<11>"  LOC = "Y13"  ;
+NET "io_tx<12>"  LOC = "W14"  ;
+NET "io_tx<13>"  LOC = "U13"  ;
+NET "io_tx<14>"  LOC = "AA15"  ;
+NET "io_tx<15>"  LOC = "AB14"  ;
+
+NET "io_rx<0>"  LOC = "Y8"  ;
+NET "io_rx<1>"  LOC = "Y9"  ;
+NET "io_rx<2>"  LOC = "V7"  ;
+NET "io_rx<3>"  LOC = "U8"  ;
+NET "io_rx<4>"  LOC = "V10"  ;
+NET "io_rx<5>"  LOC = "U9"  ;
+NET "io_rx<6>"  LOC = "AB7"  ;
+NET "io_rx<7>"  LOC = "AA8"  ;
+NET "io_rx<8>"  LOC = "W8"  ;
+NET "io_rx<9>"  LOC = "V8"  ;
+NET "io_rx<10>"  LOC = "AB5"  ;
+NET "io_rx<11>"  LOC = "AB6"  ;
+NET "io_rx<12>"  LOC = "AB4"  ;
+NET "io_rx<13>"  LOC = "AA4"  ;
+NET "io_rx<14>"  LOC = "W5"  ;
+NET "io_rx<15>"  LOC = "Y4"  ;
+
+#NET "CLKOUT2_CODEC"  LOC = "U12"  ;
+#NET "CLKOUT1_CODEC"  LOC = "V12"  ;
+
+## FPGA Config Pins
+#NET "fpga_cfg_prog_b"  LOC = "A2"  ;
+#NET "fpga_cfg_done"  LOC = "AB21"  ;
+#NET "fpga_cfg_din"  LOC = "W17"  ;
+#NET "fpga_cfg_cclk"  LOC = "V17"  ;
+#NET "fpga_cfg_init_b"  LOC = "W15"  ;
+
+## Unused
+#NET "unnamed_net53"  LOC = "B1"  ;  # TMS
+#NET "unnamed_net52"  LOC = "B22"  ; # TDO
+#NET "unnamed_net51"  LOC = "D2"  ;  # TDI
+#NET "unnamed_net50"  LOC = "A21"  ; # TCK
+#NET "unnamed_net59"  LOC = "F7"  ;  # PUDC_B
+#NET "unnamed_net58"  LOC = "V6"  ;  # M2
+#NET "unnamed_net57"  LOC = "AA3"  ; # M1
+#NET "unnamed_net56"  LOC = "AB3"  ; # M0
+#NET "GND"  LOC = "V19"  ;  # Suspend, unused
diff --git a/fpga/usrp2/top/u1e/u1e.v b/fpga/usrp2/top/u1e/u1e.v
new file mode 100644
index 000000000..445b14a03
--- /dev/null
+++ b/fpga/usrp2/top/u1e/u1e.v
@@ -0,0 +1,141 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u1e
+  (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
+   output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+   input debug_pb, output FPGA_TXD, input FPGA_RXD,
+
+   // GPMC
+   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+   input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6,
+   input EM_NWE, input EM_NOE,
+
+   inout db_sda, inout db_scl, // I2C
+
+   output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx,   // DB TX SPI
+   output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx,   // DB TX SPI
+   output sclk_codec, output sen_codec, output mosi_codec, input miso_codec,   // AD9862 main SPI
+   output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso,     // Clock gen SPI
+
+   input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,
+   
+   output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147,  // Fifo controls
+   input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22,  // Misc GPIO
+   input overo_gpio23, input overo_gpio64, input overo_gpio65, input overo_gpio127, // Misc GPIO
+   input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO
+   
+   inout [15:0] io_tx, inout [15:0] io_rx,
+
+   output [13:0] TX, output TXSYNC, output TXBLANK,
+   input [11:0] DA, input [11:0] DB, input RXSYNC,
+  
+   input PPS_IN
+   );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Clocking
+   wire  clk_fpga, clk_fpga_in;
+   
+   IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
+   clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+
+   wire  clk_2x, dcm_rst, dcm_locked, clk_fb;
+   DCM #(.CLK_FEEDBACK ( "1X" ),
+	 .CLKDV_DIVIDE ( 2 ),
+	 .CLKFX_DIVIDE ( 2 ),
+	 .CLKFX_MULTIPLY ( 2 ),
+	 .CLKIN_DIVIDE_BY_2 ( "FALSE" ),
+	 .CLKIN_PERIOD ( 15.625 ),
+	 .CLKOUT_PHASE_SHIFT ( "NONE" ),
+	 .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ),
+	 .DFS_FREQUENCY_MODE ( "LOW" ),
+	 .DLL_FREQUENCY_MODE ( "LOW" ),
+	 .DUTY_CYCLE_CORRECTION ( "TRUE" ),
+	 .FACTORY_JF ( 16'h8080 ),
+	 .PHASE_SHIFT ( 0 ),
+	 .STARTUP_WAIT ( "FALSE" ))
+   clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), 
+                .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), 
+		.CLKDV(), .CLKFX(), .CLKFX180(), 
+                .CLK2X(), .CLK2X180(), 
+                .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), 
+                .LOCKED(dcm_locked), .STATUS());
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // SPI
+   wire  mosi, sclk, miso;
+   assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0;
+   assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0;
+   assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0;
+   assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0;
+   assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) |
+		 (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso);
+
+   // /////////////////////////////////////////////////////////////////////////
+   // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL
+
+   assign TXBLANK = 0;
+   wire [13:0] tx_i, tx_q;
+
+   reg[13:0] delay_q;
+   always @(posedge clk_fpga)
+     delay_q <= tx_q;
+   
+   genvar i;
+   generate
+      for(i=0;i<14;i=i+1)
+	begin : gen_dacout
+	   ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
+		   .INIT(1'b0),            // Sets initial state of the Q output to 1'b0 or 1'b1
+		   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
+	   ODDR2_inst (.Q(TX[i]),      // 1-bit DDR output data
+		       .C0(clk_fpga),  // 1-bit clock input
+		       .C1(~clk_fpga), // 1-bit clock input
+		       .CE(1'b1),      // 1-bit clock enable input
+		       .D0(tx_i[i]),   // 1-bit data input (associated with C0)
+		       .D1(delay_q[i]),   // 1-bit data input (associated with C1)
+		       .R(1'b0),       // 1-bit reset input
+		       .S(1'b0));      // 1-bit set input
+	end // block: gen_dacout
+      endgenerate
+   ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
+	   .INIT(1'b0),            // Sets initial state of the Q output to 1'b0 or 1'b1
+	   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
+   ODDR2_txsnc (.Q(TXSYNC),      // 1-bit DDR output data
+		.C0(clk_fpga),  // 1-bit clock input
+		.C1(~clk_fpga), // 1-bit clock input
+		.CE(1'b1),      // 1-bit clock enable input
+		.D0(1'b0),   // 1-bit data input (associated with C0)
+		.D1(1'b1),   // 1-bit data input (associated with C1)
+		.R(1'b0),       // 1-bit reset input
+		.S(1'b0));      // 1-bit set input
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Main U1E Core
+   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb),
+		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+		     .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
+		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), 
+		     .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
+		     .db_sda(db_sda), .db_scl(db_scl),
+		     .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso),
+		     .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), 
+		     .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel),
+		     .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145),
+		     .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147),
+		     .io_tx(io_tx), .io_rx(io_rx),
+		     .tx_i(tx_i), .tx_q(tx_q), 
+		     .rx_i(DA), .rx_q(DB),
+		     .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176},
+				  {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22},
+				  {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}),
+		     .pps_in(PPS_IN) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Local Debug
+   // assign debug_clk = {clk_fpga, clk_2x };
+   // assign debug = { TXSYNC, TXBLANK, TX };
+   
+endmodule // u1e
diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v
new file mode 100644
index 000000000..e7e798b34
--- /dev/null
+++ b/fpga/usrp2/top/u1e/u1e_core.v
@@ -0,0 +1,459 @@
+
+
+//`define LOOPBACK 1
+//`define TIMED 1
+`define DSP 1
+
+module u1e_core
+  (input clk_fpga, input rst_fpga,
+   output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+   output debug_txd, input debug_rxd,
+   
+   // GPMC
+   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+   input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6,
+   input EM_NWE, input EM_NOE,
+   
+   inout db_sda, inout db_scl,
+   output sclk, output [7:0] sen, output mosi, input miso,
+
+   input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,   
+   output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun,
+   inout [15:0] io_tx, inout [15:0] io_rx, 
+   output [13:0] tx_i, output [13:0] tx_q, 
+   input [11:0] rx_i, input [11:0] rx_q, 
+   
+   input [11:0] misc_gpio, input pps_in
+   );
+
+   localparam TXFIFOSIZE = 13;
+   localparam RXFIFOSIZE = 13;
+
+   localparam SR_RX_DSP = 0;     // 5 regs
+   localparam SR_CLEAR_FIFO = 6; // 1 reg
+   localparam SR_RX_CTRL = 8;    // 9 regs
+   localparam SR_TX_DSP = 17;    // 5 regs
+   localparam SR_TX_CTRL = 24;   // 2 regs
+   localparam SR_TIME64 = 28;    // 4 regs
+
+   wire [7:0]	COMPAT_NUM = 8'd2;
+   
+   wire 	wb_clk = clk_fpga;
+   wire 	wb_rst = rst_fpga;
+   
+   wire 	pps_int;
+   wire [63:0] 	vita_time;
+   reg [15:0] 	reg_leds, reg_cgen_ctrl, reg_test, xfer_rate;
+   
+   wire [7:0] 	set_addr;
+   wire [31:0] 	set_data;
+   wire 	set_stb;
+
+   wire [31:0] 	debug_vt;
+
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // GPMC Slave to Wishbone Master
+   localparam dw = 16;
+   localparam aw = 11;
+   localparam sw = 2;
+   
+   wire [dw-1:0] m0_dat_mosi, m0_dat_miso;
+   wire [aw-1:0] m0_adr;
+   wire [sw-1:0] m0_sel;
+   wire 	 m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty;
+
+   wire [31:0] 	 debug_gpmc;
+
+   wire [35:0] 	 tx_data, rx_data, tx_err_data;
+   wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, 
+		 tx_err_src_rdy, tx_err_dst_rdy;
+   reg [15:0] 	 tx_frame_len;
+   wire [15:0] 	 rx_frame_len;
+   wire [7:0] 	 rate;
+
+   wire 	 bus_error;
+
+   wire 	 clear_rx_int, clear_tx_int, clear_tx, clear_rx, do_clear;
+   
+   setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(2)) sr_clear
+     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({clear_tx_int,clear_rx_int}),.changed(do_clear));
+   assign clear_tx = clear_tx_int & do_clear;
+   assign clear_rx = clear_rx_int & do_clear;
+   
+   gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
+   gpmc (.arst(wb_rst),
+	 .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+	 .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), 
+	 .EM_NOE(EM_NOE),
+	 
+	 .rx_have_data(rx_have_data), .tx_have_space(tx_have_space),
+	 .bus_error(bus_error), .bus_reset(0),
+	 
+	 .wb_clk(wb_clk), .wb_rst(wb_rst),
+	 .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
+	 .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
+	 .wb_ack_i(m0_ack),
+	 
+	 .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx),
+	 .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
+	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
+	 
+	 .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len),
+	 .debug(debug_gpmc));
+
+   wire 	 rx_sof = rx_data[32];
+   wire 	 rx_eof = rx_data[33];
+   wire 	 rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int;
+   
+`ifdef LOOPBACK
+   wire [7:0] 	 WHOAMI = 1;
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx),
+      .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
+      .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+
+   assign tx_underrun = 0;
+   assign rx_overrun = 0;
+
+   wire 	 run_tx, run_rx, strobe_tx, strobe_rx;
+`endif // LOOPBACK
+
+`ifdef TIMED
+   wire [7:0] 	 WHOAMI = 2;
+   
+   // TX side
+   wire 	 tx_enable;
+   
+   fifo_pacer tx_pacer
+     (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable),
+      .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy),
+      .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int),
+      .underrun(tx_underrun), .overrun());
+   
+   packet_verifier32 pktver32
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
+      .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int),
+      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+   // RX side
+   wire 	 rx_enable;
+
+   packet_generator32 pktgen32
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
+      .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int));
+
+   fifo_pacer rx_pacer
+     (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable),
+      .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int),
+      .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy),
+      .underrun(), .overrun(rx_overrun));
+   
+`endif //  `ifdef TIMED
+
+`ifdef DSP
+   wire [7:0] 	 WHOAMI = 0;
+   
+   wire [31:0] 	 debug_rx_dsp, vrc_debug, vrf_debug;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // DSP RX
+   wire [31:0] 	 sample_rx, sample_tx;
+   wire 	 strobe_rx, strobe_tx;
+   wire 	 rx1_dst_rdy, rx1_src_rdy;
+   wire [99:0] 	 rx1_data;
+   wire 	 run_rx;
+   wire [35:0] 	 vita_rx_data;
+   wire 	 vita_rx_src_rdy, vita_rx_dst_rdy;
+      
+   dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx
+     (.clk(wb_clk),.rst(wb_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0),
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .debug(debug_rx_dsp) );
+
+   vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .vita_time(vita_time), .overrun(rx_overrun),
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy),
+      .debug_rx(vrc_debug));
+
+   vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy),
+      .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy),
+      .fifo_occupied(), .fifo_full(), .fifo_empty(),
+      .debug_rx(vrf_debug) );
+   
+   fifo36_mux #(.prio(0)) mux_err_stream
+     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+      .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy),
+      .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
+      .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+   
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // DSP TX
+
+   wire [15:0] 	 tx_i_int, tx_q_int;
+   wire 	 run_tx;
+   
+   vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
+		   .REPORT_ERROR(1), .PROT_ENG_FLAGS(0)) 
+   vita_tx_chain
+     (.clk(wb_clk), .reset(wb_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .vita_time(vita_time),
+      .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
+      .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
+      .dac_a(tx_i_int),.dac_b(tx_q_int),
+      .underrun(underrun), .run(run_tx),
+      .debug(debug_vt));
+   
+   assign tx_i = tx_i_int[15:2];
+   assign tx_q = tx_q_int[15:2];
+   
+`else // !`ifdef DSP
+   // Dummy DSP signal generator for test purposes
+   wire [23:0] 	 tx_i_int, tx_q_int;
+   wire [23:0] 	 freq = {reg_test,8'd0};
+   reg [23:0] 	 phase;
+   
+   always @(posedge wb_clk)
+     phase <= phase + freq;
+   
+   cordic_z24 #(.bitwidth(24)) tx_cordic
+     (.clock(wb_clk), .reset(wb_rst), .enable(1),
+      .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo());
+
+   assign tx_i = tx_i_int[23:10];
+   assign tx_q = tx_q_int[23:10];
+`endif // !`ifdef DSP
+      
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Wishbone Intercon, single master
+   wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,
+		 s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso,
+		 s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso,
+		 sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso;
+   wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr;
+   wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr;
+   wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel;
+   wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel;
+   wire 	 s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack;
+   wire 	 s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack;
+   wire 	 s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb;
+   wire 	 s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb;
+   wire 	 s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc;
+   wire 	 s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc;
+   wire 	 s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we;
+   wire 	 s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we;
+   
+   wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4),
+		.s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF),
+		.s2_addr(4'h2), .s2_mask(4'hF),	.s3_addr(4'h3), .s3_mask(4'hF),
+		.s4_addr(4'h4), .s4_mask(4'hF),	.s5_addr(4'h5), .s5_mask(4'hF),
+		.s6_addr(4'h6), .s6_mask(4'hF),	.s7_addr(4'h7), .s7_mask(4'hF),
+		.s8_addr(4'h8), .s8_mask(4'hF),	.s9_addr(4'h9), .s9_mask(4'hF),
+		.sa_addr(4'ha), .sa_mask(4'hF),	.sb_addr(4'hb), .sb_mask(4'hF),
+		.sc_addr(4'hc), .sc_mask(4'hF),	.sd_addr(4'hd), .sd_mask(4'hF),
+		.se_addr(4'he), .se_mask(4'hF),	.sf_addr(4'hf), .sf_mask(4'hF))
+   wb_1master
+     (.clk_i(wb_clk),.rst_i(wb_rst),       
+      .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi),
+      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+      .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+      .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
+      .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+      .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
+      .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+      .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
+      .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+      .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
+      .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+      .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
+      .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+      .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
+      .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+      .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
+      .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+      .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
+      .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
+      .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
+      .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
+      .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
+      .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
+      .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
+      .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
+      .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
+      .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
+      .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
+      .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
+      .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
+      .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
+      .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
+      .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
+      .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) );
+
+   assign s7_ack = 0;
+   assign s8_ack = 0;   assign s9_ack = 0;   assign sa_ack = 0;   assign sb_ack = 0;
+   assign sc_ack = 0;   assign sd_ack = 0;   assign se_ack = 0;   assign sf_ack = 0;
+
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Slave 0, Misc LEDs, Switches, controls
+   
+   localparam REG_LEDS = 7'd0;         // out
+   localparam REG_SWITCHES = 7'd2;     // in
+   localparam REG_CGEN_CTRL = 7'd4;    // out
+   localparam REG_CGEN_ST = 7'd6;      // in
+   localparam REG_TEST = 7'd8;         // out
+   localparam REG_RX_FRAMELEN = 7'd10; // in
+   localparam REG_TX_FRAMELEN = 7'd12; // out
+   localparam REG_XFER_RATE = 7'd14;   // out
+   localparam REG_COMPAT = 7'd16;      // in
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       begin
+	  reg_leds <= 0;
+	  reg_cgen_ctrl <= 2'b11;
+	  reg_test <= 0;
+	  tx_frame_len <= 0;
+	  xfer_rate <= 0;
+       end
+     else
+       if(s0_cyc & s0_stb & s0_we) 
+	 case(s0_adr[6:0])
+	   REG_LEDS :
+	     reg_leds <= s0_dat_mosi;
+	   REG_CGEN_CTRL :
+	     reg_cgen_ctrl <= s0_dat_mosi;
+	   REG_TEST :
+	     reg_test <= s0_dat_mosi;
+	   REG_TX_FRAMELEN :
+	     tx_frame_len <= s0_dat_mosi;
+	   REG_XFER_RATE :
+	     xfer_rate <= s0_dat_mosi;
+	 endcase // case (s0_adr[6:0])
+
+   assign tx_enable = xfer_rate[15];
+   assign rx_enable = xfer_rate[14];
+   assign rate = xfer_rate[7:0];
+   
+   assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]};
+   assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
+   
+   assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : 
+			(s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } :
+			(s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
+			(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
+			(s0_adr[6:0] == REG_TEST) ? reg_test :
+			(s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len :
+			(s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } :
+			16'hBEEF;
+   
+   assign s0_ack = s0_stb & s0_cyc;
+
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Slave 1, UART
+   //    depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock
+   
+   simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart 
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack),
+      .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso),
+      .rx_int_o(),.tx_int_o(),
+      .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o());
+
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Slave 2, SPI
+
+   spi_top16 shared_spi
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi),
+      .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
+      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(),
+      .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) );
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Slave 3, I2C
+
+   wire 	scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o;
+   i2c_master_top #(.ARST_LVL(1)) i2c 
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
+      .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]),
+      .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+      .wb_ack_o(s3_ack),.wb_inta_o(),
+      .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+      .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+   assign 	 s3_dat_miso[15:8] = 8'd0;
+
+   // I2C -- Don't use external transistors for open drain, the FPGA implements this
+   IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o));
+   IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+   // /////////////////////////////////////////////////////////////////////////
+   // GPIOs -- Slave #4
+
+   wire [31:0] 	atr_lines;
+   wire [31:0] 	debug_gpio_0, debug_gpio_1;
+   
+   nsgpio16LE 
+     nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst),
+		.cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
+		.dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack),
+		.atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+		.gpio( {io_tx,io_rx} ) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Settings Bus -- Slave #5
+
+   // only have 32 regs, 32 bits each with current setup...
+   settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi),
+      .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack),
+      .strobe(set_stb),.addr(set_addr),.data(set_data) );
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // ATR Controller -- Slave #6
+
+   atr_controller16 atr_controller16
+     (.clk_i(wb_clk), .rst_i(wb_rst),
+      .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso),
+      .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack),
+      .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines));
+
+
+   // /////////////////////////////////////////////////////////////////////////
+   // VITA Timing
+
+   time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit
+     (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
+   
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Debug circuitry
+
+   assign debug_clk = { EM_CLK, clk_fpga };
+
+   assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun },
+		    { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int },
+		    { EM_D } };
+
+   assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, 
+			   {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} };
+
+   assign debug_gpio_1 = debug_vt;
+   
+/*   
+   assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy},
+			   {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy},
+			   {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0},
+			   {2'b0, bus_error, debug_gpmc[4:0] },
+			   {misc_gpio[7:0]} };
+  */ 
+endmodule // u1e_core
diff --git a/fpga/usrp2/top/u1e_ethdebug/.gitignore b/fpga/usrp2/top/u1e_ethdebug/.gitignore
new file mode 100644
index 000000000..8d872713e
--- /dev/null
+++ b/fpga/usrp2/top/u1e_ethdebug/.gitignore
@@ -0,0 +1,6 @@
+*~
+build
+*.log
+*.cmd
+tb_u1e
+*.lxt
diff --git a/fpga/usrp2/top/u1e_ethdebug/Makefile b/fpga/usrp2/top/u1e_ethdebug/Makefile
new file mode 100644
index 000000000..751b52970
--- /dev/null
+++ b/fpga/usrp2/top/u1e_ethdebug/Makefile
@@ -0,0 +1,83 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u1e
+BUILD_DIR = $(abspath build$(ISE))
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+u1e.v \
+u1e.ucf
+
+SOURCES = $(abspath $(TOP_SRCS))
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/u1e_ethdebug/u1e.ucf b/fpga/usrp2/top/u1e_ethdebug/u1e.ucf
new file mode 100644
index 000000000..d6a2ea4ed
--- /dev/null
+++ b/fpga/usrp2/top/u1e_ethdebug/u1e.ucf
@@ -0,0 +1,88 @@
+
+## GPMC
+NET "EM_D<15>"  LOC = "D13"  ;
+NET "EM_D<14>"  LOC = "D15"  ;
+NET "EM_D<13>"  LOC = "C16"  ;
+NET "EM_D<12>"  LOC = "B20"  ;
+NET "EM_D<11>"  LOC = "A19"  ;
+NET "EM_D<10>"  LOC = "A17"  ;
+NET "EM_D<9>"  LOC = "E15"  ;
+NET "EM_D<8>"  LOC = "F15"  ;
+NET "EM_D<7>"  LOC = "E16"  ;
+NET "EM_D<6>"  LOC = "F16"  ;
+NET "EM_D<5>"  LOC = "B17"  ;
+NET "EM_D<4>"  LOC = "C17"  ;
+NET "EM_D<3>"  LOC = "B19"  ;
+NET "EM_D<2>"  LOC = "D19"  ;
+NET "EM_D<1>"  LOC = "C19"  ;
+NET "EM_D<0>"  LOC = "A20"  ;
+
+NET "EM_A<10>"  LOC = "C14"  ;
+NET "EM_A<9>"  LOC = "C10"  ;
+NET "EM_A<8>"  LOC = "C5"  ;
+NET "EM_A<7>"  LOC = "A18"  ;
+NET "EM_A<6>"  LOC = "A15"  ;
+NET "EM_A<5>"  LOC = "A12"  ;
+NET "EM_A<4>"  LOC = "A10"  ;
+NET "EM_A<3>"  LOC = "E7"  ;
+NET "EM_A<2>"  LOC = "A7"  ;
+NET "EM_A<1>"  LOC = "C15"  ;
+
+NET "EM_NCS6"  LOC = "E17"  ;
+NET "EM_NCS5"  LOC = "E10"  ;
+NET "EM_NCS4"  LOC = "E6"  ;
+#NET "EM_NCS1"  LOC = "D18"  ;
+#NET "EM_NCS0"  LOC = "D17"  ;
+
+NET "EM_CLK"  LOC = "F11"  ;
+NET "EM_WAIT0"  LOC = "F14"  ;
+#NET "EM_NBE<1>"  LOC = "D14"  ;
+#NET "EM_NBE<0>"  LOC = "A13"  ;
+NET "EM_NWE"  LOC = "B13"  ;
+NET "EM_NOE"  LOC = "A14"  ;
+NET "EM_NADV_ALE"  LOC = "B15"  ;
+#NET "EM_NWP"  LOC = "F13"  ;
+NET "overo_gpio64"  LOC = "A4"  ;  # nRESET
+NET "overo_gpio176"  LOC = "B4"  ;  # IRQ
+
+## Debug pins
+NET "debug_led<3>"  LOC = "Y15"  ;
+NET "debug_led<2>"  LOC = "K16"  ;
+NET "debug_led<1>"  LOC = "J17"  ;
+NET "debug_led<0>"  LOC = "H22"  ;
+NET "debug<0>"  LOC = "G22"  ;
+NET "debug<1>"  LOC = "H17"  ;
+NET "debug<2>"  LOC = "H18"  ;
+NET "debug<3>"  LOC = "K20"  ;
+NET "debug<4>"  LOC = "J20"  ;
+NET "debug<5>"  LOC = "K19"  ;
+NET "debug<6>"  LOC = "K18"  ;
+NET "debug<7>"  LOC = "L22"  ;
+NET "debug<8>"  LOC = "K22"  ;
+NET "debug<9>"  LOC = "N22"  ;
+NET "debug<10>"  LOC = "M22"  ;
+NET "debug<11>"  LOC = "N20"  ;
+NET "debug<12>"  LOC = "N19"  ;
+NET "debug<13>"  LOC = "R22"  ;
+NET "debug<14>"  LOC = "P22"  ;
+NET "debug<15>"  LOC = "N17"  ;
+NET "debug<16>"  LOC = "P16"  ;
+NET "debug<17>"  LOC = "U22"  ;
+NET "debug<18>"  LOC = "P19"  ;
+NET "debug<19>"  LOC = "R18"  ;
+NET "debug<20>"  LOC = "U20"  ;
+NET "debug<21>"  LOC = "T20"  ;
+NET "debug<22>"  LOC = "R19"  ;
+NET "debug<23>"  LOC = "R20"  ;
+NET "debug<24>"  LOC = "W22"  ;
+NET "debug<25>"  LOC = "Y22"  ;
+NET "debug<26>"  LOC = "T18"  ;
+NET "debug<27>"  LOC = "T17"  ;
+NET "debug<28>"  LOC = "W19"  ;
+NET "debug<29>"  LOC = "V20"  ;
+NET "debug<30>"  LOC = "Y21"  ;
+NET "debug<31>"  LOC = "AA22"  ;
+NET "debug_clk<0>"  LOC = "N18"  ;
+NET "debug_clk<1>"  LOC = "M17"  ;
+
+NET "debug_pb"  LOC = "C22"  ;
diff --git a/fpga/usrp2/top/u1e_ethdebug/u1e.v b/fpga/usrp2/top/u1e_ethdebug/u1e.v
new file mode 100644
index 000000000..2a543a313
--- /dev/null
+++ b/fpga/usrp2/top/u1e_ethdebug/u1e.v
@@ -0,0 +1,28 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+//`define DCM 1
+
+module u1e
+  (output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+   input debug_pb,
+
+   // GPMC
+   input EM_CLK, input [15:0] EM_D, input [10:1] EM_A,
+   input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, input EM_NWE, input EM_NOE,
+   input EM_NADV_ALE,
+
+   input overo_gpio64, input overo_gpio176
+   );
+
+   assign debug_clk = {EM_CLK, EM_NADV_ALE};
+
+   assign debug_led = {1'b0, EM_A[9], EM_A[8], debug_pb};
+
+   assign debug = { {overo_gpio64, overo_gpio176, EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE },
+		    { EM_A[10], EM_A[7:1] },
+		    { EM_D[15:8] },
+		    { EM_D[7:0] } };
+   
+
+endmodule // u1e
diff --git a/fpga/usrp2/top/u1e_passthru/.gitignore b/fpga/usrp2/top/u1e_passthru/.gitignore
new file mode 100644
index 000000000..1b2211df0
--- /dev/null
+++ b/fpga/usrp2/top/u1e_passthru/.gitignore
@@ -0,0 +1 @@
+build*
diff --git a/fpga/usrp2/top/u1e_passthru/Makefile b/fpga/usrp2/top/u1e_passthru/Makefile
new file mode 100644
index 000000000..d1950629b
--- /dev/null
+++ b/fpga/usrp2/top/u1e_passthru/Makefile
@@ -0,0 +1,99 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = passthru
+BUILD_DIR = $(abspath build$(ISE))
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
+include ../../gpmc/Makefile.srcs
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+passthru.v \
+passthru.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(GPMC_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/u1e_passthru/passthru.ucf b/fpga/usrp2/top/u1e_passthru/passthru.ucf
new file mode 100644
index 000000000..64e6f0440
--- /dev/null
+++ b/fpga/usrp2/top/u1e_passthru/passthru.ucf
@@ -0,0 +1,6 @@
+NET "overo_gpio145"  LOC = "C7"  ;
+NET "cgen_mosi"  LOC = "E22"  ;
+NET "cgen_sclk"  LOC = "J19"  ;
+NET "cgen_sen_b"  LOC = "H20"  ;
+NET "fpga_cfg_din"  LOC = "W17"  ;
+NET "fpga_cfg_cclk"  LOC = "V17"  ;
diff --git a/fpga/usrp2/top/u1e_passthru/passthru.v b/fpga/usrp2/top/u1e_passthru/passthru.v
new file mode 100644
index 000000000..12e4db017
--- /dev/null
+++ b/fpga/usrp2/top/u1e_passthru/passthru.v
@@ -0,0 +1,18 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module passthru
+  (input overo_gpio145,
+   output cgen_sclk,
+   output cgen_sen_b,
+   output cgen_mosi,
+   input fpga_cfg_din,
+   input fpga_cfg_cclk
+   );
+   
+   assign cgen_sclk = fpga_cfg_cclk;
+   assign cgen_sen_b = overo_gpio145;
+   assign cgen_mosi = fpga_cfg_din;
+   
+   
+endmodule // passthru
diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v
old mode 100755
new mode 100644
diff --git a/fpga/usrp2/top/u2_rev3/u2_core_udp.v b/fpga/usrp2/top/u2_rev3/u2_core_udp.v
index b47e7e311..9e62ee1cc 100644
--- a/fpga/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/fpga/usrp2/top/u2_rev3/u2_core_udp.v
@@ -125,7 +125,6 @@ module u2_core
    output [18:0] RAM_A,
    output RAM_CE1n,
    output RAM_CENn,
- //  output RAM_CLK,
    output RAM_WEn,
    output RAM_OEn,
    output RAM_LDn,
@@ -162,6 +161,7 @@ module u2_core
    
    wire 	ram_loader_done;
    wire 	ram_loader_rst, wb_rst, dsp_rst;
+   assign dsp_rst = wb_rst;
 
    wire [31:0] 	status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
    wire 	bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int;
@@ -561,14 +561,6 @@ module u2_core
    // Master Timer, Slave #9
 
    // No longer used, replaced with simple_timer below
-   /*
-   wire [31:0] 	 master_time;
-   timer timer
-     (.wb_clk_i(wb_clk),.rst_i(wb_rst),
-      .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
-      .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
-      .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
-    */
    assign s9_ack = 0;
    
    // /////////////////////////////////////////////////////////////////////////
@@ -632,9 +624,15 @@ module u2_core
       .debug(debug_rx_dsp) );
 
    wire [31:0] 	 vrc_debug;
+   wire 	 clear_rx;
    
+   setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
+      .out(),.changed(clear_rx));
+
    vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .vita_time(vita_time), .overrun(overrun),
       .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
@@ -644,7 +642,7 @@ module u2_core
    wire [3:0] 	 vita_state;
    
    vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy),
       .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy),
@@ -652,7 +650,7 @@ module u2_core
       .debug_rx(vita_state) );
 
    fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
       .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
       .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
 
@@ -662,23 +660,17 @@ module u2_core
    wire [35:0] 	 tx_data;
    wire 	 tx_src_rdy, tx_dst_rdy;
    wire [31:0] 	 debug_vt;
+   wire 	 clear_tx;
 
-   // FIFO cascade draws from buffer pool, feeds vita tx deframer
-/* -----\/----- EXCLUDED -----\/-----
-   
-   fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i),
-      .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) );
- -----/\----- EXCLUDED -----/\----- */
+   setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(clear_tx));
 
    ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) 
      ext_fifo_i1
-       (
-	.int_clk(dsp_clk),
+       (.int_clk(dsp_clk),
 	.ext_clk(clk_to_mac),
-//	.ext_clk(wb_clk),
-	.rst(dsp_rst),
+	.rst(dsp_rst | clear_tx),
 	.RAM_D_pi(RAM_D_pi),
 	.RAM_D_po(RAM_D_po),
 	.RAM_D_poe(RAM_D_poe),
@@ -688,17 +680,14 @@ module u2_core
 	.RAM_LDn(RAM_LDn),
 	.RAM_OEn(RAM_OEn),
 	.RAM_CE1n(RAM_CE1n),
-//	.datain({rd1_flags,rd1_dat}),
 	.datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}),
-	.src_rdy_i(rd1_ready_o),               // WRITE
-	.dst_rdy_o(rd1_ready_i),               // not FULL
-//	.dataout(tx_data),
+	.src_rdy_i(rd1_ready_o),
+	.dst_rdy_o(rd1_ready_i),
 	.dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}),
-	.src_rdy_o(tx_src_rdy),               // not EMPTY
+	.src_rdy_o(tx_src_rdy),
 	.dst_rdy_i(tx_dst_rdy),
 	.debug(debug_extfifo),
-	.debug2(debug_extfifo2)
-	);
+	.debug2(debug_extfifo2) );
 
    vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
 		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
@@ -713,8 +702,6 @@ module u2_core
       .underrun(underrun), .run(run_tx),
       .debug(debug_vt));
    
-   assign dsp_rst = wb_rst;
-
    // ///////////////////////////////////////////////////////////////////////////////////
    // SERDES
 
@@ -728,63 +715,7 @@ module u2_core
       .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
       .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
 
-   // ///////////////////////////////////////////////////////////////////////////////////
-   // External RAM Interface
-
-   /*
-   localparam PAGE_SIZE = 10;  // PAGE SIZE is in bytes, 10 = 1024 bytes
-
-   wire [15:0] bus2ram, ram2bus;
-   wire [15:0] bridge_adr;
-   wire [1:0]  bridge_sel;
-   wire        bridge_stb, bridge_cyc, bridge_we, bridge_ack;
-   
-   wire [19:0] page;
-   wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]};
-   setting_reg #(.my_addr(6),.width(20)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-				       .in(set_data),.out(page),.changed());
-
-   wb_bridge_16_32 bridge
-     (.wb_clk(wb_clk),.wb_rst(wb_rst),
-      .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel),
-      .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack),
-      .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel),
-      .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack));
-
-   wb_zbt16_b wb_zbt16_b
-     (.clk(wb_clk),.rst(wb_rst),
-      .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel),
-      .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we),
-      .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn),
-      .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
-      .sram_mode(),.sram_zz() );
-
-   assign      RAM_CE1n = 0;
-   assign      RAM_D[17:16] = 2'bzz;
-/* -----\/----- EXCLUDED -----\/-----
-   *-/
-
-   test_sram_if test_sram_if_i1
-     (
-    //  .clk(wb_clk),
-      .clk(clk_to_mac),
-      .rst(wb_rst),
-      .RAM_D_pi(RAM_D_pi),
-      .RAM_D_po(RAM_D_po),
-      .RAM_D_poe(RAM_D_poe),
-      .RAM_A(RAM_A),
-      .RAM_WEn(RAM_WEn),
-      .RAM_CENn(RAM_CENn),
-      .RAM_LDn(RAM_LDn),
-      .RAM_OEn(RAM_OEn),
-      .RAM_CE1n(RAM_CE1n),
-      .correct()
-      );
- -----/\----- EXCLUDED -----/\----- */
-   
-   //assign RAM_CLK = wb_clk;
-   //assign RAM_CLK = clk_to_mac;
-   
+   assign RAM_CLK = clk_to_mac;
    
    // /////////////////////////////////////////////////////////////////////////
    // VITA Timing
@@ -802,140 +733,3 @@ module u2_core
    assign debug_gpio_1 = 32'd0;
    
 endmodule // u2_core
-
-/*
-   // FIFO Level Debugging
-   reg [31:0]  host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo;
-   
-   always @(posedge dsp_clk)
-     serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]},
-			     {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
-
-   always @(posedge dsp_clk)
-     dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]},
-			     {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
-   
-   always @(posedge dsp_clk)
-     host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]},
-			   {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
-   
-   always @(posedge dsp_clk)
-     dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]},
-			   {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
-   
-   always @(posedge dsp_clk)
-     eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]},
-			{eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
-   
-   assign  debug_clk[0]  = GMII_RX_CLK; // wb_clk;
-   assign  debug_clk[1]  = dsp_clk;
-*/
-/*
- 
-   wire        mdio_cpy  = MDIO;
-   assign  debug 	 = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] },
-			     { s6_adr[15:8] },
-			     { s6_adr[7:0] },
-			     { 6'd0, mdio_cpy, MDC } };
-
-   assign debug 	 = { { GMII_TXD },
-			     { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK },
-			     { wr2_flags, rd2_flags },
-			     { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
-   assign debug 	 = { { GMII_RXD },
-			     { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK },
-			     { wr2_flags, rd2_flags },
-			     { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
-
-//   assign debug = debug_udp;
-  // assign debug = vrc_debug;
-/*
-  assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state},
-			   {2'd0, rx_dst_rdy, rx_src_rdy, rx_data[99:96]},
-			   {run_rx_d1, run_rx, strobe_rx, overrun, wr1_flags[3:0]} , 
-			   {wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}};
-*/
-//   assign debug_gpio_1 = {vita_time[63:32] };
-/*   
-   assign debug_gpio_1 = { { tx_f19_data[15:8] },
-			   { tx_f19_data[7:0] },
-			   { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] },
-			   { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } };
- */  
-   
-//   wire        debug_mux;
-//   setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-//					.in(set_data),.out(debug_mux),.changed());
-
-//assign     debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
-//assign     debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo;
-   
-//assign      debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
-//		{run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
-
-//assign      debug = debug_tx_dsp;
-//assign      debug = debug_serdes0;
-
-//assign      debug_gpio_0 = 0; //debug_serdes0;
-//assign      debug_gpio_1 = 0; //debug_serdes1;
-
-//   assign      debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success},
-//	      {8'b0},
-//      {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done },
-//    {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} };
-
-//assign      debug = {dac_a,dac_b};
-
-/*
- assign      debug = {{ram_loader_done, takeover, 6'd0},
- {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi},
- {8'd0},
- {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */
-
-/*assign      debug = host_to_dsp_fifo;
- assign      debug_gpio_0 = eth_mac_debug;
- assign      debug_gpio_1 = 0;
- */
-// Assign various commonly used debug buses.
-/*
- wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
- irq[7:0],
- GMII_RXD,
- GMII_TXD};
- 
- wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
-   
-   wire [31:0] debug_time =  {uart_tx_o, 7'b0,
-			      irq[7:0],
-			      6'b0, GMII_RX_DV, GMII_TX_EN,
-			      4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int};
-
-   wire [31:0] debug_irq =  {uart_tx_o, iwb_adr, iwb_ack,
-			     irq[7:0],
-			     proc_int,  7'b0 };
-
-   wire [31:0] debug_eth = 
-	       {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
-		{8'd0},
-		{8'd0},
-		{GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} };
-
-   assign      debug_serdes0 = { { rd0_dat[7:0] },
-				 { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done },
-				 { ser_t[15:8] },
-				 { ser_t[7:0] } };
-
-   assign      debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write},
-				 { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en },
-				 { ser_r[15:8] },
-				 { ser_r[7:0] } };
-       
-   assign      debug_gpio_1 = {uart_tx_o,7'd0,
-			       3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error,
-			       debug_txc[15:0]};
-   assign      debug_gpio_1 = debug_rx;
-   assign      debug_gpio_1 = debug_serdes1;
-   assign      debug_gpio_1 = debug_eth;
-      
-    */
-      
diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf
index deaeecb53..6e0caedd5 100644
--- a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf
+++ b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf
@@ -74,49 +74,49 @@ NET "MDC"  LOC = "V18"  ;
 NET "PHY_INTn"  LOC = "AB13"  ; 
 NET "PHY_RESETn"  LOC = "AA19"  ; 
 NET "PHY_CLK"  LOC = "V15"  ; 
-NET "RAM_D[0]"  LOC = "N20" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
-NET "RAM_D[1]"  LOC = "N21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
-NET "RAM_D[2]"  LOC = "N22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
-NET "RAM_D[3]"  LOC = "M17" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
-NET "RAM_D[4]"  LOC = "M18" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
-NET "RAM_D[5]"  LOC = "M19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
-NET "RAM_D[6]"  LOC = "M20" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
-NET "RAM_D[7]"  LOC = "M21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
-NET "RAM_D[8]"  LOC = "M22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
-NET "RAM_D[9]"  LOC = "Y22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
-NET "RAM_D[10]"  LOC = "Y21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
-NET "RAM_D[11]"  LOC = "Y20" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_D[12]"  LOC = "Y19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_D[13]"  LOC = "W22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_D[14]"  LOC = "W21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_D[15]"  LOC = "W20" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_D[16]"  LOC = "W19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_D[17]"  LOC = "V22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[0]"  LOC = "U21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[1]"  LOC = "T19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[2]"  LOC = "V21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[3]"  LOC = "V20" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[4]"  LOC = "T20" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[5]"  LOC = "T21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[6]"  LOC = "T22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[7]"  LOC = "T18" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[8]"  LOC = "R18" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[9]"  LOC = "P19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[10]"  LOC = "P21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[11]"  LOC = "P22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[12]"  LOC = "N19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[13]"  LOC = "N17" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[14]"  LOC = "N18" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[15]"  LOC = "T17" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[16]"  LOC = "U19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[17]"  LOC = "U18" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
-NET "RAM_A[18]"  LOC = "V19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
-NET "RAM_CE1n"  LOC = "U20" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ; 
-NET "RAM_CENn"  LOC = "P18" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ; 
-NET "RAM_CLK"  LOC = "P17" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ; 
-NET "RAM_WEn"  LOC = "R22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ; 
-NET "RAM_OEn"  LOC = "R21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ; 
-NET "RAM_LDn"  LOC = "R19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ; 
+NET "RAM_D[0]"  LOC = "N20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[1]"  LOC = "N21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[2]"  LOC = "N22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[3]"  LOC = "M17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[4]"  LOC = "M18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[5]"  LOC = "M19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[6]"  LOC = "M20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[7]"  LOC = "M21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[8]"  LOC = "M22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[9]"  LOC = "Y22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[10]"  LOC = "Y21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[11]"  LOC = "Y20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[12]"  LOC = "Y19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[13]"  LOC = "W22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[14]"  LOC = "W21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[15]"  LOC = "W20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[16]"  LOC = "W19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[17]"  LOC = "V22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[0]"  LOC = "U21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[1]"  LOC = "T19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[2]"  LOC = "V21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[3]"  LOC = "V20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[4]"  LOC = "T20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[5]"  LOC = "T21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[6]"  LOC = "T22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[7]"  LOC = "T18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[8]"  LOC = "R18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[9]"  LOC = "P19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[10]"  LOC = "P21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[11]"  LOC = "P22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[12]"  LOC = "N19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[13]"  LOC = "N17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[14]"  LOC = "N18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[15]"  LOC = "T17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[16]"  LOC = "U19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[17]"  LOC = "U18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[18]"  LOC = "V19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_CE1n"  LOC = "U20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_CENn"  LOC = "P18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_CLK"  LOC = "P17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_WEn"  LOC = "R22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_OEn"  LOC = "R21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_LDn"  LOC = "R19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
 NET "ser_enable"  LOC = "W11"  ; 
 NET "ser_prbsen"  LOC = "AA3"  ; 
 NET "ser_loopen"  LOC = "Y4"  ; 
diff --git a/fpga/usrp2/top/u2plus/.gitignore b/fpga/usrp2/top/u2plus/.gitignore
new file mode 100644
index 000000000..1b2211df0
--- /dev/null
+++ b/fpga/usrp2/top/u2plus/.gitignore
@@ -0,0 +1 @@
+build*
diff --git a/fpga/usrp2/top/u2plus/Makefile b/fpga/usrp2/top/u2plus/Makefile
new file mode 100644
index 000000000..c38bd3ec1
--- /dev/null
+++ b/fpga/usrp2/top/u2plus/Makefile
@@ -0,0 +1,99 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u2plus
+BUILD_DIR = $(abspath build$(ISE))
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
+include ../../extramfifo/Makefile.srcs
+
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd3400a \
+package fg676 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+u2plus_core.v \
+u2plus.v \
+u2plus.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/u2plus/bootloader.rmi b/fpga/usrp2/top/u2plus/bootloader.rmi
new file mode 100644
index 000000000..7c15699db
--- /dev/null
+++ b/fpga/usrp2/top/u2plus/bootloader.rmi
@@ -0,0 +1,245 @@
+defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b808175c_00000000_b8080050;
+defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8081764;
+defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401e70_31a01e98_00000000_00000000_00000000_00000000;
+defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f40668_80000000_b9f400cc;
+defparam bootram.RAM0.INIT_04=256'he8830000_e8601e78_80000000_99fc2000_f8601e78_b8000044_bc030014_f9e10000;
+defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a01e8c_bc030010_30600000_b0000000_30630004_be24ffec;
+defparam bootram.RAM0.INIT_06=256'h30600000_b0000000_3021001c_b60f0008_e9e10000_f060f800_b0000000_30600001;
+defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a01e8c_f9e10000_3021ffe4;
+defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01e90_bc030014_30800000_b0000000_e8601e90;
+defparam bootram.RAM0.INIT_09=256'h06463800_20e01e98_20c01e98_f9e10000_2021ffec_3021001c_b60f0008_e9e10000;
+defparam bootram.RAM0.INIT_0A=256'hb0000000_20c0f800_b0000000_bc92fff4_06463800_20c60004_f8060000_bc720014;
+defparam bootram.RAM0.INIT_0B=256'hb9f415f8_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f82c;
+defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f401c8_20e00000_20c00000_80000000_b9f41778_80000000;
+defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f415c4_80000000_b9f41780;
+defparam bootram.RAM0.INIT_0E=256'he9e10000_f9610004_fa410010_95608001_fa21000c_f9610008_f9e10000_3021ffec;
+defparam bootram.RAM0.INIT_0F=256'hbc050018_30210014_b62e0000_ea410010_ea21000c_e9610008_940bc001_e9610004;
+defparam bootram.RAM0.INIT_10=256'h3021ff2c_80000000_b60f0008_bc32fff4_16432800_30630001_80000000_10600000;
+defparam bootram.RAM0.INIT_11=256'hb9f4062c_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c;
+defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a01984_10b30000_b9f40da4_10d60000_10b30000;
+defparam bootram.RAM0.INIT_13=256'h30a01984_bc120040_aa430001_30a0194c_e061001c_10a30000_be520034_16439003;
+defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f406c0_b800ffb4_80000000_b9f406cc;
+defparam bootram.RAM0.INIT_15=256'h80000000_b9f40694_b800ff88_80000000_b9f406a0_30a0194c_80000000_b9f4155c;
+defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f40678_30a01950_80000000_b9f411e8_30a08000_b0000000;
+defparam bootram.RAM0.INIT_17=256'hbe030020_30a00050_31000001_30e1001c_30c000f7_f9e10000_a46500ff_3021ffe0;
+defparam bootram.RAM0.INIT_18=256'hb810ffe8_30210020_b60f0008_e9e10000_80000000_b9f40330_f081001c_3080005e;
+defparam bootram.RAM0.INIT_19=256'h31000001_b9f40280_f9e10000_30e1001c_30c000f7_30a00050_3021ffe0_308000dc;
+defparam bootram.RAM0.INIT_1A=256'h3021ffdc_30210020_b60f0008_6463001f_3063ffff_a863005e_e9e10000_e061001c;
+defparam bootram.RAM0.INIT_1B=256'h30a0a120_b0000007_9403c001_ac640002_94808001_fac10020_fa61001c_f9e10000;
+defparam bootram.RAM0.INIT_1C=256'hb9f40ea8_80000000_b9f4082c_f800200c_80000000_b9f4fe74_f860200c_306000ff;
+defparam bootram.RAM0.INIT_1D=256'h80000000_b9f4ff6c_80000000_b9f4059c_30a01988_80000000_b9f409ec_80000000;
+defparam bootram.RAM0.INIT_1E=256'h30a00000_b0000030_bc160100_bc130134_a6632000_e8603334_12c30000_be23017c;
+defparam bootram.RAM0.INIT_1F=256'hb0000000_80000000_b9f40558_30a01b04_12c30000_be030068_80000000_b9f41180;
+defparam bootram.RAM0.INIT_20=256'hb9f41094_30a08000_b0000000_30c07c00_b9f40e70_30a00000_b0000030_30e08000;
+defparam bootram.RAM0.INIT_21=256'he9e10000_30600001_10a00000_b9f41244_80000000_b9f40524_30a01b30_80000000;
+defparam bootram.RAM0.INIT_22=256'hb000003f_80000000_b9f404f8_30a01b6c_30210024_b60f0008_eac10020_ea61001c;
+defparam bootram.RAM0.INIT_23=256'h80000000_b9f404d4_30a019f8_12630000_be230024_80000000_b9f410fc_30a00000;
+defparam bootram.RAM0.INIT_24=256'h30a00000_b000003f_30e08000_b0000000_10730000_b810ffb4_80000000_b9f4fd9c;
+defparam bootram.RAM0.INIT_25=256'hb9f40490_30a019bc_80000000_b9f41000_30a08000_b0000000_30c07c00_b9f40ddc;
+defparam bootram.RAM0.INIT_26=256'h80000000_b9f40474_30a01a50_30600001_b810ff70_10b60000_b9f411b0_80000000;
+defparam bootram.RAM0.INIT_27=256'h80000000_b9f40454_30a01ab4_bc230098_80000000_b9f41000_30a00000_b0000018;
+defparam bootram.RAM0.INIT_28=256'h80000000_b9f41048_30a00000_b000003f_80000000_b9f40444_30a0199c_b800fed8;
+defparam bootram.RAM0.INIT_29=256'hb9f4fda4_b800fe9c_80000000_b9f4fcec_80000000_b9f40424_30a019f8_bc230028;
+defparam bootram.RAM0.INIT_2A=256'h30c07c00_b9f40d24_30a00000_b000003f_30e08000_b0000000_b800fe84_10a00000;
+defparam bootram.RAM0.INIT_2B=256'hb9f410f8_80000000_b9f403d8_30a019bc_80000000_b9f40f48_30a08000_b0000000;
+defparam bootram.RAM0.INIT_2C=256'hb9f4fc60_30a00001_b9f4fd4c_80000000_b9f403c0_30a01a7c_b800fe50_10b30000;
+defparam bootram.RAM0.INIT_2D=256'hfa610020_3021ffd4_b800ff40_80000000_b9f410c8_30a00000_b0000018_30a07530;
+defparam bootram.RAM0.INIT_2E=256'hfac10024_30e00001_30c1001c_12e70000_f0c1001c_fae10028_10b30000_a66500ff;
+defparam bootram.RAM0.INIT_2F=256'h10b30000_10f60000_10d70000_10830000_be030030_12c80000_b9f40898_f9e10000;
+defparam bootram.RAM0.INIT_30=256'h10640000_a8830001_6463001f_3063ffff_80000000_b9f407d0_30800001_be76001c;
+defparam bootram.RAM0.INIT_31=256'hfac10024_3021ffcc_3021002c_b60f0008_eae10028_eac10024_ea610020_e9e10000;
+defparam bootram.RAM0.INIT_32=256'hf9e10000_12c80000_12e70000_13250000_13060000_fb210030_fb01002c_fae10028;
+defparam bootram.RAM0.INIT_33=256'h32d6ffff_e0770000_f301001c_30e00002_be76005c_30c1001c_10b90000_fa610020;
+defparam bootram.RAM0.INIT_34=256'hbe33ffcc_32f70001_b9f4089c_30a0000a_12630000_33180001_b9f407f8_f061001d;
+defparam bootram.RAM0.INIT_35=256'heb210030_eb01002c_eae10028_eac10024_ea610020_e9e10000_10730000_10b90000;
+defparam bootram.RAM0.INIT_36=256'h80000000_b9f4f998_f9e10000_3021ffe4_30600001_b810ffe0_30210034_b60f0008;
+defparam bootram.RAM0.INIT_37=256'h12660000_fb21002c_fb010028_fae10024_fa61001c_3021ffd0_80000000_b60f0008;
+defparam bootram.RAM0.INIT_38=256'haa43ffff_12c00000_b810001c_f9e10000_fac10020_13260000_12e70000_13050000;
+defparam bootram.RAM0.INIT_39=256'h10960000_90630060_10b80000_b9f405ec_32730001_bcb2002c_16572001_bc120030;
+defparam bootram.RAM0.INIT_3A=256'he9e10000_10640000_f0130000_14999800_32d60001_be32ffd4_aa43000a_f0730000;
+defparam bootram.RAM0.INIT_3B=256'h3021ffd0_30210030_b60f0008_eb21002c_eb010028_eae10024_eac10020_ea61001c;
+defparam bootram.RAM0.INIT_3C=256'h13260000_12e70000_13050000_12660000_fb21002c_fb010028_fae10024_fa61001c;
+defparam bootram.RAM0.INIT_3D=256'hb9f4051c_32730001_bcb2002c_16572001_12c00000_b8100014_f9e10000_fac10020;
+defparam bootram.RAM0.INIT_3E=256'h14999800_32d60001_be32ffdc_aa43000a_f0730000_10960000_90630060_10b80000;
+defparam bootram.RAM0.INIT_3F=256'heb21002c_eb010028_eae10024_eac10020_ea61001c_e9e10000_10640000_f0130000;
+defparam bootram.RAM1.INIT_00=256'h12e60000_12c50000_fae10024_fac10020_fa61001c_3021ffd8_30210030_b60f0008;
+defparam bootram.RAM1.INIT_01=256'hbe32ffec_aa43000a_f0730000_90630060_10b60000_b9f404b0_12660000_f9e10000;
+defparam bootram.RAM1.INIT_02=256'heae10024_eac10020_ea61001c_e9e10000_10770000_f0130000_3273ffff_32730001;
+defparam bootram.RAM1.INIT_03=256'he9e10000_10a00000_b9f4ff94_f9e10000_3021ffe4_10c50000_30210028_b60f0008;
+defparam bootram.RAM1.INIT_04=256'hb60f0008_e9e10000_80000000_b9f40448_f9e10000_3021ffe4_3021001c_b60f0008;
+defparam bootram.RAM1.INIT_05=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ffdc_f9e10000_3021ffe4_3021001c;
+defparam bootram.RAM1.INIT_06=256'hbe060024_90c30060_12660000_e0660000_f9e10000_fac10020_fa61001c_3021ffdc;
+defparam bootram.RAM1.INIT_07=256'h10b60000_be26fff0_90c30060_e0730000_32730001_b9f40324_10b60000_12c50000;
+defparam bootram.RAM1.INIT_08=256'hfac1001c_3021ffe0_30210024_b60f0008_10600000_eac10020_ea61001c_e9e10000;
+defparam bootram.RAM1.INIT_09=256'heac1001c_e9e10000_30c0000a_b9f402dc_10b60000_12c50000_b9f4ff9c_f9e10000;
+defparam bootram.RAM1.INIT_0A=256'h10a00000_b9f4ffc0_f9e10000_3021ffe4_10c50000_30210020_b60f0008_10600000;
+defparam bootram.RAM1.INIT_0B=256'h10a00000_b9f4ff48_f9e10000_3021ffe4_10c50000_3021001c_b60f0008_e9e10000;
+defparam bootram.RAM1.INIT_0C=256'he9e10000_30c0000a_b9f40278_f9e10000_3021ffe4_3021001c_b60f0008_e9e10000;
+defparam bootram.RAM1.INIT_0D=256'hb9f40250_f9e10000_10a00000_12c50000_fac1001c_3021ffe0_3021001c_b60f0008;
+defparam bootram.RAM1.INIT_0E=256'hfac1001c_3021ffe0_30210020_b60f0008_eac1001c_e9e10000_10760000_10d60000;
+defparam bootram.RAM1.INIT_0F=256'h30210020_b60f0008_eac1001c_e9e10000_10760000_12c60000_b9f40228_f9e10000;
+defparam bootram.RAM1.INIT_10=256'h94e08001_3021001c_b60f0008_e9e10000_80000000_b9f401b8_f9e10000_3021ffe4;
+defparam bootram.RAM1.INIT_11=256'h80633000_84632000_84c62800_a866ffff_e880f81c_b0000000_9404c001_ac870002;
+defparam bootram.RAM1.INIT_12=256'h9404c001_80843800_ac840002_94808001_a4e70002_f860f81c_b0000000_f860200c;
+defparam bootram.RAM1.INIT_13=256'h88a52000_e880f81c_b0000000_9406c001_acc30002_94608001_80000000_b60f0008;
+defparam bootram.RAM1.INIT_14=256'h9404c001_80841800_ac840002_94808001_a4630002_f8a0f81c_b0000000_f8a0200c;
+defparam bootram.RAM1.INIT_15=256'ha866ffff_e880f820_b0000000_9404c001_ac870002_94e08001_80000000_b60f0008;
+defparam bootram.RAM1.INIT_16=256'h94808001_a4e70002_f860f820_b0000000_f8602020_80633000_84632000_84c62800;
+defparam bootram.RAM1.INIT_17=256'hfae10024_fa61001c_3021ffd4_80000000_b60f0008_9404c001_80843800_ac840002;
+defparam bootram.RAM1.INIT_18=256'hbe060040_90c30060_13050000_12e60000_e0660000_fac10020_f9e10000_fb010028;
+defparam bootram.RAM1.INIT_19=256'h10730000_be120028_16569800_32c70001_b8100014_32600001_be670038_12660000;
+defparam bootram.RAM1.INIT_1A=256'h10730000_3273ffff_32730001_be26ffe4_90c30060_c0779800_10b80000_b9f400cc;
+defparam bootram.RAM1.INIT_1B=256'h3021ffe4_3021002c_b60f0008_eb010028_eae10024_eac10020_ea61001c_e9e10000;
+defparam bootram.RAM1.INIT_1C=256'hf0c51e7c_3021001c_b60f0008_e9e10000_30c0000a_b9f40084_f9e10000_10a00000;
+defparam bootram.RAM1.INIT_1D=256'h80000000_b60f0008_f8653700_64a50405_e4661bac_10c63000_80000000_b60f0008;
+defparam bootram.RAM1.INIT_1E=256'h90c60060_b9f4ffc4_10b30000_e0d31e7c_12600000_f9e10000_fa61001c_3021ffe0;
+defparam bootram.RAM1.INIT_1F=256'he9e10000_bc32ffd8_aa530003_90c60060_b9f4ffbc_32730001_10b30000_e0d31ba8;
+defparam bootram.RAM1.INIT_20=256'h12c60000_f9e10000_fac10020_fa61001c_3021ffdc_30210020_b60f0008_ea61001c;
+defparam bootram.RAM1.INIT_21=256'hfac5000c_bc03fffc_e8650004_30a33700_64730405_12650000_be120030_aa46000a;
+defparam bootram.RAM1.INIT_22=256'hbc32ffd0_aa430001_e0651e7c_30210024_b60f0008_eac10020_ea61001c_e9e10000;
+defparam bootram.RAM1.INIT_23=256'hf9e10000_fac10020_fa61001c_3021ffdc_64730405_b810ffc8_30c0000d_b9f4ffac;
+defparam bootram.RAM1.INIT_24=256'hbc040008_e8830004_30633700_64730405_12650000_be120030_aa46000a_12c60000;
+defparam bootram.RAM1.INIT_25=256'haa430001_e0651e7c_30210024_b60f0008_eac10020_ea61001c_e9e10000_fac3000c;
+defparam bootram.RAM1.INIT_26=256'h30a53700_64a50405_64730405_b810ffc4_80000000_b9f4ff44_30c0000d_be32ffd0;
+defparam bootram.RAM1.INIT_27=256'he8650008_30a53700_64a50405_80000000_b60f0008_e8650010_bc03fffc_e8650008;
+defparam bootram.RAM1.INIT_28=256'h64a50405_80000000_b60f0008_90630060_be24fff8_e8850008_e8650010_bc030014;
+defparam bootram.RAM1.INIT_29=256'h32600001_be230040_e8760008_32c53700_fa61001c_f9e10000_fac10020_3021ffdc;
+defparam bootram.RAM1.INIT_2A=256'hbe03ffe8_e8760008_30a00001_b9f401e0_3060ffff_be120034_aa53012d_b8000010;
+defparam bootram.RAM1.INIT_2B=256'he9e10000_e8760010_3060ffff_be52000c_16539001_3240012b_3273ffff_32730001;
+defparam bootram.RAM1.INIT_2C=256'h32400004_a463000f_e8603324_f8003108_30210024_b60f0008_eac10020_ea61001c;
+defparam bootram.RAM1.INIT_2D=256'ha46300ff_64a30008_e4641bb8_10831800_30600004_10831800_beb20010_16439001;
+defparam bootram.RAM1.INIT_2E=256'ha4a500ff_be070088_80000000_b60f0008_f8603108_30600080_f8a03104_f8603100;
+defparam bootram.RAM1.INIT_2F=256'hf8803110_30800090_f860310c_a0630001_10652800_be23fff8_a4630040_e8603110;
+defparam bootram.RAM1.INIT_30=256'haa470001_10800000_be230058_a4630080_e8603110_bc23fff8_a4630002_e8603110;
+defparam bootram.RAM1.INIT_31=256'h30e7ffff_e860310c_bc23fff8_a4630002_e8603110_f8603110_30600020_be120038;
+defparam bootram.RAM1.INIT_32=256'h30600068_b810ffd0_30600020_be32ffd8_aa470001_30c60001_be07001c_f0660000;
+defparam bootram.RAM1.INIT_33=256'ha4a500ff_10640000_b60f0008_f8603110_30600040_10640000_b60f0008_30800001;
+defparam bootram.RAM1.INIT_34=256'h306000d0_30600090_be27000c_f860310c_10652800_be23fff8_a4630040_e8603110;
+defparam bootram.RAM1.INIT_35=256'h10800000_be23005c_a4630080_e8603110_bc23fff8_a4630002_e8603110_f8603110;
+defparam bootram.RAM1.INIT_36=256'hf8803110_bc120030_aa470001_f860310c_30800010_e0660000_30800001_be070068;
+defparam bootram.RAM1.INIT_37=256'hbe070028_30e7ffff_be23001c_a4630080_e8603110_bc23fff8_a4630002_e8603110;
+defparam bootram.RAM1.INIT_38=256'hb60f0008_f8603110_30600040_10800000_30800050_b810ffd4_b800ffc4_30c60001;
+defparam bootram.RAM1.INIT_39=256'hbc260054_a4c30000_b0008000_e8603324_10640000_b60f0008_30800001_10640000;
+defparam bootram.RAM1.INIT_3A=256'h80000000_10800000_bc660030_e8c01e80_10660000_be650048_bc430054_e8601e80;
+defparam bootram.RAM1.INIT_3B=256'h16443000_30840001_80000000_80000000_80000000_80000000_80000000_80000000;
+defparam bootram.RAM1.INIT_3C=256'ha4630007_e8603324_80000000_b60f0008_bc32ffc8_16432800_30630001_bc32ffdc;
+defparam bootram.RAM1.INIT_3D=256'h16459001_3240005a_3065ffa9_90a50060_b800ff9c_f8801e80_e4831bc4_10631800;
+defparam bootram.RAM1.INIT_3E=256'h3085ffd0_be52000c_16459001_32400039_a46300ff_3065ffc9_a46300ff_be520024;
+defparam bootram.RAM1.INIT_3F=256'hf9e10000_fb610034_13250000_fb21002c_3021ffc8_80000000_b60f0008_a46400ff;
+defparam bootram.RAM2.INIT_00=256'haa43003a_13660000_e0790000_fb410030_fb010028_fae10024_fac10020_fa61001c;
+defparam bootram.RAM2.INIT_01=256'heb010028_eae10024_eac10020_ea61001c_e9e10000_10650000_30a0ffff_be120034;
+defparam bootram.RAM2.INIT_02=256'hc085c800_30a00001_e8c01e84_30210038_b60f0008_eb610034_eb410030_eb21002c;
+defparam bootram.RAM2.INIT_03=256'hb810ffac_bc23ffe4_a4630044_c0662000_a4a300ff_be04001c_90840060_30650001;
+defparam bootram.RAM2.INIT_04=256'h12761800_66c30404_b9f4ff1c_e0b90002_80000000_b9f4ff28_e0b90001_30a0fffe;
+defparam bootram.RAM2.INIT_05=256'he0b90005_30a0fffd_be38ff74_93040060_e083000b_10791800_fa7b0004_10739800;
+defparam bootram.RAM2.INIT_06=256'h66c3040c_b9f4fed8_e0b90004_66e30404_b9f4fee4_e0b90003_13530000_b9f4fef0;
+defparam bootram.RAM2.INIT_07=256'he0b90007_fafb0008_12f7b000_12d61800_12d61800_b9f4fec8_64630408_e0b90006;
+defparam bootram.RAM2.INIT_08=256'hbe130060_f07b0000_1063b000_66c30404_b9f4fea4_e0b90008_80000000_b9f4feb0;
+defparam bootram.RAM2.INIT_09=256'hb9f4fe74_c0b6c800_a6d600ff_32d60009_12d8c000_ea7b000c_13580000_10f30000;
+defparam bootram.RAM2.INIT_0A=256'he8fb0004_ea7b000c_d0789800_1063b800_66e30404_b9f4fe68_e0b60001_12d9b000;
+defparam bootram.RAM2.INIT_0B=256'headb0008_a74300ff_be52ffb8_1647c003_107a1800_a70400ff_c073c000_30980001;
+defparam bootram.RAM2.INIT_0C=256'h107a1800_12c7b000_10632000_e0b70009_12f9b800_64760008_12e73800_e09b0000;
+defparam bootram.RAM2.INIT_0D=256'ha6d600ff_1063c000_16d60000_67030404_b9f4fe04_e0b7000a_12d61800_b9f4fe10;
+defparam bootram.RAM2.INIT_0E=256'ha4630100_e8603b10_10a00000_b810fe58_30a0fffb_be32fe60_1643b000_a46300ff;
+defparam bootram.RAM2.INIT_0F=256'ha4a500ff_80884800_a1292000_a508007f_a5290600_80000000_b60f0008_bc23fff8;
+defparam bootram.RAM2.INIT_10=256'ha0840100_f8603b18_a46600ff_f8803b10_f8e03b00_bc23fff8_a4630100_e8603b10;
+defparam bootram.RAM2.INIT_11=256'hb60f0008_e8603b00_bc23fff8_a4630100_e8603b10_10650000_be050018_f8803b10;
+defparam bootram.RAM2.INIT_12=256'h31200400_31000008_10a00000_f9e10000_3021ffe4_10e60000_10c00000_80000000;
+defparam bootram.RAM2.INIT_13=256'h3021ffc4_3021001c_b60f0008_e9e10000_80000000_b9f4ff84_f8603b14_30600001;
+defparam bootram.RAM2.INIT_14=256'hb9f4ff3c_fae10034_13060000_f9e10000_fb010038_fa61002c_12c50000_fac10030;
+defparam bootram.RAM2.INIT_15=256'hfac03b00_f8603b04_3060000b_66d60408_f8603b10_f8003b18_30600400_12670000;
+defparam bootram.RAM2.INIT_16=256'h80000000_b9f4ff00_f8603b10_30600528_f8803b10_30800428_f8603b18_30600001;
+defparam bootram.RAM2.INIT_17=256'hf8803b10_30800500_f8603b10_30600400_3261001c_12e00000_12d30000_be18009c;
+defparam bootram.RAM2.INIT_18=256'he8803b04_f8610020_e8603b08_f881001c_14b7c000_e8803b0c_80000000_b9f4fed8;
+defparam bootram.RAM2.INIT_19=256'h30a00010_10800000_beb20034_16459003_22400010_f8610028_e8603b00_f8810024;
+defparam bootram.RAM2.INIT_1A=256'hbeb20020_1658b803_12f72800_bc32fff0_16442800_30840001_d0762000_c0732000;
+defparam bootram.RAM2.INIT_1B=256'hf8003b18_12d62800_be52ff7c_1658b803_12f72800_bc25ffd8_b800ff8c_12d62800;
+defparam bootram.RAM2.INIT_1C=256'hb0009f00_3021003c_b60f0008_eb010038_eae10034_eac10030_ea61002c_e9e10000;
+defparam bootram.RAM2.INIT_1D=256'h31200400_b9f4fe34_f9e10000_31000020_30c00001_30a00001_3021ffe4_30e00000;
+defparam bootram.RAM2.INIT_1E=256'h3021ffe4_e860f828_b0000000_3021001c_b60f0008_a463ffff_b00000ff_e9e10000;
+defparam bootram.RAM2.INIT_1F=256'h64830008_80000000_b9f4ffa8_3021001c_b60f0008_e9e10000_bc030010_f9e10000;
+defparam bootram.RAM2.INIT_20=256'h16439001_32400015_80000000_b9f40330_a46300ff_be120010_aa440020_a48400ff;
+defparam bootram.RAM2.INIT_21=256'hb0000000_b800ffb0_f860f828_b0000000_bc52ffe4_16439001_32400018_bcb2fff0;
+defparam bootram.RAM2.INIT_22=256'hb9f4ff40_3021001c_b60f0008_e9e10000_bc030010_f9e10000_3021ffe4_e860f824;
+defparam bootram.RAM2.INIT_23=256'h80000000_b9f402c8_a4a300ff_be120010_aa440020_a48400ff_64830008_80000000;
+defparam bootram.RAM2.INIT_24=256'hb0000000_e0651bbe_bc52ffe4_16459001_32400018_bcb2fff0_16459001_32400015;
+defparam bootram.RAM2.INIT_25=256'h10c50000_12c00000_fac1001c_3021ffe0_b800ffa4_f860f824_b0000000_f8a0f828;
+defparam bootram.RAM2.INIT_26=256'heac1001c_e9e10000_80000000_99fcb000_30e00024_b9f40334_f9e10000_10b60000;
+defparam bootram.RAM2.INIT_27=256'hb810001c_30e1001c_b9f4fd88_f9e10000_30c00040_3021ffa4_30210020_b60f0008;
+defparam bootram.RAM2.INIT_28=256'he063001c_10612800_10600000_be520044_16459001_3240003e_30a50001_10a00000;
+defparam bootram.RAM2.INIT_29=256'haa440099_e083001c_10612800_30a50001_bc32ffd8_aa4300aa_bc12ffe0_aa4300ff;
+defparam bootram.RAM2.INIT_2A=256'h3021005c_b60f0008_e9e10000_3021005c_b60f0008_e9e10000_30600001_be32ffc8;
+defparam bootram.RAM2.INIT_2B=256'h10b60000_30c00006_b9f4fd08_f9e10000_10f60000_32c1001c_fac10028_3021ffd4;
+defparam bootram.RAM2.INIT_2C=256'heac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f401f8_30c01bd8;
+defparam bootram.RAM2.INIT_2D=256'h65040403_64e40003_64a40007_64c40005_e0803a03_3021002c_b60f0008_6464001f;
+defparam bootram.RAM2.INIT_2E=256'ha4a50008_80e73000_90a40041_a4e70004_80c62800_a4c60002_64640407_65240405;
+defparam bootram.RAM2.INIT_2F=256'h81294000_a5290040_81082000_a5080020_80842800_a4840010_80a53800_10842000;
+defparam bootram.RAM2.INIT_30=256'h64e50403_64c50003_64650007_64850005_a4a500ff_a46300ff_b60f0008_80634800;
+defparam bootram.RAM2.INIT_31=256'ha4630008_80c62000_90650041_a4c60004_80841800_a4840002_65250407_65050405;
+defparam bootram.RAM2.INIT_32=256'h81083800_a5080040_80e72800_a4e70020_80a51800_a4a50010_80633000_10a52800;
+defparam bootram.RAM2.INIT_33=256'hb00000ff_fac1001c_3021ffe0_80000000_b60f0008_f9203a00_a52900ff_81294000;
+defparam bootram.RAM2.INIT_34=256'h30a0ffaa_b9f4ff74_30a0ffff_b9f4ff7c_30a0ffff_b9f4ff84_f9e10000_a6c5ffff;
+defparam bootram.RAM2.INIT_35=256'h30a00061_b9f4ff54_30a00032_b9f4ff5c_a2d60000_b0000b00_30a0ff99_b9f4ff6c;
+defparam bootram.RAM2.INIT_36=256'h30a0ff81_b9f4ff34_30a00032_b9f4ff3c_10b60000_b9f4ff44_64b60008_b9f4ff4c;
+defparam bootram.RAM2.INIT_37=256'h30a0ffa1_b9f4ff14_30a00030_b9f4ff1c_64b60010_b9f4ff24_30a0000b_b9f4ff2c;
+defparam bootram.RAM2.INIT_38=256'h10a00000_b9f4fef4_30a00020_b9f4fefc_30a0000e_b9f4ff04_10a00000_b9f4ff0c;
+defparam bootram.RAM2.INIT_39=256'h30210020_b60f0008_eac1001c_e9e10000_10a00000_b9f4fee4_30a00020_b9f4feec;
+defparam bootram.RAM2.INIT_3A=256'hb6110000_30a0ffff_b9f4e91c_80000000_b9f4f220_f9e10000_3021ffe4_30a01be0;
+defparam bootram.RAM2.INIT_3B=256'h22400003_80000000_b60f0008_80000000_b60f0008_80000000_b6910000_80000000;
+defparam bootram.RAM2.INIT_3C=256'h16432000_e8660000_e8850000_bc230050_a4630003_80653000_beb2005c_16479003;
+defparam bootram.RAM2.INIT_3D=256'h30e7ffff_30c60004_be52ffe0_16479003_22400003_30a50004_30e7fffc_bc320040;
+defparam bootram.RAM2.INIT_3E=256'h30c60001_30a50001_be320020_16434000_e0660000_e1050000_bc120028_aa47ffff;
+defparam bootram.RAM2.INIT_3F=256'h2240000f_14634000_b60f0008_10600000_b60f0008_bc32ffe0_aa47ffff_30e7ffff;
+defparam bootram.RAM3.INIT_00=256'hbc070024_11050000_be030034_a4630003_80662800_10850000_beb20018_16479003;
+defparam bootram.RAM3.INIT_01=256'h30c60001_be32fff0_16474000_31080001_f0680000_e0660000_10e72000_11040000;
+defparam bootram.RAM3.INIT_02=256'he8860008_f8680004_e8660004_f8880000_30e7fff0_e8860000_10650000_b60f0008;
+defparam bootram.RAM3.INIT_03=256'h31080010_be52ffd0_16479003_2240000f_f868000c_30c60010_e866000c_f8880008;
+defparam bootram.RAM3.INIT_04=256'h22400003_d8682000_30e7fffc_c8662000_10800000_bcb2002c_16479003_22400003;
+defparam bootram.RAM3.INIT_05=256'he860193c_10880000_b810ff68_11044000_10c43000_30840004_be52ffec_16479003;
+defparam bootram.RAM3.INIT_06=256'h3273fffc_99fc1800_bc120018_aa43ffff_3260193c_f9e10000_fa61001c_3021ffe0;
+defparam bootram.RAM3.INIT_07=256'h3021fff8_30210020_b60f0008_ea61001c_e9e10000_bc32fff0_aa43ffff_e8730000;
+defparam bootram.RAM3.INIT_08=256'h30210008_b60f0008_c9e00800_80000000_b9f4ffb0_80000000_b9f4e7d4_d9e00800;
+defparam bootram.RAM3.INIT_09=256'hffffffff_30210008_b60f0008_c9e00800_80000000_b9f4e74c_d9e00800_3021fff8;
+defparam bootram.RAM3.INIT_0A=256'h696d6167_61696e20_523a206d_4552524f_4f4b0000_00000000_ffffffff_00000000;
+defparam bootram.RAM3.INIT_0B=256'h64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e_65207265;
+defparam bootram.RAM3.INIT_0C=256'h53746172_720a0000_6f616465_6f6f746c_322b2062_55535250_4e4f4b00_64652e00;
+defparam bootram.RAM3.INIT_0D=256'h4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20_20555352_74696e67;
+defparam bootram.RAM3.INIT_0E=256'h20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672_65747572_523a2072;
+defparam bootram.RAM3.INIT_0F=256'h523a206e_4552524f_6e210000_61707065_65722068_206e6576_6f756c64_73207368;
+defparam bootram.RAM3.INIT_10=256'h626c652e_61696c61_65206176_696d6167_61726520_69726d77_66652066_6f207361;
+defparam bootram.RAM3.INIT_11=256'h6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963_6d206120_20492061;
+defparam bootram.RAM3.INIT_12=256'h2076616c_20666f72_6b696e67_43686563_2e000000_2052414d_5820746f_20494845;
+defparam bootram.RAM3.INIT_13=256'h56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070;
+defparam bootram.RAM3.INIT_14=256'h642e2041_666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072;
+defparam bootram.RAM3.INIT_15=256'h2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e_7474656d;
+defparam bootram.RAM3.INIT_16=256'h74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741_696f6e20_64756374;
+defparam bootram.RAM3.INIT_17=256'h77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164_20746f20_74696e67;
+defparam bootram.RAM3.INIT_18=256'h6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69_2e2e2e00;
+defparam bootram.RAM3.INIT_19=256'h6e206672_65747572_523a2052_4552524f_2e2e2e00_64696e67_204c6f61_756e642e;
+defparam bootram.RAM3.INIT_1A=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d;
+defparam bootram.RAM3.INIT_1B=256'h696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000_61707065_65722068;
+defparam bootram.RAM3.INIT_1C=256'h6669726d_61666520_6e672073_54727969_6e642e20_20666f75_77617265_6669726d;
+defparam bootram.RAM3.INIT_1D=256'h0018000f_ffff0031_01b200d9_05160364_14580a2c_05050400_2e2e2e00_77617265;
+defparam bootram.RAM3.INIT_1E=256'hb8080000_b0000000_10101200_06820594_09c407d0_13880d05_00002710_000b0000;
+defparam bootram.RAM3.INIT_1F=256'h20202020_28282820_20202828_20202020_00202020_00000000_6f72740a_0a0a6162;
+defparam bootram.RAM3.INIT_20=256'h10040404_10101010_10101010_10101010_20881010_20202020_20202020_20202020;
+defparam bootram.RAM3.INIT_21=256'h01010101_01010101_01010101_41414141_10104141_10101010_04040410_04040404;
+defparam bootram.RAM3.INIT_22=256'h02020202_02020202_02020202_42424242_10104242_10101010_01010101_01010101;
+defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_20000000_10101010_02020202_02020202;
+defparam bootram.RAM3.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_2B=256'h28282020_20282828_20202020_20202020_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_2C=256'h10101010_10101010_10101010_88101010_20202020_20202020_20202020_20202020;
+defparam bootram.RAM3.INIT_2D=256'h01010101_01010101_41414101_10414141_10101010_04041010_04040404_04040404;
+defparam bootram.RAM3.INIT_2E=256'h02020202_02020202_42424202_10424242_10101010_01010110_01010101_01010101;
+defparam bootram.RAM3.INIT_2F=256'h00000000_00000000_00000000_00000000_10101020_02020210_02020202_02020202;
+defparam bootram.RAM3.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_33=256'h01010100_00001948_00000000_00000000_00000000_00000000_00000000_00000000;
+defparam bootram.RAM3.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00001d70_ffffffff;
diff --git a/fpga/usrp2/top/u2plus/capture_ddrlvds.v b/fpga/usrp2/top/u2plus/capture_ddrlvds.v
new file mode 100644
index 000000000..b9f53ff8c
--- /dev/null
+++ b/fpga/usrp2/top/u2plus/capture_ddrlvds.v
@@ -0,0 +1,39 @@
+
+
+module capture_ddrlvds
+  #(parameter WIDTH=7)
+   (input clk,
+    input ssclk_p,
+    input ssclk_n,
+    input [WIDTH-1:0] in_p,
+    input [WIDTH-1:0] in_n,
+    output reg [(2*WIDTH)-1:0] out);
+
+   wire [WIDTH-1:0] 	   ddr_dat;
+   wire 		   ssclk_regional;
+   wire 		   ssclk_io;
+   wire 		   ssclk;
+   wire [(2*WIDTH)-1:0]    out_pre1;
+   reg [(2*WIDTH)-1:0] 	   out_pre2;
+   
+   IBUFGDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
+   
+   genvar 	       i;
+   generate
+      for(i = 0; i < WIDTH; i = i + 1)
+	begin : gen_lvds_pins
+	   IBUFDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) ibufds 
+	      (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) );
+	   IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2
+	     (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk),
+	      .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0));
+	end
+   endgenerate
+
+   always @(negedge clk)
+     out_pre2 <= out_pre1;
+
+   always @(posedge clk)
+     out      <= out_pre2;
+   
+endmodule // capture_ddrlvds
diff --git a/fpga/usrp2/top/u2plus/u2plus.ucf b/fpga/usrp2/top/u2plus/u2plus.ucf
index 091eb2005..25267a67e 100755
--- a/fpga/usrp2/top/u2plus/u2plus.ucf
+++ b/fpga/usrp2/top/u2plus/u2plus.ucf
@@ -1,157 +1,137 @@
-NET "DAC_LOCK"  LOC = "P4"  ;
+## Main 100 MHz Clock
+NET "CLK_FPGA_P"  LOC = "AA13"  ;
+NET "CLK_FPGA_N"  LOC = "Y13"  ;
+
+## ADC
 NET "ADC_clkout_p"  LOC = "P1"  ;
 NET "ADC_clkout_n"  LOC = "P2"  ;
-NET "io_rx<15>"  LOC = "AD1"  ;
-NET "io_rx<14>"  LOC = "AD2"  ;
-NET "io_rx<13>"  LOC = "AC2"  ;
-NET "io_rx<12>"  LOC = "AC3"  ;
-NET "io_rx<11>"  LOC = "W7"  ;
-NET "io_rx<10>"  LOC = "W6"  ;
-NET "io_rx<09>"  LOC = "U9"  ;
-NET "io_rx<08>"  LOC = "V8"  ;
-NET "io_rx<07>"  LOC = "AB1"  ;
-NET "io_rx<06>"  LOC = "AC1"  ;
-NET "io_rx<05>"  LOC = "V7"  ;
-NET "io_rx<04>"  LOC = "V6"  ;
-NET "io_rx<03>"  LOC = "Y5"  ;
-NET "ADCB_2_3_p"  LOC = "U7"  ;
-NET "ADCB_2_3_n"  LOC = "U8"  ;
-NET "ADCB_0_1_p"  LOC = "AA2"  ;
-NET "ADCB_0_1_n"  LOC = "AA3"  ;
-NET "ADCA_12_13_p"  LOC = "Y1"  ;
-NET "ADCA_12_13_n"  LOC = "Y2"  ;
-NET "ADCA_10_11_p"  LOC = "W3"  ;
-NET "ADCA_10_11_n"  LOC = "W4"  ;
-NET "ADCA_8_9_p"  LOC = "T7"  ;
-NET "ADCA_8_9_n"  LOC = "U6"  ;
-NET "ADCA_6_7_p"  LOC = "U5"  ;
-NET "ADCA_6_7_n"  LOC = "V5"  ;
-NET "ADCA_4_5_p"  LOC = "T10"  ;
-NET "ADCA_4_5_n"  LOC = "T9"  ;
-NET "ADCA_2_3_p"  LOC = "V1"  ;
-NET "ADCA_2_3_n"  LOC = "V2"  ;
-NET "ADCA_0_1_p"  LOC = "R8"  ;
-NET "ADCA_0_1_n"  LOC = "R7"  ;
-NET "TX00_A"  LOC = "P8"  ;
-NET "TX01_A"  LOC = "P9"  ;
-NET "TX02_A"  LOC = "R5"  ;
-NET "TX03_A"  LOC = "R6"  ;
-NET "TX04_A"  LOC = "P7"  ;
-NET "TX05_A"  LOC = "P6"  ;
-NET "TX06_A"  LOC = "T3"  ;
-NET "TX07_A"  LOC = "T4"  ;
-NET "TX08_A"  LOC = "R3"  ;
-NET "TX09_A"  LOC = "R4"  ;
-NET "TX10_A"  LOC = "R2"  ;
-NET "TX11_A"  LOC = "N1"  ;
-NET "TX12_A"  LOC = "N2"  ;
-NET "TX13_A"  LOC = "N5"  ;
-NET "TX14_A"  LOC = "N4"  ;
-NET "TX15_A"  LOC = "M2"  ;
-NET "TX00_B"  LOC = "M5"  ;
-NET "TX01_B"  LOC = "M6"  ;
-NET "TX02_B"  LOC = "M4"  ;
-NET "TX03_B"  LOC = "M3"  ;
-NET "TX04_B"  LOC = "M8"  ;
-NET "TX05_B"  LOC = "M7"  ;
-NET "TX06_B"  LOC = "L4"  ;
-NET "TX07_B"  LOC = "L3"  ;
-NET "TX08_B"  LOC = "K3"  ;
-NET "TX09_B"  LOC = "K2"  ;
-NET "TX10_B"  LOC = "K5"  ;
-NET "TX11_B"  LOC = "K4"  ;
-NET "TX12_B"  LOC = "M10"  ;
-NET "TX13_B"  LOC = "M9"  ;
-NET "TX14_B"  LOC = "J5"  ;
-NET "TX15_B"  LOC = "J4"  ;
+NET "ADCA_12_p"  LOC = "Y1"  ;
+NET "ADCA_12_n"  LOC = "Y2"  ;
+NET "ADCA_10_p"  LOC = "W3"  ;
+NET "ADCA_10_n"  LOC = "W4"  ;
+NET "ADCA_8_p"  LOC = "T7"  ;
+NET "ADCA_8_n"  LOC = "U6"  ;
+NET "ADCA_6_p"  LOC = "U5"  ;
+NET "ADCA_6_n"  LOC = "V5"  ;
+NET "ADCA_4_p"  LOC = "T10"  ;
+NET "ADCA_4_n"  LOC = "T9"  ;
+NET "ADCA_2_p"  LOC = "V1"  ;
+NET "ADCA_2_n"  LOC = "V2"  ;
+NET "ADCA_0_p"  LOC = "R8"  ;
+NET "ADCA_0_n"  LOC = "R7"  ;
+NET "ADCB_2_p"  LOC = "U7"  ;
+NET "ADCB_2_n"  LOC = "U8"  ;
+NET "ADCB_0_p"  LOC = "AA2"  ;
+NET "ADCB_0_n"  LOC = "AA3"  ;
+NET "ADCB_4_p"  LOC = "AE1"  ;
+NET "ADCB_4_n"  LOC = "AE2"  ;
+NET "ADCB_6_p"  LOC = "W1"  ;
+NET "ADCB_6_n"  LOC = "W2"  ;
+NET "ADCB_8_p"  LOC = "U3"  ;
+NET "ADCB_8_n"  LOC = "V4"  ;
+NET "ADCB_10_p"  LOC = "J1"  ;
+NET "ADCB_10_n"  LOC = "K1"  ;
+NET "ADCB_12_p"  LOC = "J3"  ;
+NET "ADCB_12_n"  LOC = "J2"  ;
+
+## DAC
+NET "DAC_LOCK"  LOC = "P4"  ;
+NET "DACA<0>"  LOC = "P8"  ;
+NET "DACA<1>"  LOC = "P9"  ;
+NET "DACA<2>"  LOC = "R5"  ;
+NET "DACA<3>"  LOC = "R6"  ;
+NET "DACA<4>"  LOC = "P7"  ;
+NET "DACA<5>"  LOC = "P6"  ;
+NET "DACA<6>"  LOC = "T3"  ;
+NET "DACA<7>"  LOC = "T4"  ;
+NET "DACA<8>"  LOC = "R3"  ;
+NET "DACA<9>"  LOC = "R4"  ;
+NET "DACA<10>"  LOC = "R2"  ;
+NET "DACA<11>"  LOC = "N1"  ;
+NET "DACA<12>"  LOC = "N2"  ;
+NET "DACA<13>"  LOC = "N5"  ;
+NET "DACA<14>"  LOC = "N4"  ;
+NET "DACA<15>"  LOC = "M2"  ;
+NET "DACB<0>"  LOC = "M5"  ;
+NET "DACB<1>"  LOC = "M6"  ;
+NET "DACB<2>"  LOC = "M4"  ;
+NET "DACB<3>"  LOC = "M3"  ;
+NET "DACB<4>"  LOC = "M8"  ;
+NET "DACB<5>"  LOC = "M7"  ;
+NET "DACB<6>"  LOC = "L4"  ;
+NET "DACB<7>"  LOC = "L3"  ;
+NET "DACB<8>"  LOC = "K3"  ;
+NET "DACB<9>"  LOC = "K2"  ;
+NET "DACB<10>"  LOC = "K5"  ;
+NET "DACB<11>"  LOC = "K4"  ;
+NET "DACB<12>"  LOC = "M10"  ;
+NET "DACB<13>"  LOC = "M9"  ;
+NET "DACB<14>"  LOC = "J5"  ;
+NET "DACB<15>"  LOC = "J4"  ;
+
+## TX DB GPIO
 NET "io_tx<15>"  LOC = "K6"  ;
 NET "io_tx<14>"  LOC = "L7"  ;
 NET "io_tx<13>"  LOC = "H2"  ;
 NET "io_tx<12>"  LOC = "H1"  ;
 NET "io_tx<11>"  LOC = "L10"  ;
 NET "io_tx<10>"  LOC = "L9"  ;
-NET "io_tx<09>"  LOC = "G3"  ;
-NET "io_tx<08>"  LOC = "F3"  ;
-NET "io_tx<07>"  LOC = "K7"  ;
-NET "io_tx<06>"  LOC = "J6"  ;
-NET "io_tx<05>"  LOC = "E1"  ;
-NET "io_tx<04>"  LOC = "F2"  ;
-NET "io_tx<03>"  LOC = "J7"  ;
-NET "io_tx<02>"  LOC = "H6"  ;
-NET "io_tx<01>"  LOC = "F5"  ;
-NET "io_tx<00>"  LOC = "G4"  ;
-NET "MOSI_RX_ADC"  LOC = "E3"  ;
-NET "SCLK_RX_ADC"  LOC = "F4"  ;
-NET "SEN_RX_ADC"  LOC = "D3"  ;
-NET "SCLK_RX_DAC"  LOC = "E4"  ;
-NET "SEN_RX_DAC"  LOC = "K9"  ;
-NET "MOSI_RX_DAC"  LOC = "K8"  ;
-NET "SCLK_RX_DB"  LOC = "G6"  ;
-NET "MOSI_RX_DB"  LOC = "H7"  ;
-NET "SEN_RX_DB"  LOC = "B2"  ;
-NET "SCLK_ADC"  LOC = "B1"  ;
-NET "MOSI_ADC"  LOC = "J8"  ;
-NET "SEN_ADC"  LOC = "J9"  ;
-NET "ADCB_4_5_p"  LOC = "AE1"  ;
-NET "ADCB_4_5_n"  LOC = "AE2"  ;
-NET "ADCB_6_7_p"  LOC = "W1"  ;
-NET "ADCB_6_7_n"  LOC = "W2"  ;
-NET "ADCB_8_9_p"  LOC = "U3"  ;
-NET "ADCB_8_9_n"  LOC = "V4"  ;
-NET "ADCB_10_11_p"  LOC = "J1"  ;
-NET "ADCB_10_11_n"  LOC = "K1"  ;
-NET "ADCB_12_13_p"  LOC = "J3"  ;
-NET "ADCB_12_13_n"  LOC = "J2"  ;
-NET "MISO_RX_DB"  LOC = "H4"  ;
-NET "MISO_RX_ADC"  LOC = "C1"  ;
-NET "MISO_TX_DB"  LOC = "AA5"  ;
-NET "MISO_DAC"  LOC = "Y3"  ;
-NET "MISO_TX_ADC"  LOC = "G1"  ;
-NET "io_rx<02>"  LOC = "R10"  ;
-NET "io_rx<01>"  LOC = "R1"  ;
-NET "io_rx<00>"  LOC = "M1"  ;
-NET "exp_user_out_p"  LOC = "AF14"  ;
-NET "exp_user_out_n"  LOC = "AE14"  ;
-NET "exp_time_out_p"  LOC = "Y14"  ;
-NET "exp_time_out_n"  LOC = "AA14"  ;
-NET "CLK_FPGA_P"  LOC = "AA13"  ;
-NET "CLK_FPGA_N"  LOC = "Y13"  ;
+NET "io_tx<9>"  LOC = "G3"  ;
+NET "io_tx<8>"  LOC = "F3"  ;
+NET "io_tx<7>"  LOC = "K7"  ;
+NET "io_tx<6>"  LOC = "J6"  ;
+NET "io_tx<5>"  LOC = "E1"  ;
+NET "io_tx<4>"  LOC = "F2"  ;
+NET "io_tx<3>"  LOC = "J7"  ;
+NET "io_tx<2>"  LOC = "H6"  ;
+NET "io_tx<1>"  LOC = "F5"  ;
+NET "io_tx<0>"  LOC = "G4"  ;
+
+## RX DB GPIO
+NET "io_rx<15>"  LOC = "AD1"  ;
+NET "io_rx<14>"  LOC = "AD2"  ;
+NET "io_rx<13>"  LOC = "AC2"  ;
+NET "io_rx<12>"  LOC = "AC3"  ;
+NET "io_rx<11>"  LOC = "W7"  ;
+NET "io_rx<10>"  LOC = "W6"  ;
+NET "io_rx<9>"  LOC = "U9"  ;
+NET "io_rx<8>"  LOC = "V8"  ;
+NET "io_rx<7>"  LOC = "AB1"  ;
+NET "io_rx<6>"  LOC = "AC1"  ;
+NET "io_rx<5>"  LOC = "V7"  ;
+NET "io_rx<4>"  LOC = "V6"  ;
+NET "io_rx<3>"  LOC = "Y5"  ;
+NET "io_rx<2>"  LOC = "R10"  ;
+NET "io_rx<1>"  LOC = "R1"  ;
+NET "io_rx<0>"  LOC = "M1"  ;
+
+## MISC
 NET "leds<5>"  LOC = "AF25"  ;
 NET "leds<4>"  LOC = "AE25"  ;
 NET "leds<3>"  LOC = "AF23"  ;
 NET "leds<2>"  LOC = "AE23"  ;
 NET "leds<1>"  LOC = "AB18"  ;
-NET "SEN_CLK"  LOC = "AA18"  ;
-NET "MOSI_CLK"  LOC = "W17"  ;
-NET "SCLK_CLK"  LOC = "V17"  ;
-NET "CLK_STATUS"  LOC = "AD22"  ;
-NET "CLK_FUNC"  LOC = "AC21"  ;
-NET "clk_sel<0>"  LOC = "AE21"  ;
-NET "clk_sel<1>"  LOC = "AD21"  ;
-NET "clk_en<1>"  LOC = "AA17"  ;
-NET "clk_en<0>"  LOC = "Y17"  ;
-NET "SDA"  LOC = "V16"  ;
-NET "SCL"  LOC = "U16"  ;
-NET "TXD3"  LOC = "AD20"  ;
-NET "TXD2"  LOC = "AC20"  ;
-NET "TXD1"  LOC = "AD19"  ;
-NET "debug<00>"  LOC = "AC19"  ;
-NET "debug<01>"  LOC = "AF20"  ;
-NET "debug<02>"  LOC = "AE20"  ;
-NET "debug<03>"  LOC = "AC16"  ;
-NET "debug<04>"  LOC = "AB16"  ;
-NET "debug<05>"  LOC = "AF19"  ;
-NET "debug<06>"  LOC = "AE19"  ;
-NET "debug<07>"  LOC = "V15"  ;
-NET "debug<08>"  LOC = "U15"  ;
-NET "debug<09>"  LOC = "AE17"  ;
+NET "FPGA_RESET"  LOC = "K24"  ;
+
+## Debug
+NET "debug_clk<0>"  LOC = "AA10"  ;
+NET "debug_clk<1>"  LOC = "AD11"  ;
+NET "debug<0>"  LOC = "AC19"  ;
+NET "debug<1>"  LOC = "AF20"  ;
+NET "debug<2>"  LOC = "AE20"  ;
+NET "debug<3>"  LOC = "AC16"  ;
+NET "debug<4>"  LOC = "AB16"  ;
+NET "debug<5>"  LOC = "AF19"  ;
+NET "debug<6>"  LOC = "AE19"  ;
+NET "debug<7>"  LOC = "V15"  ;
+NET "debug<8>"  LOC = "U15"  ;
+NET "debug<9>"  LOC = "AE17"  ;
 NET "debug<10>"  LOC = "AD17"  ;
 NET "debug<11>"  LOC = "V14"  ;
 NET "debug<12>"  LOC = "W15"  ;
 NET "debug<13>"  LOC = "AC15"  ;
 NET "debug<14>"  LOC = "AD14"  ;
 NET "debug<15>"  LOC = "AC14"  ;
-NET "debug_clk<1>"  LOC = "AD11"  ;
 NET "debug<16>"  LOC = "AC11"  ;
 NET "debug<17>"  LOC = "AB12"  ;
 NET "debug<18>"  LOC = "AC12"  ;
@@ -168,187 +148,277 @@ NET "debug<28>"  LOC = "AB7"  ;
 NET "debug<29>"  LOC = "V11"  ;
 NET "debug<30>"  LOC = "U11"  ;
 NET "debug<31>"  LOC = "Y10"  ;
-NET "debug_clk<0>"  LOC = "AA10"  ;
+
+## UARTS
+NET "TXD<3>"  LOC = "AD20"  ;
+NET "TXD<2>"  LOC = "AC20"  ;
+NET "TXD<1>"  LOC = "AD19"  ;
+NET "RXD<3>"  LOC = "AF17"  ;
+NET "RXD<2>"  LOC = "AF15"  ;
+NET "RXD<1>"  LOC = "AD12"  ;
+
+## AD9510
+NET "CLK_STATUS"  LOC = "AD22"  ;
+NET "CLK_FUNC"  LOC = "AC21"  ;
+NET "clk_sel<0>"  LOC = "AE21"  ;
+NET "clk_sel<1>"  LOC = "AD21"  ;
+NET "clk_en<1>"  LOC = "AA17"  ;
+NET "clk_en<0>"  LOC = "Y17"  ;
+
+## I2C
+NET "SDA"  LOC = "V16"  ;
+NET "SCL"  LOC = "U16"  ;
+
+## Timing
+NET "PPS_IN"  LOC = "AB6"  ;
+NET "PPS2_IN"  LOC = "AA20"  ;
+
+## SPI
+NET "SEN_CLK"  LOC = "AA18"  ;
+NET "MOSI_CLK"  LOC = "W17"  ;
+NET "SCLK_CLK"  LOC = "V17"  ;
+NET "MISO_CLK"  LOC = "AC10"  ;
+
 NET "SEN_DAC"  LOC = "AE7"  ;
 NET "SCLK_DAC"  LOC = "AF5"  ;
 NET "MOSI_DAC"  LOC = "AE6"  ;
+NET "MISO_DAC"  LOC = "Y3"  ;
+
+NET "SCLK_ADC"  LOC = "B1"  ;
+NET "MOSI_ADC"  LOC = "J8"  ;
+NET "SEN_ADC"  LOC = "J9"  ;
+
 NET "MOSI_TX_ADC"  LOC = "V10"  ;
 NET "SEN_TX_ADC"  LOC = "W10"  ;
 NET "SCLK_TX_ADC"  LOC = "AC6"  ;
+NET "MISO_TX_ADC"  LOC = "G1"  ;
+
 NET "MOSI_TX_DAC"  LOC = "AD6"  ;
 NET "SEN_TX_DAC"  LOC = "AE4"  ;
 NET "SCLK_TX_DAC"  LOC = "AF4"  ;
+
 NET "SCLK_TX_DB"  LOC = "AE3"  ;
 NET "MOSI_TX_DB"  LOC = "AF3"  ;
 NET "SEN_TX_DB"  LOC = "W9"  ;
-NET "RXD3"  LOC = "AF17"  ;
-NET "RXD2"  LOC = "AF15"  ;
-NET "RXD1"  LOC = "AD12"  ;
-NET "MISO_CLK"  LOC = "AC10"  ;
-NET "PPS_IN"  LOC = "AB6"  ;
-NET "PPS2_IN"  LOC = "AA20"  ;
-NET "ser_rx_clk"  LOC = "P18"  ;
-NET "ser_tx_clk"  LOC = "P23"  ;   # SERDES TX CLK
+NET "MISO_TX_DB"  LOC = "AA5"  ;
+
+NET "MOSI_RX_ADC"  LOC = "E3"  ;
+NET "SCLK_RX_ADC"  LOC = "F4"  ;
+NET "SEN_RX_ADC"  LOC = "D3"  ;
+NET "MISO_RX_ADC"  LOC = "C1"  ;
+
+NET "SCLK_RX_DAC"  LOC = "E4"  ;
+NET "SEN_RX_DAC"  LOC = "K9"  ;
+NET "MOSI_RX_DAC"  LOC = "K8"  ;
+
+NET "SCLK_RX_DB"  LOC = "G6"  ;
+NET "MOSI_RX_DB"  LOC = "H7"  ;
+NET "SEN_RX_DB"  LOC = "B2"  ;
+NET "MISO_RX_DB"  LOC = "H4"  ;
+
+## ETH PHY
 NET "CLK_TO_MAC"  LOC = "P26"  ;
-NET "GMII_TX_CLK"  LOC = "P25"  ;
-NET "GMII_RX_CLK"  LOC = "P21"  ;
-NET "ETH_LED"  LOC = "H20"  ;
-NET "GMII_TXD7"  LOC = "G21"  ;
-NET "GMII_TXD6"  LOC = "C26"  ;
-NET "GMII_TXD5"  LOC = "C25"  ;
-NET "GMII_TXD4"  LOC = "J21"  ;
-NET "GMII_TXD3"  LOC = "H21"  ;
-NET "GMII_TXD2"  LOC = "D25"  ;
-NET "GMII_TXD1"  LOC = "D24"  ;
-NET "GMII_TXD0"  LOC = "E26"  ;
+
+NET "GMII_TXD<7>"  LOC = "G21"  ;
+NET "GMII_TXD<6>"  LOC = "C26"  ;
+NET "GMII_TXD<5>"  LOC = "C25"  ;
+NET "GMII_TXD<4>"  LOC = "J21"  ;
+NET "GMII_TXD<3>"  LOC = "H21"  ;
+NET "GMII_TXD<2>"  LOC = "D25"  ;
+NET "GMII_TXD<1>"  LOC = "D24"  ;
+NET "GMII_TXD<0>"  LOC = "E26"  ;
 NET "GMII_TX_EN"  LOC = "D26"  ;
 NET "GMII_TX_ER"  LOC = "J19"  ;
 NET "GMII_GTX_CLK"  LOC = "J20"  ;
-NET "GMII_RXD7"  LOC = "G22"  ;
-NET "GMII_RXD6"  LOC = "K19"  ;
-NET "GMII_RXD5"  LOC = "K18"  ;
-NET "GMII_RXD4"  LOC = "E24"  ;
-NET "GMII_RXD3"  LOC = "F23"  ;
-NET "GMII_RXD2"  LOC = "L18"  ;
-NET "GMII_RXD1"  LOC = "L17"  ;
-NET "GMII_RXD0"  LOC = "F25"  ;
+NET "GMII_TX_CLK"  LOC = "P25"  ;
+
+NET "GMII_RX_CLK"  LOC = "P21"  ;
+NET "GMII_RXD<7>"  LOC = "G22"  ;
+NET "GMII_RXD<6>"  LOC = "K19"  ;
+NET "GMII_RXD<5>"  LOC = "K18"  ;
+NET "GMII_RXD<4>"  LOC = "E24"  ;
+NET "GMII_RXD<3>"  LOC = "F23"  ;
+NET "GMII_RXD<2>"  LOC = "L18"  ;
+NET "GMII_RXD<1>"  LOC = "L17"  ;
+NET "GMII_RXD<0>"  LOC = "F25"  ;
 NET "GMII_RX_DV"  LOC = "F24"  ;
 NET "GMII_RX_ER"  LOC = "L20"  ;
 NET "GMII_CRS"  LOC = "K20"  ;
 NET "GMII_COL"  LOC = "G23"  ;
+
 NET "PHY_INTn"  LOC = "L22"  ;
 NET "MDIO"  LOC = "K21"  ;
 NET "MDC"  LOC = "J23"  ;
-NET "PHY_RESET"  LOC = "J22"  ;
+NET "PHY_RESETn"  LOC = "J22"  ;
+NET "ETH_LED"  LOC = "H20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+
+## MIMO Interface
+NET "exp_time_out_p"  LOC = "Y14"  ;
+NET "exp_time_out_n"  LOC = "AA14"  ;
 NET "exp_time_in_p"  LOC = "N18"  ;
 NET "exp_time_in_n"  LOC = "N17"  ;
+NET "exp_user_out_p"  LOC = "AF14"  ;
+NET "exp_user_out_n"  LOC = "AE14"  ;
 NET "exp_user_in_p"  LOC = "L24"  ;
 NET "exp_user_in_n"  LOC = "M23"  ;
+
+## SERDES
+NET "ser_enable"  LOC = "R20"  ;
 NET "ser_prbsen"  LOC = "U23"  ;
 NET "ser_loopen"  LOC = "R19"  ;
-NET "ser_enable"  LOC = "R20"  ;
+NET "ser_rx_en"  LOC = "Y21"  ;
+NET "ser_tx_clk"  LOC = "P23"  ;   # SERDES TX CLK
 NET "ser_t<15>"  LOC = "V23"  ;
 NET "ser_t<14>"  LOC = "U22"  ;
 NET "ser_t<13>"  LOC = "V24"  ;
 NET "ser_t<12>"  LOC = "V25"  ;
 NET "ser_t<11>"  LOC = "W23"  ;
 NET "ser_t<10>"  LOC = "V22"  ;
-NET "ser_t<09>"  LOC = "T18"  ;
-NET "ser_t<08>"  LOC = "T17"  ;
-NET "ser_t<07>"  LOC = "Y24"  ;
-NET "ser_t<06>"  LOC = "Y25"  ;
-NET "ser_t<05>"  LOC = "U21"  ;
-NET "ser_t<04>"  LOC = "T20"  ;
-NET "ser_t<03>"  LOC = "Y22"  ;
-NET "ser_t<02>"  LOC = "Y23"  ;
-NET "ser_t<01>"  LOC = "U19"  ;
-NET "ser_t<00>"  LOC = "U18"  ;
+NET "ser_t<9>"  LOC = "T18"  ;
+NET "ser_t<8>"  LOC = "T17"  ;
+NET "ser_t<7>"  LOC = "Y24"  ;
+NET "ser_t<6>"  LOC = "Y25"  ;
+NET "ser_t<5>"  LOC = "U21"  ;
+NET "ser_t<4>"  LOC = "T20"  ;
+NET "ser_t<3>"  LOC = "Y22"  ;
+NET "ser_t<2>"  LOC = "Y23"  ;
+NET "ser_t<1>"  LOC = "U19"  ;
+NET "ser_t<0>"  LOC = "U18"  ;
 NET "ser_tkmsb"  LOC = "AA24"  ;
 NET "ser_tklsb"  LOC = "AA25"  ;
+NET "ser_rx_clk"  LOC = "P18"  ;
 NET "ser_r<15>"  LOC = "V21"  ;
 NET "ser_r<14>"  LOC = "U20"  ;
 NET "ser_r<13>"  LOC = "AA22"  ;
 NET "ser_r<12>"  LOC = "AA23"  ;
 NET "ser_r<11>"  LOC = "V18"  ;
 NET "ser_r<10>"  LOC = "V19"  ;
-NET "ser_r<09>"  LOC = "AB23"  ;
-NET "ser_r<08>"  LOC = "AC26"  ;
-NET "ser_r<07>"  LOC = "AB26"  ;
-NET "ser_r<06>"  LOC = "AD26"  ;
-NET "ser_r<05>"  LOC = "AC25"  ;
-NET "ser_r<04>"  LOC = "W20"  ;
-NET "ser_r<03>"  LOC = "W21"  ;
-NET "ser_r<02>"  LOC = "AC23"  ;
-NET "ser_r<01>"  LOC = "AC24"  ;
-NET "ser_r<00>"  LOC = "AE26"  ;
+NET "ser_r<9>"  LOC = "AB23"  ;
+NET "ser_r<8>"  LOC = "AC26"  ;
+NET "ser_r<7>"  LOC = "AB26"  ;
+NET "ser_r<6>"  LOC = "AD26"  ;
+NET "ser_r<5>"  LOC = "AC25"  ;
+NET "ser_r<4>"  LOC = "W20"  ;
+NET "ser_r<3>"  LOC = "W21"  ;
+NET "ser_r<2>"  LOC = "AC23"  ;
+NET "ser_r<1>"  LOC = "AC24"  ;
+NET "ser_r<0>"  LOC = "AE26"  ;
 NET "ser_rkmsb"  LOC = "AD25"  ;
 NET "ser_rklsb"  LOC = "Y20"  ;
-NET "ser_rx_en"  LOC = "Y21"  ;
-NET "FPGA_RESET"  LOC = "K24"  ;
-NET "RAM_D<17>"  LOC = "F7"  ;
-NET "RAM_D<16>"  LOC = "E7"  ;
-NET "RAM_D<15>"  LOC = "G9"  ;
-NET "RAM_D<14>"  LOC = "H9"  ;
-NET "RAM_D<13>"  LOC = "G10"  ;
-NET "RAM_D<12>"  LOC = "H10"  ;
-NET "RAM_D<11>"  LOC = "A4"  ;
-NET "RAM_D<10>"  LOC = "B4"  ;
-NET "RAM_D<09>"  LOC = "C5"  ;
-NET "RAM_D<08>"  LOC = "D6"  ;
-NET "RAM_D<07>"  LOC = "J11"  ;
-NET "RAM_D<06>"  LOC = "K11"  ;
-NET "RAM_D<05>"  LOC = "B7"  ;
-NET "RAM_D<04>"  LOC = "C7"  ;
-NET "RAM_D<03>"  LOC = "B6"  ;
-NET "RAM_D<02>"  LOC = "C6"  ;
-NET "RAM_D<01>"  LOC = "C8"  ;
-NET "RAM_D<00>"  LOC = "D8"  ;
-NET "RAM_ZZ"  LOC = "J12"  ;
-NET "RAM_BWn<3>"  LOC = "D9"  ;
-NET "RAM_BWn<2>"  LOC = "A9"  ;
-NET "RAM_BWn<1>"  LOC = "B9"  ;
-NET "RAM_BWn<0>"  LOC = "G12"  ;
-NET "RAM_LDn"  LOC = "H12"  ;
-NET "RAM_OEn"  LOC = "C10"  ;
-NET "RAM_WEn"  LOC = "D10"  ;
-NET "RAM_CLK"  LOC = "A10"  ;
-NET "RAM_CENn"  LOC = "B10"  ;
-NET "RAM_A<00>"  LOC = "C11"  ;
-NET "RAM_A<01>"  LOC = "E12"  ;
-NET "RAM_A<02>"  LOC = "F12"  ;
-NET "RAM_A<03>"  LOC = "D13"  ;
-NET "RAM_A<04>"  LOC = "C12"  ;
-NET "RAM_A<05>"  LOC = "A12"  ;
-NET "RAM_A<06>"  LOC = "B12"  ;
-NET "RAM_A<07>"  LOC = "E14"  ;
-NET "RAM_A<08>"  LOC = "F14"  ;
-NET "RAM_A<09>"  LOC = "B15"  ;
-NET "RAM_A<10>"  LOC = "A15"  ;
-NET "RAM_A<11>"  LOC = "D16"  ;
-NET "RAM_A<12>"  LOC = "C15"  ;
-NET "RAM_A<13>"  LOC = "D17"  ;
-NET "RAM_A<14>"  LOC = "C16"  ;
-NET "RAM_A<15>"  LOC = "F15"  ;
-NET "RAM_A<16>"  LOC = "C17"  ;
-NET "RAM_A<17>"  LOC = "B17"  ;
-NET "RAM_A<18>"  LOC = "B18"  ;
-NET "RAM_A<19>"  LOC = "A18"  ;
-NET "RAM_A<20>"  LOC = "D18"  ;
-NET "RAM_D<35>"  LOC = "K16"  ;
-NET "RAM_D<34>"  LOC = "D20"  ;
-NET "RAM_D<33>"  LOC = "C20"  ;
-NET "RAM_D<32>"  LOC = "E21"  ;
-NET "RAM_D<31>"  LOC = "D21"  ;
-NET "RAM_D<30>"  LOC = "C21"  ;
-NET "RAM_D<29>"  LOC = "B21"  ;
-NET "RAM_D<28>"  LOC = "H17"  ;
-NET "RAM_D<27>"  LOC = "G17"  ;
-NET "RAM_D<26>"  LOC = "B23"  ;
-NET "RAM_D<25>"  LOC = "A22"  ;
-NET "RAM_D<24>"  LOC = "D23"  ;
-NET "RAM_D<23>"  LOC = "C23"  ;
-NET "RAM_D<22>"  LOC = "D22"  ;
-NET "RAM_D<21>"  LOC = "C22"  ;
-NET "RAM_D<20>"  LOC = "F19"  ;
-NET "RAM_D<19>"  LOC = "G20"  ;
-NET "RAM_D<18>"  LOC = "F20"  ;
-#NET "unnamed_net20"  LOC = "V20"  ;  # SUSPEND
-NET "PROG_B"  LOC = "A2"  ;
-NET "PUDC_B"  LOC = "G8"  ;
-NET "DONE"  LOC = "AB21"  ;
+
+## SRAM
+NET "RAM_D<35>"  LOC = "K16"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<34>"  LOC = "D20"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<33>"  LOC = "C20"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<32>"  LOC = "E21"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<31>"  LOC = "D21"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<30>"  LOC = "C21"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<29>"  LOC = "B21"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<28>"  LOC = "H17"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<27>"  LOC = "G17"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<26>"  LOC = "B23"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<25>"  LOC = "A22"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<24>"  LOC = "D23"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<23>"  LOC = "C23"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<22>"  LOC = "D22"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<21>"  LOC = "C22"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<20>"  LOC = "F19"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<19>"  LOC = "G20"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<18>"  LOC = "F20"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<17>"  LOC = "F7"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<16>"  LOC = "E7"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<15>"  LOC = "G9"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<14>"  LOC = "H9"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<13>"  LOC = "G10"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<12>"  LOC = "H10"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<11>"  LOC = "A4"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<10>"  LOC = "B4"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<9>"  LOC = "C5"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<8>"  LOC = "D6"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<7>"  LOC = "J11"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<6>"  LOC = "K11"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<5>"  LOC = "B7"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<4>"  LOC = "C7"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<3>"  LOC = "B6"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<2>"  LOC = "C6"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<1>"  LOC = "C8"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_D<0>"  LOC = "D8"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<0>"  LOC = "C11"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<1>"  LOC = "E12"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<2>"  LOC = "F12"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<3>"  LOC = "D13"    |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<4>"  LOC = "C12"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<5>"  LOC = "A12"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<6>"  LOC = "B12"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<7>"  LOC = "E14"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<8>"  LOC = "F14"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<9>"  LOC = "B15"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<10>"  LOC = "A15"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<11>"  LOC = "D16"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<12>"  LOC = "C15"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<13>"  LOC = "D17"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<14>"  LOC = "C16"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<15>"  LOC = "F15"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<16>"  LOC = "C17"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<17>"  LOC = "B17"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<18>"  LOC = "B18"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<19>"  LOC = "A18"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_A<20>"  LOC = "D18"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_BWn<3>"  LOC = "D9"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_BWn<2>"  LOC = "A9"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_BWn<1>"  LOC = "B9"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_BWn<0>"  LOC = "G12"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_ZZ"  LOC = "J12"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_LDn"  LOC = "H12"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_OEn"  LOC = "C10"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_WEn"  LOC = "D10"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_CENn"  LOC = "B10"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+NET "RAM_CLK"  LOC = "A10"   |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = FAST ;
+
+## SPI Flash
 NET "flash_miso"  LOC = "AF24"  ;
 NET "flash_clk"  LOC = "AE24"  ;
-NET "INIT_B"  LOC = "AA15"  ;
 NET "flash_mosi"  LOC = "AB15"  ;
+NET "flash_cs"  LOC = "AA7"  ;
+
+## MISC FPGA, unused for now
+#NET "PROG_B"  LOC = "A2"  ;
+#NET "PUDC_B"  LOC = "G8"  ;
+#NET "DONE"  LOC = "AB21"  ;
+#NET "INIT_B"  LOC = "AA15"  ;
+
+
 #NET "unnamed_net19"  LOC = "AE9"  ;    # VS1
 #NET "unnamed_net18"  LOC = "AF9"  ;    # VS0
 #NET "unnamed_net17"  LOC = "AA12"  ;   # VS2
 #NET "unnamed_net16"  LOC = "Y7"  ;     # M2
-NET "flash_cs"  LOC = "AA7"  ;
 #NET "unnamed_net15"  LOC = "AC4"  ;    # M1
 #NET "unnamed_net14"  LOC = "AD4"  ;    # M0
 #NET "unnamed_net13"  LOC = "D4"  ;     # TMS
 #NET "unnamed_net12"  LOC = "E23"  ;    # TDO
 #NET "unnamed_net11"  LOC = "G7"  ;     # TDI
 #NET "unnamed_net10"  LOC = "A25"  ;    # TCK
+#NET "unnamed_net20"  LOC = "V20"  ;    # SUSPEND
+
+
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+
+TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns;
+
+#NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE;
+#PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
+
+#NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
+#PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE;
+
 
diff --git a/fpga/usrp2/top/u2plus/u2plus.v b/fpga/usrp2/top/u2plus/u2plus.v
index e95445867..270655a8d 100644
--- a/fpga/usrp2/top/u2plus/u2plus.v
+++ b/fpga/usrp2/top/u2plus/u2plus.v
@@ -1,48 +1,96 @@
 `timescale 1ns / 1ps
+//`define DCM_FOR_RAMCLK
 //////////////////////////////////////////////////////////////////////////////////
 
 module u2plus
   (
+   input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
+   
+   // ADC
+   input ADC_clkout_p, input ADC_clkout_n,
+   input ADCA_12_p, input ADCA_12_n,
+   input ADCA_10_p, input ADCA_10_n,
+   input ADCA_8_p, input ADCA_8_n,
+   input ADCA_6_p, input ADCA_6_n,
+   input ADCA_4_p, input ADCA_4_n,
+   input ADCA_2_p, input ADCA_2_n,
+   input ADCA_0_p, input ADCA_0_n,
+   input ADCB_12_p, input ADCB_12_n,
+   input ADCB_10_p, input ADCB_10_n,
+   input ADCB_8_p, input ADCB_8_n,
+   input ADCB_6_p, input ADCB_6_n,
+   input ADCB_4_p, input ADCB_4_n,
+   input ADCB_2_p, input ADCB_2_n,
+   input ADCB_0_p, input ADCB_0_n,
+   
+   // DAC
+   output reg [15:0] DACA,
+   output reg [15:0] DACB,
+   input DAC_LOCK,     // unused for now
+   
+   // DB IO Pins
+   inout [15:0] io_tx,
+   inout [15:0] io_rx,
+
    // Misc, debug
-   output [4:0] leds,  // LED4 is shared w/INIT_B
-   input [3:0] dipsw,
-   output [31:0] debug,
+   output [5:1] leds,  // LED4 is shared w/INIT_B
+   input FPGA_RESET,
    output [1:0] debug_clk,
-   output uart_tx_o,
-   input uart_rx_i,
-   
-   // Expansion
-   input exp_pps_in_p, // Diff
-   input exp_pps_in_n, // Diff
-   output exp_pps_out_p, // Diff 
-   output exp_pps_out_n, // Diff 
+   output [31:0] debug,
+   output [3:1] TXD, input [3:1] RXD, // UARTs
+   //input [3:0] dipsw,  // Forgot DIP Switches...
    
-   // GMII
-   //   GMII-CTRL
-   input GMII_COL,
-   input GMII_CRS,
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input CLK_FUNC,        // FIXME is an input to control the 9510
+   input CLK_STATUS,
+
+   inout SCL, inout SDA,   // I2C
+
+   // PPS
+   input PPS_IN, input PPS2_IN,
+
+   // SPI
+   output SEN_CLK, output SCLK_CLK, output MOSI_CLK, input MISO_CLK,
+   output SEN_DAC, output SCLK_DAC, output MOSI_DAC, input MISO_DAC,
+   output SEN_ADC, output SCLK_ADC, output MOSI_ADC,
+   output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB,
+   output SEN_TX_DAC, output SCLK_TX_DAC, output MOSI_TX_DAC,
+   output SEN_TX_ADC, output SCLK_TX_ADC, output MOSI_TX_ADC, input MISO_TX_ADC,
+   output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB,
+   output SEN_RX_DAC, output SCLK_RX_DAC, output MOSI_RX_DAC,
+   output SEN_RX_ADC, output SCLK_RX_ADC, output MOSI_RX_ADC, input MISO_RX_ADC,
+
+   // GigE PHY
+   input CLK_TO_MAC,
 
-   //   GMII-TX
    output reg [7:0] GMII_TXD,
    output reg GMII_TX_EN,
    output reg GMII_TX_ER,
    output GMII_GTX_CLK,
    input GMII_TX_CLK,  // 100mbps clk
 
-   //   GMII-RX
-   input [7:0] GMII_RXD,
    input GMII_RX_CLK,
+   input [7:0] GMII_RXD,
    input GMII_RX_DV,
    input GMII_RX_ER,
+   input GMII_COL,
+   input GMII_CRS,
 
-   //   GMII-Management
+   input PHY_INTn,   // open drain
    inout MDIO,
    output MDC,
-   input PHY_INTn,   // open drain
    output PHY_RESETn,
-   input PHY_CLK,   // possibly use on-board osc
-   input clk_to_mac,
-   output eth_led,
+   output ETH_LED,
+   
+//   input POR,
+   
+   // Expansion
+   input exp_time_in_p, input exp_time_in_n, // Diff
+   output exp_time_out_p, output exp_time_out_n, // Diff 
+   input exp_user_in_p, input exp_user_in_n, // Diff
+   output exp_user_out_p, output exp_user_out_n, // Diff 
    
    // SERDES
    output ser_enable,
@@ -59,75 +107,18 @@ module u2plus
    input [15:0] ser_r,
    input ser_rklsb,
    input ser_rkmsb,
-   
-   // ADC
-   input [13:0] adc_a,
-   input adc_ovf_a,
-   output adc_oen_a,
-   output adc_pdn_a,
-   
-   input [13:0] adc_b,
-   input adc_ovf_b,
-   output adc_oen_b,
-   output adc_pdn_b,
-   
-   // DAC
-   output [15:0] dac_a,
-   output [15:0] dac_b,
-   input dac_lock,     // unused for now
-   
-   // I2C
-   inout SCL,
-   inout SDA,
 
-   // Clock Gen Control
-   output [1:0] clk_en,
-   output [1:0] clk_sel,
-   input clk_func,        // FIXME is an input to control the 9510
-   input clk_status,
-
-   // Clocks
-   input clk_fpga_p,  // Diff
-   input clk_fpga_n,  // Diff
-   input pps_in,
-   input POR,
+   // SRAM
+   inout [35:0] RAM_D,
+   output [20:0] RAM_A,
+   output [3:0] RAM_BWn,
+   output RAM_ZZ,
+   output RAM_LDn,
+   output RAM_OEn,
+   output RAM_WEn,
+   output RAM_CENn,
+   output RAM_CLK,
    
-   // AD9510 SPI
-   output sclk,
-   output sen_clk,
-   output sdi,
-   input sdo,
-
-   // TX side SPI -- tx_db, tx_adc, tx_dac, 9777
-   output sen_dac,
-   output sen_tx_db,
-   output sen_tx_adc,
-   output sen_tx_dac,
-   output mosi_tx,
-   input miso_dac,
-   input miso_tx_db,
-   input miso_tx_adc,
-   output sclk_tx,
-
-   // RX side SPI
-   output sen_rx_db,
-   output sclk_rx_db,
-   input sdo_rx_db,
-   output sdi_rx_db,
-
-   output sen_rx_adc,
-   output sclk_rx_adc,
-   input sdo_rx_adc,
-   output sdi_rx_adc,
-
-   output sen_rx_dac,
-   output sclk_rx_dac,
-   output sdi_rx_dac,
-
-   // DB IO Pins
-   inout [15:0] io_tx,
-   inout [15:0] io_rx,
-
    // SPI Flash
    output flash_cs,
    output flash_clk,
@@ -135,38 +126,63 @@ module u2plus
    input flash_miso
    );
 
+   wire  CLK_TO_MAC_int, CLK_TO_MAC_int2;
+   IBUFG phyclk (.O(CLK_TO_MAC_int), .I(CLK_TO_MAC));
+   BUFG phyclk2 (.O(CLK_TO_MAC_int2), .I(CLK_TO_MAC_int));
+      
    // FPGA-specific pins connections
-   wire 	aux_clk = PHY_CLK;
-
    wire 	clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
 
-   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
    defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
    
-   wire 	exp_pps_in;
-   IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
-   defparam 	exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+   wire 	exp_time_in;
+   IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n));
+   defparam 	exp_time_in_pin.IOSTANDARD = "LVDS_25";
+   
+   wire 	exp_time_out;
+   OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out));
+   defparam 	exp_time_out_pin.IOSTANDARD  = "LVDS_25";
+
+   wire 	exp_user_in;
+   IBUFDS exp_user_in_pin (.O(exp_user_in),.I(exp_user_in_p),.IB(exp_user_in_n));
+   defparam 	exp_user_in_pin.IOSTANDARD = "LVDS_25";
    
-   wire 	exp_pps_out;
-   OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
-   defparam 	exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+   wire 	exp_user_out;
+   OBUFDS exp_user_out_pin (.O(exp_user_out_p),.OB(exp_user_out_n),.I(exp_user_out));
+   defparam 	exp_user_out_pin.IOSTANDARD  = "LVDS_25";
 
    reg [5:0] 	clock_ready_d;
-   always @(posedge aux_clk)
+   always @(posedge clk_fpga)
      clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
-
    wire 	dcm_rst = ~&clock_ready_d & |clock_ready_d;
-   wire 	clk_muxed = clock_ready ? clk_fpga : aux_clk;
-
-   wire 	adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
-   assign 	adc_oen_a = ~adc_oe_a;
-   assign 	adc_oen_b = ~adc_oe_b;
-   assign 	adc_pdn_a = ~adc_on_a; 	
-   assign 	adc_pdn_b = ~adc_on_b; 	
 
+   // ADC A is inverted on the schematic to facilitate a clean layout
+   //  We account for that here by inverting it
+`ifdef LVDS
+   wire [13:0] 	adc_a, adc_a_inv, adc_b;
+   capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds
+     (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), 
+      .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p},
+	     {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), 
+      .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n},
+	     {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), 
+      .out({adc_a_inv,adc_b}));
+   assign adc_a = ~adc_a_inv;
+`else
+   reg [13:0] 	adc_a, adc_b;
+   always @(posedge dsp_clk)
+     begin
+	adc_a <= ~{ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n,
+		   ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n };
+	adc_b <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n,
+		   ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n };
+     end
+`endif // !`ifdef LVDS
+   
    // Handle Clocks
    DCM DCM_INST (.CLKFB(dsp_clk), 
-                 .CLKIN(clk_muxed), 
+                 .CLKIN(clk_fpga), 
                  .DSSEN(0), 
                  .PSCLK(0), 
                  .PSEN(0), 
@@ -180,7 +196,7 @@ module u2plus
                  .CLK2X180(), 
                  .CLK90(), 
                  .CLK180(), 
-                 .CLK270(), 
+                 .CLK270(clk270_100), 
                  .LOCKED(LOCKED_OUT), 
                  .PSDONE(), 
                  .STATUS());
@@ -202,28 +218,43 @@ module u2plus
    BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
    BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
 
+   // Create clock for external SRAM thats -90degree phase to DSPCLK (i.e) 2nS earlier at 100MHz.
+   BUFG  clk270_100_buf_i1 (.I(clk270_100), 
+			    .O(clk270_100_buf));
+   OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK),
+			.C0(clk270_100_buf),
+			.C1(~clk270_100_buf),
+			.CE(1'b1),
+			.D0(1'b1),
+			.D1(1'b0),
+			.R(1'b0),
+			.S(1'b0));
+  
    // I2C -- Don't use external transistors for open drain, the FPGA implements this
    IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
    IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
 
    // LEDs are active low outputs
-   wire [4:0] leds_int;
-   assign     leds = ~leds_int;  // drive low to turn on leds
+   wire [5:0] leds_int;
+   assign     {ETH_LED,leds} = {6'b011111 ^ leds_int};  // drive low to turn on leds
    
    // SPI
-   wire 	miso, mosi, sclk_int;
-   assign 	{sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
-   assign 	{sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
-   assign 	{sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
-   assign 	{sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
-   assign 	{sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
-   assign 	{sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
-   assign 	{sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
-   
-   assign 	miso = (~sen_clk & sdo) | (~sen_dac & sdo) | 
-		(~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
-		(~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+   wire       miso, mosi, sclk;
 
+   assign 	{SCLK_CLK,MOSI_CLK} 	   = ~SEN_CLK ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_DAC,MOSI_DAC} 	   = ~SEN_DAC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_ADC,MOSI_ADC} 	   = ~SEN_ADC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_TX_DB,MOSI_TX_DB}    = ~SEN_TX_DB ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_TX_DAC,MOSI_TX_DAC}  = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_TX_ADC,MOSI_TX_ADC}  = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_RX_DB,MOSI_RX_DB}    = ~SEN_RX_DB ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_RX_DAC,MOSI_RX_DAC}  = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_RX_ADC,MOSI_RX_ADC}  = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0;
+   
+   assign 	miso 			   = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) |
+					     (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) |
+					     (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC);
+   
    wire 	GMII_TX_EN_unreg, GMII_TX_ER_unreg;
    wire [7:0] 	GMII_TXD_unreg;
    wire 	GMII_GTX_CLK_int;
@@ -281,16 +312,53 @@ module u2plus
       .S(0)       // Synchronous preset input
       );
    */
-   u2_core u2_core(.dsp_clk           (dsp_clk),
+
+
+   //
+   // Instantiate IO for Bidirectional bus to SRAM
+   //
+   wire [35:0] RAM_D_pi;
+   wire [35:0] RAM_D_po;
+   wire        RAM_D_poe;
+   
+   genvar      i;
+   
+   generate  
+      for (i=0;i<36;i=i+1)
+        begin : gen_RAM_D_IO
+
+	   IOBUF #(
+		   .DRIVE(12),
+		   .IOSTANDARD("LVCMOS25"),
+		   .SLEW("FAST")
+		   )
+	     RAM_D_i (
+		      .O(RAM_D_pi[i]),
+		      .I(RAM_D_po[i]),
+		      .IO(RAM_D[i]),
+		      .T(RAM_D_poe)
+		      );
+	end // block: gen_RAM_D_IO
+   endgenerate
+
+   
+   
+   wire [15:0] dac_a_int, dac_b_int;
+   // DAC A and B are swapped in schematic to facilitate clean layout
+   // DAC A is also inverted in schematic to facilitate clean layout
+   always @(negedge dsp_clk) DACA <= ~dac_b_int;
+   always @(negedge dsp_clk) DACB <= dac_a_int;
+   
+   u2plus_core u2p_c(.dsp_clk           (dsp_clk),
 		     .wb_clk            (wb_clk),
 		     .clock_ready       (clock_ready),
-		     .clk_to_mac	(clk_to_mac),
-		     .pps_in		(pps_in),
+		     .clk_to_mac	(CLK_TO_MAC_int2),
+		     .pps_in		(PPS_IN),
 		     .leds		(leds_int),
 		     .debug		(debug[31:0]),
 		     .debug_clk		(debug_clk[1:0]),
-		     .exp_pps_in	(exp_pps_in),
-		     .exp_pps_out	(exp_pps_out),
+		     .exp_pps_in	(exp_time_in),
+		     .exp_pps_out	(exp_time_out),
 		     .GMII_COL		(GMII_COL),
 		     .GMII_CRS		(GMII_CRS),
 		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
@@ -306,7 +374,6 @@ module u2plus
 		     .MDC		(MDC),
 		     .PHY_INTn		(PHY_INTn),
 		     .PHY_RESETn	(PHY_RESETn),
-		     .PHY_CLK		(PHY_CLK),
 		     .ser_enable	(ser_enable),
 		     .ser_prbsen	(ser_prbsen),
 		     .ser_loopen	(ser_loopen),
@@ -319,22 +386,16 @@ module u2plus
 		     .ser_r		(ser_r_int[15:0]),
 		     .ser_rklsb		(ser_rklsb_int),
 		     .ser_rkmsb		(ser_rkmsb_int),
-		     .cpld_start        (cpld_start),
-		     .cpld_mode         (cpld_mode),
-		     .cpld_done         (cpld_done),
-		     .cpld_din          (cpld_din),
-		     .cpld_clk          (cpld_clk),
-		     .cpld_detached     (cpld_detached),
 		     .adc_a		(adc_a[13:0]),
-		     .adc_ovf_a		(adc_ovf_a),
-		     .adc_on_a		(adc_on_a),
-		     .adc_oe_a		(adc_oe_a),
+		     .adc_ovf_a		(1'b0),
+		     .adc_on_a		(),
+		     .adc_oe_a		(),
 		     .adc_b		(adc_b[13:0]),
-		     .adc_ovf_b		(adc_ovf_b),
-		     .adc_on_b		(adc_on_b),
-		     .adc_oe_b		(adc_oe_b),
-		     .dac_a		(dac_a[15:0]),
-		     .dac_b		(dac_b[15:0]),
+		     .adc_ovf_b		(1'b0),
+		     .adc_on_b		(),
+		     .adc_oe_b		(),
+		     .dac_a		(dac_a_int[15:0]),
+		     .dac_b		(dac_b_int[15:0]),
 		     .scl_pad_i		(scl_pad_i),
 		     .scl_pad_o		(scl_pad_o),
 		     .scl_pad_oen_o	(scl_pad_oen_o),
@@ -345,33 +406,45 @@ module u2plus
 		     .clk_sel		(clk_sel[1:0]),
 		     .clk_func		(clk_func),
 		     .clk_status	(clk_status),
-		     .sclk		(sclk_int),
+		     .sclk		(sclk),
 		     .mosi		(mosi),
 		     .miso		(miso),
-		     .sen_clk		(sen_clk),
-		     .sen_dac		(sen_dac),
-		     .sen_tx_db		(sen_tx_db),
-		     .sen_tx_adc	(sen_tx_adc),
-		     .sen_tx_dac	(sen_tx_dac),
-		     .sen_rx_db		(sen_rx_db),
-		     .sen_rx_adc	(sen_rx_adc),
-		     .sen_rx_dac	(sen_rx_dac),
+		     .sen_clk		(SEN_CLK),
+		     .sen_dac		(SEN_DAC),
+		     .sen_adc           (SEN_ADC),
+		     .sen_tx_db		(SEN_TX_DB),
+		     .sen_tx_adc	(SEN_TX_ADC),
+		     .sen_tx_dac	(SEN_TX_DAC),
+		     .sen_rx_db		(SEN_RX_DB),
+		     .sen_rx_adc	(SEN_RX_ADC),
+		     .sen_rx_dac	(SEN_RX_DAC),
 		     .io_tx		(io_tx[15:0]),
 		     .io_rx		(io_rx[15:0]),
-		     .RAM_D             (RAM_D),
+		     .RAM_D_po          (RAM_D_po),
+		     .RAM_D_pi          (RAM_D_pi),
+		     .RAM_D_poe         (RAM_D_poe),
 		     .RAM_A             (RAM_A),
 		     .RAM_CE1n          (RAM_CE1n),
 		     .RAM_CENn          (RAM_CENn),
-		     .RAM_CLK           (RAM_CLK),
 		     .RAM_WEn           (RAM_WEn),
 		     .RAM_OEn           (RAM_OEn),
 		     .RAM_LDn           (RAM_LDn), 
-		     .uart_tx_o         (uart_tx_o),
-		     //.uart_rx_i         (uart_rx_i),
-		     .uart_rx_i         (),
+		     .uart_tx_o         (TXD[3:1]),
+		     .uart_rx_i         ({1'b1,RXD[3:1]}),
 		     .uart_baud_o       (),
 		     .sim_mode          (1'b0),
-		     .clock_divider     (2)
+		     .clock_divider     (2),
+		     .button            (FPGA_RESET),
+		     .spiflash_cs       (flash_cs),
+		     .spiflash_clk      (flash_clk),
+		     .spiflash_miso     (flash_miso),
+		     .spiflash_mosi     (flash_mosi)
 		     );
+
+   // Drive low so that RAM does not sleep.
+   assign RAM_ZZ = 0;
+   // Byte Writes are qualified by the global write enable
+   // Always do 36bit operations to extram.
+   assign RAM_BWn = 4'b0000;
    
 endmodule // u2plus
diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v
new file mode 100644
index 000000000..8426826e2
--- /dev/null
+++ b/fpga/usrp2/top/u2plus/u2plus_core.v
@@ -0,0 +1,696 @@
+// ////////////////////////////////////////////////////////////////////////////////
+// Module Name:    u2_core
+// ////////////////////////////////////////////////////////////////////////////////
+
+module u2plus_core
+  (// Clocks
+   input dsp_clk,
+   input wb_clk,
+   output clock_ready,
+   input clk_to_mac,
+   input pps_in,
+   
+   // Misc, debug
+   output [7:0] leds,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+
+   // Expansion
+   input exp_pps_in,
+   output exp_pps_out,
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output [7:0] GMII_TXD,
+   output GMII_TX_EN,
+   output GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output [15:0] ser_t,
+   output ser_tklsb,
+   output ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   input por,
+   output config_success,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_on_a,
+   output adc_oe_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_on_b,
+   output adc_oe_b,
+   
+   // DAC
+   output [15:0] dac_a,
+   output [15:0] dac_b,
+
+   // I2C
+   input scl_pad_i,
+   output scl_pad_o,
+   output scl_pad_oen_o,
+   input sda_pad_i,
+   output sda_pad_o,
+   output sda_pad_oen_o,
+   
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Generic SPI
+   output sclk,
+   output mosi,
+   input miso,
+   output sen_clk,
+   output sen_dac,
+   output sen_adc,
+   output sen_tx_db,
+   output sen_tx_adc,
+   output sen_tx_dac,
+   output sen_rx_db,
+   output sen_rx_adc,
+   output sen_rx_dac,
+   
+   // GPIO to DBoards
+   inout [15:0] io_tx,
+   inout [15:0] io_rx,
+
+   // External RAM
+   input [35:0] RAM_D_pi,
+   output [35:0] RAM_D_po,
+   output RAM_D_poe,   
+   output [20:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // Debug stuff
+   output [3:0] uart_tx_o, 
+   input [3:0] uart_rx_i,
+   output [3:0] uart_baud_o,
+   input sim_mode,
+   input [3:0] clock_divider,
+   input button,
+   
+   output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi
+   );
+
+   localparam SR_BUF_POOL = 64;   // Uses 1 reg
+   localparam SR_UDP_SM   = 96;   // 64 regs
+   localparam SR_RX_DSP   = 160;  // 16
+   localparam SR_RX_CTRL  = 176;  // 16
+   localparam SR_TIME64   = 192;  //  3
+   localparam SR_SIMTIMER = 198;  //  2
+   localparam SR_TX_DSP   = 208;  // 16
+   localparam SR_TX_CTRL  = 224;  // 16
+
+   // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048
+   // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
+   localparam DSP_TX_FIFOSIZE = 10;
+   localparam DSP_RX_FIFOSIZE = 10;
+   localparam ETH_TX_FIFOSIZE = 10;
+   localparam ETH_RX_FIFOSIZE = 11;
+   localparam SERDES_TX_FIFOSIZE = 9;
+   localparam SERDES_RX_FIFOSIZE = 9;  // RX currently doesn't use a fifo?
+   
+   wire [7:0] 	set_addr, set_addr_dsp;
+   wire [31:0] 	set_data, set_data_dsp;
+   wire 	set_stb, set_stb_dsp;
+   
+   wire 	wb_rst, dsp_rst;
+
+   wire [31:0] 	status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
+   wire 	bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int;
+   wire 	proc_int, overrun, underrun;
+   wire [3:0] 	uart_tx_int, uart_rx_int;
+
+   wire [31:0] 	debug_gpio_0, debug_gpio_1;
+   wire [31:0] 	atr_lines;
+
+   wire [31:0] 	debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
+		debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp;
+
+   wire [15:0] 	ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
+   wire 	ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
+   wire 	ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2;
+	
+   wire 	serdes_link_up;
+   wire 	epoch;
+   wire [31:0] 	irq;
+   wire [63:0] 	vita_time;
+   wire 	run_rx, run_tx;
+   
+   // ///////////////////////////////////////////////////////////////////////////////////////////////
+   // Wishbone Single Master INTERCON
+   localparam 	dw = 32;  // Data bus width
+   localparam 	aw = 16;  // Address bus width, for byte addressibility, 16 = 64K byte memory space
+   localparam	sw = 4;   // Select width -- 32-bit data bus with 8-bit granularity.  
+   
+   wire [dw-1:0] m0_dat_o, m0_dat_i;
+   wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
+		 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
+		 s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o,
+		 sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o;
+   wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr;
+   wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel;
+   wire 	 m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack;
+   wire 	 m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb;
+   wire 	 m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc;
+   wire 	 m0_err, m0_rty;
+   wire 	 m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we;
+   
+   wb_1master #(.decode_w(8),
+		.s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000),  // 0-8K, Boot RAM
+		.s1_addr(8'b0100_0000),.s1_mask(8'b1100_0000),  // 16K-32K, Buffer Pool
+ 		.s2_addr(8'b0011_0000),.s2_mask(8'b1111_1111),  // SPI
+		.s3_addr(8'b0011_0001),.s3_mask(8'b1111_1111),  // I2C
+		.s4_addr(8'b0011_0010),.s4_mask(8'b1111_1111),  // GPIO
+		.s5_addr(8'b0011_0011),.s5_mask(8'b1111_1111),  // Readback
+		.s6_addr(8'b0011_0100),.s6_mask(8'b1111_1111),  // Ethernet MAC
+		.s7_addr(8'b0010_0000),.s7_mask(8'b1111_0000),  // 8-12K, Settings Bus (only uses 1K)
+		.s8_addr(8'b0011_0101),.s8_mask(8'b1111_1111),  // PIC
+		.s9_addr(8'b0011_0110),.s9_mask(8'b1111_1111),  // Unused
+		.sa_addr(8'b0011_0111),.sa_mask(8'b1111_1111),  // UART
+		.sb_addr(8'b0011_1000),.sb_mask(8'b1111_1111),  // ATR
+		.sc_addr(8'b0011_1001),.sc_mask(8'b1111_1111),  // Unused
+		.sd_addr(8'b0011_1010),.sd_mask(8'b1111_1111),  // ICAP
+		.se_addr(8'b0011_1011),.se_mask(8'b1111_1111),  // SPI Flash
+		.sf_addr(8'b1000_0000),.sf_mask(8'b1000_0000),  // 32-64K, Main RAM
+		.dw(dw),.aw(aw),.sw(sw)) wb_1master
+     (.clk_i(wb_clk),.rst_i(wb_rst),       
+      .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
+      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+      .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o	(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+      .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
+      .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o	(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+      .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
+      .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o	(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+      .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
+      .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o	(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+      .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
+      .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o	(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+      .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
+      .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o	(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+      .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
+      .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o	(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+      .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
+      .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o	(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+      .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
+      .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o	(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
+      .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
+      .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o	(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
+      .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
+      .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
+      .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
+      .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
+      .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
+      .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
+      .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
+      .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
+      .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
+      .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
+      .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
+      .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
+      .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0));
+      
+   //////////////////////////////////////////////////////////////////////////////////////////
+   // Reset Controller
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Processor
+   wire [31:0] 	 if_dat;
+   wire [15:0] 	 if_adr;
+
+   aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
+     aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
+	   // Instruction Wishbone bus to I-RAM
+	   .if_adr(if_adr),
+	   .if_dat(if_dat),
+	   // Data Wishbone bus to system bus fabric
+	   .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
+	   .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
+	   // Interrupts and exceptions
+	   .sys_int_i(proc_int),.sys_exc_i(bus_error) );
+   
+   assign 	 bus_error = m0_err | m0_rty;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone
+   // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone
+   // I-port connects directly to processor
+
+   wire [31:0] 	 if_dat_boot, if_dat_main;
+   assign if_dat = if_adr[15] ? if_dat_main : if_dat_boot;
+   
+   bootram bootram(.clk(wb_clk), .reset(wb_rst),
+		   .if_adr(if_adr[12:0]), .if_data(if_dat_boot), 
+		   .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
+		   .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel));
+
+////blinkenlights v0.1
+//defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000;
+//defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001;
+
+`include "bootloader.rmi"
+
+   ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(32768))
+   sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),	     
+	   .if_adr(if_adr[14:0]), .if_data(if_dat_main), 
+	   .dwb_adr_i(sf_adr[14:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i),
+	   .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Buffer Pool, slave #1
+   wire 	 rd0_ready_i, rd0_ready_o;
+   wire 	 rd1_ready_i, rd1_ready_o;
+   wire 	 rd2_ready_i, rd2_ready_o;
+   wire 	 rd3_ready_i, rd3_ready_o;
+   wire [3:0] 	 rd0_flags, rd1_flags, rd2_flags, rd3_flags;
+   wire [31:0] 	 rd0_dat, rd1_dat, rd2_dat, rd3_dat;
+
+   wire 	 wr0_ready_i, wr0_ready_o;
+   wire 	 wr1_ready_i, wr1_ready_o;
+   wire 	 wr2_ready_i, wr2_ready_o;
+   wire 	 wr3_ready_i, wr3_ready_o;
+   wire [3:0] 	 wr0_flags, wr1_flags, wr2_flags, wr3_flags;
+   wire [31:0] 	 wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+   
+   buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+      .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),   
+      .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
+   
+      .stream_clk(dsp_clk), .stream_rst(dsp_rst),
+      .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+      .status(status),.sys_int_o(buffer_int),
+
+      .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
+      .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
+
+      // Write Interfaces
+      .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o),
+      .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o),
+      .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o),
+      .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o),
+      // Read Interfaces
+      .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o),
+      .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o),
+      .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o),
+      .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o)
+      );
+
+   wire [31:0] 	 status_enc;
+   priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // SPI -- Slave #2
+   spi_top shared_spi
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
+      .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
+      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int),
+      .ss_pad_o({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+      .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // I2C -- Slave #3
+   i2c_master_top #(.ARST_LVL(1)) 
+     i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
+	  .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
+	  .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+	  .wb_ack_o(s3_ack),.wb_inta_o(i2c_int),
+	  .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+	  .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+   assign 	 s3_dat_i[31:8] = 24'd0;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // GPIOs -- Slave #4
+   nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
+		 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
+		 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
+		 .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+		 .gpio({io_tx,io_rx}) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Buffer Pool Status -- Slave #5   
+   
+   reg [31:0] 	 cycle_count;
+   always @(posedge wb_clk)
+     if(wb_rst)
+       cycle_count <= 0;
+     else
+       cycle_count <= cycle_count + 1;
+
+   //compatibility number -> increment when the fpga has been sufficiently altered
+   localparam compat_num = 32'd3;
+
+   wb_readback_mux buff_pool_status
+     (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
+      .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
+      
+      .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
+      .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
+      .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
+      .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count)
+      );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Ethernet MAC  Slave #6
+
+   wire [18:0] 	 rx_f19_data, tx_f19_data;
+   wire 	 rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy;
+   
+   simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
+     (.clk125(clk_to_mac),  .reset(wb_rst),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .sys_clk(dsp_clk),
+      .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
+      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
+      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
+      .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
+      .mdio(MDIO), .mdc(MDC),
+      .debug(debug_mac));
+
+   wire [35:0] 	 udp_tx_data, udp_rx_data;
+   wire 	 udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy;
+   
+   udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+      .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy),
+      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy),
+      .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy),
+      .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy),
+      .debug(debug_udp) );
+
+   wire [35:0] 	 tx_err_data, udp1_tx_data;
+   wire 	 tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy;
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
+      .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy));
+
+   fifo36_mux #(.prio(0)) mux_err_stream
+     (.clk(dsp_clk), .reset(dsp_reset), .clear(0),
+      .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy),
+      .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
+      .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy));
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy),
+      .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Settings Bus -- Slave #7
+   settings_bus settings_bus
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
+      .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
+      .strobe(set_stb),.addr(set_addr),.data(set_data));
+   
+   assign 	 s7_dat_i = 32'd0;
+
+   settings_bus_crossclock settings_bus_crossclock
+     (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data),
+      .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp));
+   
+   // Output control lines
+   wire [7:0] 	 clock_outs, serdes_outs, adc_outs;
+   assign 	 {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
+   assign 	 {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
+   assign 	 {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0];
+
+   wire 	 phy_reset;
+   assign 	 PHY_RESETn = ~phy_reset;
+   
+   setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
+				      .in(set_data),.out(clock_outs),.changed());
+   setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(serdes_outs),.changed());
+   setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(adc_outs),.changed());
+   setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(phy_reset),.changed());
+
+   // /////////////////////////////////////////////////////////////////////////
+   //  LEDS
+   //    register 8 determines whether leds are controlled by SW or not
+   //    1 = controlled by HW, 0 = by SW
+   //    In Rev3 there are only 6 leds, and the highest one is on the ETH connector
+   
+   wire [7:0] 	 led_src, led_sw;
+   wire [7:0] 	 led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0};
+   
+   setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(led_sw),.changed());
+
+   setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110)) 
+   sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed());
+
+   assign 	 leds = (led_src & led_hw) | (~led_src & led_sw);
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Interrupt Controller, Slave #8
+
+   // Pass interrupts on dsp_clk to wb_clk.  These need edge triggering in the pic
+   wire 	 underrun_wb, overrun_wb, pps_wb;
+
+   oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb));
+   oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb));
+   oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb));
+   
+   assign irq= {{8'b0},
+		{uart_tx_int[3:0], uart_rx_int[3:0]},
+		{2'b0, button, periodic_int, clk_status, serdes_link_up, 2'b00},
+		{pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}};
+   
+   pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]),
+	   .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
+	   .irq(irq) );
+ 	 
+   // /////////////////////////////////////////////////////////////////////////
+   // Master Timer, Slave #9
+
+   // No longer used, replaced with simple_timer below
+   assign s9_ack = 0;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   //  Simple Timer interrupts
+   
+   simple_timer #(.BASE(SR_SIMTIMER)) simple_timer
+     (.clk(wb_clk), .reset(wb_rst),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .onetime_int(onetime_int), .periodic_int(periodic_int));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // UART, Slave #10
+
+   quad_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart  // depth of 3 is 128 entries
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack),
+      .adr_i(sa_adr[6:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i),
+      .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
+      .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // ATR Controller, Slave #11
+
+   reg 		 run_rx_d1;
+   always @(posedge dsp_clk)
+     run_rx_d1 <= run_rx;
+   
+   atr_controller atr_controller
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i),
+      .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack),
+      .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
+   
+   // //////////////////////////////////////////////////////////////////////////
+   // Time Sync, Slave #12 
+
+   // No longer used, see time_64bit.  Still need to handle mimo time, though
+   assign sc_ack = 0;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // ICAP for reprogramming the FPGA, Slave #13 (D)
+
+   s3a_icap_wb s3a_icap_wb
+     (.clk(wb_clk), .reset(wb_rst), .cyc_i(sd_cyc), .stb_i(sd_stb), 
+      .we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // SPI for Flash -- Slave #14 (E)
+   spi_top flash_spi
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(se_adr[4:0]),.wb_dat_i(se_dat_o),
+      .wb_dat_o(se_dat_i),.wb_sel_i(se_sel),.wb_we_i(se_we),.wb_stb_i(se_stb),
+      .wb_cyc_i(se_cyc),.wb_ack_o(se_ack),.wb_err_o(se_err),.wb_int_o(spiflash_int),
+      .ss_pad_o(spiflash_cs),
+      .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // DSP RX
+   wire [31:0] 	 sample_rx, sample_tx;
+   wire 	 strobe_rx, strobe_tx;
+   wire 	 rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy;
+   wire [99:0] 	 rx_data;
+   wire [35:0] 	 rx1_data;
+   
+   dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
+      .debug(debug_rx_dsp) );
+
+   wire [31:0] 	 vrc_debug;
+   wire 	 clear_rx;
+   
+   setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
+      .out(),.changed(clear_rx));
+
+   vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .vita_time(vita_time), .overrun(overrun),
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy),
+      .debug_rx(vrc_debug));
+
+   wire [3:0] 	 vita_state;
+   
+   vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy),
+      .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy),
+      .fifo_occupied(), .fifo_full(), .fifo_empty(),
+      .debug_rx(vita_state) );
+
+   fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
+      .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
+      .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
+
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // DSP TX
+
+   wire [35:0] 	 tx_data;
+   wire 	 tx_src_rdy, tx_dst_rdy;
+   wire [31:0] 	 debug_vt;
+   wire 	 clear_tx;
+
+   setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(clear_tx));
+
+   assign 	 RAM_A[20:18] = 3'b0;
+   
+   ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18)) 
+     ext_fifo_i1
+       (.int_clk(dsp_clk),
+	.ext_clk(dsp_clk),
+	.rst(dsp_rst | clear_tx),
+	.RAM_D_pi(RAM_D_pi),
+	.RAM_D_po(RAM_D_po),
+	.RAM_D_poe(RAM_D_poe),
+	.RAM_A(RAM_A[17:0]),
+	.RAM_WEn(RAM_WEn),
+	.RAM_CENn(RAM_CENn),
+	.RAM_LDn(RAM_LDn),
+	.RAM_OEn(RAM_OEn),
+	.RAM_CE1n(RAM_CE1n),
+	.datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}),
+	.src_rdy_i(rd1_ready_o),
+	.dst_rdy_o(rd1_ready_i),
+	.dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}),
+	.src_rdy_o(tx_src_rdy),
+	.dst_rdy_i(tx_dst_rdy),
+	.debug(debug_extfifo),
+	.debug2(debug_extfifo2) );
+
+   vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
+		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
+		   .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) 
+   vita_tx_chain
+     (.clk(dsp_clk), .reset(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .vita_time(vita_time),
+      .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
+      .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
+      .dac_a(dac_a),.dac_b(dac_b),
+      .underrun(underrun), .run(run_tx),
+      .debug(debug_vt));
+   
+   assign dsp_rst = wb_rst;
+
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // SERDES
+
+   serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+      .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o),
+      .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+      .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o),
+      .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
+      .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
+      .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // VITA Timing
+
+   time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
+     (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
+   
+   // /////////////////////////////////////////////////////////////////////////////////////////
+   // Debug Pins
+  
+   assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac};
+   assign debug = 32'd0; // debug_extfifo;
+   assign debug_gpio_0 = 32'd0;
+   assign debug_gpio_1 = 32'd0;
+   
+endmodule // u2_core
diff --git a/fpga/usrp2/vrt/gen_context_pkt.v b/fpga/usrp2/vrt/gen_context_pkt.v
index 0eb035f3e..bf83aeae5 100644
--- a/fpga/usrp2/vrt/gen_context_pkt.v
+++ b/fpga/usrp2/vrt/gen_context_pkt.v
@@ -7,8 +7,7 @@ module gen_context_pkt
     input [31:0] streamid,
     input [63:0] vita_time,
     input [31:0] message,
-    input [31:0] seqnum0,
-    input [31:0] seqnum1,
+    input [31:0] seqnum,
     output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
    
    localparam CTXT_IDLE = 0;
@@ -19,9 +18,8 @@ module gen_context_pkt
    localparam CTXT_TICS = 5;
    localparam CTXT_TICS2 = 6;
    localparam CTXT_MESSAGE = 7;
-   localparam CTXT_FLOWCTRL0 = 8;
-   localparam CTXT_FLOWCTRL1 = 9;
-   localparam CTXT_DONE = 10;
+   localparam CTXT_FLOWCTRL = 8;
+   localparam CTXT_DONE = 9;
 
    reg [33:0] 	 data_int;
    wire 	 src_rdy_int, dst_rdy_int;
@@ -36,11 +34,12 @@ module gen_context_pkt
      else
        if(trigger)
 	 stored_message <= message;
-       else if(ctxt_state == CTXT_FLOWCTRL1)
+       else if(ctxt_state == CTXT_DONE)
 	 stored_message <= 0;
-   
+
+   // Don't want to clear most of this to avoid getting stuck with a half packet in the pipe
    always @(posedge clk)
-     if(reset | clear)
+     if(reset)
        begin
 	  ctxt_state <= CTXT_IDLE;
 	  seqno <= 0;
@@ -72,19 +71,18 @@ module gen_context_pkt
    always @*
      case(ctxt_state)
        CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd32 };
-       CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd8 };
+       CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 };
        CTXT_STREAMID : data_int <= { 2'b00, streamid };
        CTXT_SECS : data_int <= { 2'b00, err_time[63:32] };
        CTXT_TICS : data_int <= { 2'b00, 32'd0 };
        CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] };
        CTXT_MESSAGE : data_int <= { 2'b00, message };
-       CTXT_FLOWCTRL0 : data_int <= { 2'b00, seqnum0 };
-       CTXT_FLOWCTRL1 : data_int <= { 2'b10, seqnum1 };
+       CTXT_FLOWCTRL : data_int <= { 2'b10, seqnum };
        default : data_int <= {2'b00, 32'b00};
      endcase // case (ctxt_state)
 
    fifo_short #(.WIDTH(34)) ctxt_fifo
-     (.clk(clk), .reset(reset), .clear(clear),
+     (.clk(clk), .reset(reset), .clear(0),
       .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
       .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
    assign data_o[35:34] = 2'b00;
diff --git a/fpga/usrp2/vrt/vita_rx_control.v b/fpga/usrp2/vrt/vita_rx_control.v
index 93673d292..0769f3a24 100644
--- a/fpga/usrp2/vrt/vita_rx_control.v
+++ b/fpga/usrp2/vrt/vita_rx_control.v
@@ -9,7 +9,7 @@ module vita_rx_control
     output overrun,
 
     // To vita_rx_framer
-    output [4+64+WIDTH-1:0] sample_fifo_o,
+    output [5+64+WIDTH-1:0] sample_fifo_o,
     output sample_fifo_src_rdy_o,
     input sample_fifo_dst_rdy_i,
     
@@ -25,16 +25,14 @@ module vita_rx_control
    
    wire [63:0] 	  new_time;
    wire [31:0] 	  new_command;
-   wire 	  sc_pre1, clear_int, clear_reg;
+   wire 	  sc_pre1;
 
-   assign clear_int  = clear | clear_reg;
-   
    wire [63:0] 	  rcvtime_pre;
    reg [63:0] 	  rcvtime;
    wire [28:0] 	  numlines_pre;
    wire 	  send_imm_pre, chain_pre, reload_pre;
    reg 		  send_imm, chain, reload;
-   wire 	  full_ctrl, read_ctrl, empty_ctrl, write_ctrl;
+   wire 	  read_ctrl, not_empty_ctrl, write_ctrl;
    reg 		  sc_pre2;
    wire [33:0] 	  fifo_line;
    reg [28:0] 	  lines_left, lines_total;
@@ -54,21 +52,22 @@ module vita_rx_control
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(new_time[31:0]),.changed(sc_pre1));
    
-   setting_reg #(.my_addr(BASE+3)) sr_clear
-     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_reg));
-
    // FIFO to store commands sent from the settings bus
    always @(posedge clk)
-     sc_pre2 		  <= sc_pre1;
+     if(reset | clear)
+       sc_pre2 <= 0;
+     else
+       sc_pre2 <= sc_pre1;
+   
    assign      write_ctrl  = sc_pre1 & ~sc_pre2;
 
    wire [4:0]  command_queue_len;
-   shortfifo #(.WIDTH(96)) commandfifo
-     (.clk(clk),.rst(reset),.clear(clear_int),
-      .datain({new_command,new_time}), .write(write_ctrl&~full_ctrl), .full(full_ctrl),
+
+   fifo_short #(.WIDTH(96)) commandfifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain({new_command,new_time}), .src_rdy_i(write_ctrl), .dst_rdy_o(),
       .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}),
-      .read(read_ctrl), .empty(empty_ctrl),
+      .src_rdy_o(not_empty_ctrl), .dst_rdy_i(read_ctrl),
       .occupied(command_queue_len), .space() );
    
    reg [33:0]  pkt_fifo_line;
@@ -79,20 +78,23 @@ module vita_rx_control
    localparam IBS_OVERRUN = 4;
    localparam IBS_BROKENCHAIN = 5;
    localparam IBS_LATECMD = 6;
-
-   wire signal_cmd_done     = (lines_left == 1) & (~chain | (~empty_ctrl & (numlines_pre==0)));
+   localparam IBS_ZEROLEN = 7;
+   
+   wire signal_cmd_done     = (lines_left == 1) & (~chain | (not_empty_ctrl & (numlines_pre==0)));
    wire signal_overrun 	    = (ibs_state == IBS_OVERRUN);
    wire signal_brokenchain  = (ibs_state == IBS_BROKENCHAIN);
    wire signal_latecmd 	    = (ibs_state == IBS_LATECMD);
+   wire signal_zerolen 	    = (ibs_state == IBS_ZEROLEN);
 
    // Buffer of samples for while we're writing the packet headers
-   wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
+   wire [4:0] flags = {signal_zerolen,signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
 
    wire       attempt_sample_write    = ((run & strobe) | (ibs_state==IBS_OVERRUN) |
-				       (ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD));
+					 (ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD) |
+					 (ibs_state==IBS_ZEROLEN));
    
-   fifo_short #(.WIDTH(4+64+WIDTH)) rx_sample_fifo
-     (.clk(clk),.reset(reset),.clear(clear_int),
+   fifo_short #(.WIDTH(5+64+WIDTH)) rx_sample_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
       .datain({flags,vita_time,sample}), .src_rdy_i(attempt_sample_write), .dst_rdy_o(sample_fifo_in_rdy),
       .dataout(sample_fifo_o), 
       .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i),
@@ -107,7 +109,7 @@ module vita_rx_control
    wire full 		    = ~sample_fifo_in_rdy;
    
    always @(posedge clk)
-     if(reset | clear_int)
+     if(reset | clear)
        begin
 	  ibs_state 	   <= IBS_IDLE;
 	  lines_left 	   <= 0;
@@ -120,12 +122,15 @@ module vita_rx_control
      else
        case(ibs_state)
 	 IBS_IDLE :
-	   if(~empty_ctrl)
+	   if(not_empty_ctrl)
 	     begin
 		lines_left <= numlines_pre;
 		lines_total <= numlines_pre;
 		rcvtime <= rcvtime_pre;
-		ibs_state <= IBS_WAITING;
+		if(numlines_pre == 0)
+		  ibs_state <= IBS_ZEROLEN;
+		else
+		  ibs_state <= IBS_WAITING;
 		send_imm <= send_imm_pre;
 		chain <= chain_pre;
 		reload <= reload_pre;
@@ -145,12 +150,12 @@ module vita_rx_control
 		  if(lines_left == 1)
 		    if(~chain)
 		      ibs_state      <= IBS_IDLE;
-		    else if(empty_ctrl & reload)
+		    else if(~not_empty_ctrl & reload)
 		      begin
 		        ibs_state      <= IBS_RUNNING;
 		        lines_left     <= lines_total;
 		      end
-		    else if(empty_ctrl)
+		    else if(~not_empty_ctrl)
 		      ibs_state      <= IBS_BROKENCHAIN;
 		    else
 		      begin
@@ -175,17 +180,20 @@ module vita_rx_control
 	 IBS_BROKENCHAIN :
 	   if(sample_fifo_in_rdy)
 	     ibs_state <= IBS_IDLE;
+	 IBS_ZEROLEN :
+	   if(sample_fifo_in_rdy)
+	     ibs_state <= IBS_IDLE;
        endcase // case(ibs_state)
    
    assign overrun = (ibs_state == IBS_OVERRUN);
    assign run = (ibs_state == IBS_RUNNING);
 
    assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) )
-     & ~empty_ctrl;
+     & not_empty_ctrl;
    
    assign debug_rx = { { ibs_state[2:0], command_queue_len },
 		       { 8'd0 },
-		       { go_now, too_late, run, strobe, read_ctrl, write_ctrl, full_ctrl, empty_ctrl },
+		       { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl },
 		       { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} };
    
 endmodule // rx_control
diff --git a/fpga/usrp2/vrt/vita_rx_framer.v b/fpga/usrp2/vrt/vita_rx_framer.v
index 235817941..bce8fe334 100644
--- a/fpga/usrp2/vrt/vita_rx_framer.v
+++ b/fpga/usrp2/vrt/vita_rx_framer.v
@@ -11,7 +11,7 @@ module vita_rx_framer
     output src_rdy_o,
     
     // From vita_rx_control
-    input [4+64+(32*MAXCHAN)-1:0] sample_fifo_i,
+    input [5+64+(32*MAXCHAN)-1:0] sample_fifo_i,
     input sample_fifo_src_rdy_i,
     output sample_fifo_dst_rdy_o,
     
@@ -23,11 +23,11 @@ module vita_rx_framer
     output [31:0] debug_rx
     );
 
-   localparam SAMP_WIDTH  = 4+64+(32*MAXCHAN);
+   localparam SAMP_WIDTH  = 5+64+(32*MAXCHAN);
    reg [3:0] 	  sample_phase;
    wire [3:0] 	  numchan;
-   wire [3:0] 	  flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-4];
-   wire [63:0] 	  vita_time_fifo_o = sample_fifo_i[SAMP_WIDTH-5:SAMP_WIDTH-68];
+   wire [4:0] 	  flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-5];
+   wire [63:0] 	  vita_time_fifo_o = sample_fifo_i[SAMP_WIDTH-6:SAMP_WIDTH-69];
 
    reg [31:0] 	  data_fifo_o;
 
@@ -55,14 +55,7 @@ module vita_rx_framer
    reg [3:0] 	  pkt_count;
    
    wire [15:0] 	  vita_pkt_len = samples_per_packet + 6;
-   //wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
-
-   wire 	  clear_reg;
-   wire 	  clear_int  = clear | clear_reg;
-
-   setting_reg #(.my_addr(BASE+3)) sr_clear
-     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_reg));
+   //wire [4:0] flags = {signal_zerolen,signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
 
    setting_reg #(.my_addr(BASE+4)) sr_header
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
@@ -76,11 +69,11 @@ module vita_rx_framer
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(vita_trailer),.changed());
 
-   setting_reg #(.my_addr(BASE+7)) sr_samples_per_pkt
+   setting_reg #(.my_addr(BASE+7),.width(16)) sr_samples_per_pkt
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(samples_per_packet),.changed());
 
-   setting_reg #(.my_addr(BASE+8), .at_reset(1)) sr_numchan
+   setting_reg #(.my_addr(BASE+8),.width(4), .at_reset(1)) sr_numchan
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(numchan),.changed());
 
@@ -102,7 +95,7 @@ module vita_rx_framer
    localparam VITA_ERR_TRAILER 	 = 15; // Extension context packets have no trailer
       
    always @(posedge clk)
-     if(reset | clear_pkt_count)
+     if(reset | clear | clear_pkt_count)
        pkt_count <= 0;
      else if((vita_state == VITA_TRAILER) & pkt_fifo_rdy)
        pkt_count <= pkt_count + 1;
@@ -114,7 +107,8 @@ module vita_rx_framer
    always @*
      case(vita_state)
        // Data packets are IF Data packets with or w/o streamid, no classid, with trailer
-       VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:20],pkt_count,vita_pkt_len};
+       VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:24],
+				       vita_header[23:20],pkt_count[3:0],vita_pkt_len[15:0]};
        VITA_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
        VITA_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
        VITA_TICS : pkt_fifo_line <= {2'b00,32'd0};
@@ -128,14 +122,14 @@ module vita_rx_framer
        VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
        VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
        VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
-       VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,28'd0,flags_fifo_o};
+       VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,27'd0,flags_fifo_o};
        //VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
        
        default : pkt_fifo_line <= 34'h0_FFFF_FFFF;
        endcase // case (vita_state)
 
    always @(posedge clk)
-     if(reset)
+     if(reset | clear)
        begin
 	  vita_state   <= VITA_IDLE;
 	  sample_ctr   <= 0;
@@ -147,7 +141,7 @@ module vita_rx_framer
 	    sample_ctr <= 1;
 	    sample_phase <= 0;
 	    if(sample_fifo_src_rdy_i)
-	      if(|flags_fifo_o[3:1])
+	      if(|flags_fifo_o[4:1])
 		vita_state <= VITA_ERR_HEADER;
 	      else
 		vita_state <= VITA_HEADER;
@@ -192,7 +186,7 @@ module vita_rx_framer
 	 req_write_pkt_fifo <= 1;
        VITA_PAYLOAD :
 	 // Write if sample ready and no error flags
-     	 req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[3:1]);
+     	 req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[4:1]);
        VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD :
 	 req_write_pkt_fifo <= 1;
        default :
@@ -203,7 +197,7 @@ module vita_rx_framer
    
    // Short FIFO to buffer between us and the FIFOs outside
    fifo_short #(.WIDTH(34)) rx_pkt_fifo 
-     (.clk(clk), .reset(reset), .clear(clear_int),
+     (.clk(clk), .reset(reset), .clear(clear),
       .datain(pkt_fifo_line), .src_rdy_i(req_write_pkt_fifo), .dst_rdy_o(pkt_fifo_rdy),
       .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
       .space(),.occupied(fifo_occupied[4:0]) );
@@ -212,7 +206,7 @@ module vita_rx_framer
    assign sample_fifo_dst_rdy_o  = pkt_fifo_rdy & 
 				   ( ((vita_state==VITA_PAYLOAD) & 
 				      (sample_phase == (numchan-4'd1)) & 
-				      ~|flags_fifo_o[3:1]) |
+				      ~|flags_fifo_o[4:1]) |
 				     (vita_state==VITA_ERR_PAYLOAD));
    
    assign debug_rx  = vita_state;
diff --git a/fpga/usrp2/vrt/vita_rx_tb.v b/fpga/usrp2/vrt/vita_rx_tb.v
index 3e01e2ee2..023934f39 100644
--- a/fpga/usrp2/vrt/vita_rx_tb.v
+++ b/fpga/usrp2/vrt/vita_rx_tb.v
@@ -37,7 +37,7 @@ module vita_rx_tb;
    
    wire        sample_dst_rdy, sample_src_rdy;
    //wire [99:0] sample_data_o;
-   wire [64+4+(MAXCHAN*32)-1:0] sample_data_o;
+   wire [64+5+(MAXCHAN*32)-1:0] sample_data_o;
 
    vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control
      (.clk(clk), .reset(reset), .clear(0),
@@ -92,58 +92,68 @@ module vita_rx_tb;
      begin
 	@(negedge reset);
 	@(posedge clk);
-	write_setting(4,32'hDEADBEEF);  // VITA header
+	write_setting(4,32'h15F00000);  // VITA header
 	write_setting(5,32'hF00D1234);  // VITA streamid
-	write_setting(6,32'hF0000000);  // VITA trailer
+	write_setting(6,32'hE0000000);  // VITA trailer
 	write_setting(7,8);  // Samples per VITA packet
-	write_setting(8,NUMCHAN);  // Samples per VITA packet
-	queue_rx_cmd(1,0,8,32'h0,32'h0);  // send imm, single packet
-	queue_rx_cmd(1,0,16,32'h0,32'h0);  // send imm, 2 packets worth
-	queue_rx_cmd(1,0,7,32'h0,32'h0);  // send imm, 1 short packet worth
-	queue_rx_cmd(1,0,9,32'h0,32'h0);  // send imm, just longer than 1 packet
+	write_setting(8,NUMCHAN);  // Vector length
+
+	queue_rx_cmd(1,1,0,10,32'h0,32'h0);  // send imm, single packet
+	#10000;
+	
+	queue_rx_cmd(1,0,0,0,32'h0,32'h0);  // send imm, single packet
+	//queue_rx_cmd(1,1,0,0,32'h0,32'h0);  // send imm, single packet
+	
+	//queue_rx_cmd(1,0,0,0,32'h0,32'h0);  // send imm, single packet
+	
+	/*
+	queue_rx_cmd(1,0,0,8,32'h0,32'h0);  // send imm, single packet
+	queue_rx_cmd(1,0,0,16,32'h0,32'h0);  // send imm, 2 packets worth
+	queue_rx_cmd(1,0,0,7,32'h0,32'h0);  // send imm, 1 short packet worth
+	queue_rx_cmd(1,0,0,9,32'h0,32'h0);  // send imm, just longer than 1 packet
 	
-	queue_rx_cmd(1,1,16,32'h0,32'h0);  // chained
-	queue_rx_cmd(0,0,8,32'h0,32'h0);  // 2nd in chain
+	queue_rx_cmd(1,1,0,16,32'h0,32'h0);  // chained
+	queue_rx_cmd(0,0,0,8,32'h0,32'h0);  // 2nd in chain
 	
-	queue_rx_cmd(1,1,17,32'h0,32'h0);  // chained, odd length
-	queue_rx_cmd(0,0,9,32'h0,32'h0);  // 2nd in chain, also odd length
+	queue_rx_cmd(1,1,0,17,32'h0,32'h0);  // chained, odd length
+	queue_rx_cmd(0,0,0,9,32'h0,32'h0);  // 2nd in chain, also odd length
 	
-	queue_rx_cmd(0,0,8,32'h0,32'h340);  // send at, on time
-	queue_rx_cmd(0,0,8,32'h0,32'h100);  // send at, but late
+	queue_rx_cmd(0,0,0,8,32'h0,32'h340);  // send at, on time
+	queue_rx_cmd(0,0,0,8,32'h0,32'h100);  // send at, but late
 
 	#100000;
 	$display("\nChained, break chain\n");
-	queue_rx_cmd(1,1,8,32'h0,32'h0);  // chained, but break chain
+	queue_rx_cmd(1,1,0,8,32'h0,32'h0);  // chained, but break chain
 	#100000;
 	$display("\nSingle packet\n");
-	queue_rx_cmd(1,0,8,32'h0,32'h0);  // send imm, single packet
+	queue_rx_cmd(1,0,0,8,32'h0,32'h0);  // send imm, single packet
 	#100000;
 	$display("\nEnd chain with zero samples, shouldn't error\n");
-	queue_rx_cmd(1,1,8,32'h0,32'h0);  // chained
-	queue_rx_cmd(0,0,0,32'h0,32'h0);  // end chain with zero samples, should keep us out of error
+	queue_rx_cmd(1,1,0,8,32'h0,32'h0);  // chained
+	queue_rx_cmd(0,0,0,0,32'h0,32'h0);  // end chain with zero samples, should keep us out of error
 	#100000;
 
 	$display("\nEnd chain with zero samples on odd-length, shouldn't error\n");
-	queue_rx_cmd(1,1,14,32'h0,32'h0);  // chained
-	queue_rx_cmd(0,0,0,32'h0,32'h0);  // end chain with zero samples, should keep us out of error
+	queue_rx_cmd(1,1,0,14,32'h0,32'h0);  // chained
+	queue_rx_cmd(0,0,0,0,32'h0,32'h0);  // end chain with zero samples, should keep us out of error
 	#100000;
 	$display("Should have gotten 14 samples and EOF by now\n");
 	
-	queue_rx_cmd(1,1,9,32'h0,32'h0);  // chained, but break chain, odd length
+	queue_rx_cmd(1,1,0,9,32'h0,32'h0);  // chained, but break chain, odd length
 	#100000;
 	dst_rdy <= 0;  // stop pulling out of fifo so we can get an overrun
-	queue_rx_cmd(1,0,100,32'h0,32'h0);  // long enough to fill the fifos
-	queue_rx_cmd(1,0,5,32'h0,32'h0);  // this command waits until the previous error packet is sent
+	queue_rx_cmd(1,0,0,100,32'h0,32'h0);  // long enough to fill the fifos
+	queue_rx_cmd(1,0,0,5,32'h0,32'h0);  // this command waits until the previous error packet is sent
 	#100000;
 	dst_rdy <= 1;  // restart the reads so we can see what we got
 	#100000;
 	dst_rdy <= 0;  // stop pulling out of fifo so we can get an overrun
-	queue_rx_cmd(1,1,100,32'h0,32'h0);  // long enough to fill the fifos
-	//queue_rx_cmd(1,0,5,32'h0,32'h0);  // this command waits until the previous error packet is sent
+	queue_rx_cmd(1,1,0,100,32'h0,32'h0);  // long enough to fill the fifos
+	//queue_rx_cmd(1,0,0,5,32'h0,32'h0);  // this command waits until the previous error packet is sent
 	#100000;
 	@(posedge clk);
 	dst_rdy <= 1;
-	  
+	 */
 	#100000 $finish;
      end
 
@@ -164,11 +174,12 @@ module vita_rx_tb;
    task queue_rx_cmd;
       input send_imm;
       input chain;
-      input [29:0] lines;
+      input reload;
+      input [28:0] lines;
       input [31:0] secs;
       input [31:0] tics;
       begin
-	 write_setting(0,{send_imm,chain,lines});
+	 write_setting(0,{send_imm,chain,reload,lines});
 	 write_setting(1,secs);
 	 write_setting(2,tics);
       end
diff --git a/fpga/usrp2/vrt/vita_tx.build b/fpga/usrp2/vrt/vita_tx.build
index 902929c08..e7106aa10 100755
--- a/fpga/usrp2/vrt/vita_tx.build
+++ b/fpga/usrp2/vrt/vita_tx.build
@@ -1 +1 @@
-iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v
+iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v
diff --git a/fpga/usrp2/vrt/vita_tx_chain.v b/fpga/usrp2/vrt/vita_tx_chain.v
index 00da4c6e1..2ec78189b 100644
--- a/fpga/usrp2/vrt/vita_tx_chain.v
+++ b/fpga/usrp2/vrt/vita_tx_chain.v
@@ -31,9 +31,13 @@ module vita_tx_chain
    wire 		clear_seqnum;
    wire [31:0] 		current_seqnum;
    
-   assign underrun = error & ~(error_code == 1);
+   assign underrun = error;
    assign message = error_code;
-      
+   
+   setting_reg #(.my_addr(BASE_CTRL+1)) sr
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(clear_vita));
+
    setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(streamid),.changed(clear_seqnum));
@@ -52,7 +56,7 @@ module vita_tx_chain
    vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control
      (.clk(clk), .reset(reset), .clear(clear_vita),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .vita_time(vita_time),.error(error),.error_code(error_code),
+      .vita_time(vita_time), .error(error), .ack(ack), .error_code(error_code),
       .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
       .sample(sample_tx), .run(run), .strobe(strobe_tx), .packet_consumed(packet_consumed),
       .debug(debug_vtc) );
@@ -71,7 +75,7 @@ module vita_tx_chain
      (.clk(clk), .reset(reset), .clear(clear_vita),
       .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), 
       .streamid(streamid), .vita_time(vita_time), .message(32'd0),
-      .seqnum0(current_seqnum), .seqnum1(32'd0),
+      .seqnum(current_seqnum),
       .data_o(flow_data), .src_rdy_o(flow_src_rdy), .dst_rdy_i(flow_dst_rdy));
    trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt
      (.clk(clk), .reset(reset), .clear(clear_vita),
@@ -80,15 +84,15 @@ module vita_tx_chain
    
    gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt
      (.clk(clk), .reset(reset), .clear(clear_vita),
-      .trigger(error & (REPORT_ERROR==1)), .sent(), 
+      .trigger((error|ack) & (REPORT_ERROR==1)), .sent(), 
       .streamid(streamid), .vita_time(vita_time), .message(message),
-      .seqnum0(current_seqnum), .seqnum1(32'd0),
+      .seqnum(current_seqnum),
       .data_o(err_data_int), .src_rdy_o(err_src_rdy_int), .dst_rdy_i(err_dst_rdy_int));
       
    assign debug = debug_vtc | debug_vtd;
    
    fifo36_mux #(.prio(1)) mux_err_and_flow  // Priority to err messages
-     (.clk(clk), .reset(reset), .clear(clear_vita),
+     (.clk(clk), .reset(reset), .clear(0),  // Don't clear this or it could get clogged
       .data0_i(err_data_int), .src0_rdy_i(err_src_rdy_int), .dst0_rdy_o(err_dst_rdy_int),
       .data1_i(flow_data), .src1_rdy_i(flow_src_rdy), .dst1_rdy_o(flow_dst_rdy),
       .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i));
diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v
index 936762212..20ad6b995 100644
--- a/fpga/usrp2/vrt/vita_tx_control.v
+++ b/fpga/usrp2/vrt/vita_tx_control.v
@@ -6,7 +6,7 @@ module vita_tx_control
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
     
     input [63:0] vita_time,
-    output error,
+    output error, output ack,
     output reg [31:0] error_code,
     output reg packet_consumed,
     
@@ -38,9 +38,8 @@ module vita_tx_control
    // FIXME ignore too_early for now for timing reasons
    assign too_early = 0;
    time_compare 
-     time_compare (.time_now(vita_time), .trigger_time(send_time), .now(now), .early(early), 
-		   .late(late), .too_early());
-//		   .late(late), .too_early(too_early));
+     time_compare (.time_now(vita_time), .trigger_time(send_time), 
+		   .now(now), .early(early), .late(late), .too_early());
    
    localparam IBS_IDLE = 0;
    localparam IBS_RUN = 1;  // FIXME do we need this?
@@ -58,11 +57,6 @@ module vita_tx_control
    
    reg [2:0] ibs_state;
 
-   wire      clear_state;
-   setting_reg #(.my_addr(BASE+1)) sr
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_state));
-   
    wire [31:0] error_policy;
    setting_reg #(.my_addr(BASE+3)) sr_error_policy
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -71,13 +65,15 @@ module vita_tx_control
    wire        policy_wait = error_policy[0];
    wire        policy_next_packet = error_policy[1];
    wire        policy_next_burst = error_policy[2];
-   reg 	       send_error;
+   reg 	       send_error, send_ack;
    
    always @(posedge clk)
-     if(reset | clear_state)
+     if(reset | clear)
        begin
 	  ibs_state <= IBS_IDLE;
 	  send_error <= 0;
+	  send_ack <= 0;
+	  error_code <= 0;
        end
      else
        case(ibs_state)
@@ -111,7 +107,7 @@ module vita_tx_control
 		 begin
 		    ibs_state <= IBS_ERROR_DONE;  // Not really an error
 		    error_code <= CODE_EOB_ACK;
-		    send_error <= 1;
+		    send_ack <= 1;
 		 end
 	       else
 		 ibs_state <= IBS_CONT_BURST;
@@ -151,6 +147,7 @@ module vita_tx_control
 	 IBS_ERROR_DONE :
 	   begin
 	      send_error <= 0;
+	      send_ack <= 0;
 	      ibs_state <= IBS_IDLE;
 	   end
 	 
@@ -161,14 +158,15 @@ module vita_tx_control
    assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN));  // FIXME also cleanout
    assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST);
    assign error = send_error;
+   assign ack = send_ack;
 
    always @(posedge clk)
-     if(reset)
+     if(reset | clear)
        packet_consumed <= 0;
      else
        packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o;
    
-   assign debug = { { now,early,late,too_early,eop,eob,sob,send_at },
+   assign debug = { { now,early,late,ack,eop,eob,sob,send_at },
 		    { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] },
 		    { 8'b0 },
 		    { 8'b0 } };
diff --git a/fpga/usrp2/vrt/vita_tx_deframer.v b/fpga/usrp2/vrt/vita_tx_deframer.v
index 7fb8e3893..eb39feaec 100644
--- a/fpga/usrp2/vrt/vita_tx_deframer.v
+++ b/fpga/usrp2/vrt/vita_tx_deframer.v
@@ -80,7 +80,7 @@ module vita_tx_deframer
    wire        fifo_space;
 
    always @(posedge clk)
-     if(reset | clear_seqnum)
+     if(reset | clear | clear_seqnum)
        begin
 	  seqnum_reg <= 32'hFFFF_FFFF;
 	  vita_seqnum_reg <= 4'hF;
@@ -201,8 +201,6 @@ module vita_tx_deframer
 	 send_time[63:32] <= data_i[31:0];
        VITA_TICS2 :
 	 send_time[31:0] <= data_i[31:0];
-       VITA_STORE, VITA_HEADER :
-	 send_time[63:0] <= 64'd0;
      endcase // case (vita_state)
    
    always @(posedge clk)
diff --git a/fpga/usrp2/vrt/vita_tx_tb.v b/fpga/usrp2/vrt/vita_tx_tb.v
index 0223d6850..a118ffd4e 100644
--- a/fpga/usrp2/vrt/vita_tx_tb.v
+++ b/fpga/usrp2/vrt/vita_tx_tb.v
@@ -33,7 +33,7 @@ module vita_tx_tb;
    wire [31:0] set_data_dsp;
 
    wire        sample_dst_rdy, sample_src_rdy;
-   wire [64+4+(MAXCHAN*32)-1:0] sample_data_o, sample_data_tx;
+   wire [5+64+16+(MAXCHAN*32)-1:0] sample_data_o, sample_data_tx;
 
    time_64bit #(.TICKS_PER_SEC(100000000), .BASE(0)) time_64bit
      (.clk(clk), .rst(reset),
@@ -49,8 +49,8 @@ module vita_tx_tb;
       .datain(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
       .dataout(data_tx), .src_rdy_o(src_rdy_tx), .dst_rdy_i(dst_rdy_tx));
    
-   vita_tx_deframer #(.BASE(16), .MAXCHAN(MAXCHAN)) vita_tx_deframer
-     (.clk(clk), .reset(reset), .clear(0),
+   vita_tx_deframer #(.BASE(16), .MAXCHAN(MAXCHAN), .USE_TRANS_HEADER(0)) vita_tx_deframer
+     (.clk(clk), .reset(reset), .clear(0), .clear_seqnum(0),
       .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
       .data_i(data_tx), .dst_rdy_o(dst_rdy_tx), .src_rdy_i(src_rdy_tx),
       .sample_fifo_o(sample_data_tx), 
@@ -60,7 +60,7 @@ module vita_tx_tb;
    vita_tx_control #(.BASE(16), .WIDTH(MAXCHAN*32)) vita_tx_control
      (.clk(clk), .reset(reset), .clear(0),
       .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-      .vita_time(vita_time), .underrun(underrun),
+      .vita_time(vita_time), .error(underrun), .error_code(),
       .sample_fifo_i(sample_data_tx), 
       .sample_fifo_dst_rdy_o(sample_dst_rdy_tx), .sample_fifo_src_rdy_i(sample_src_rdy_tx),
       .sample(sample_tx), .run(run_tx), .strobe(strobe_tx));
@@ -92,35 +92,47 @@ module vita_tx_tb;
 	write_setting(7,8);  // Samples per VITA packet
 	write_setting(8,NUMCHAN);  // Samples per VITA packet
 	#10000;
-	queue_vita_packets(32'h300, 106, 32'hF00D_1234, 32'h55AA_AA55);
-	//queue_vita_packets(32'h300, 6, 32'hF00D_1234, 32'h0);
-	queue_vita_packets(32'h600, 9, 32'h9876_ABCD, 32'h0);
-	
+	queue_vita_packets(0, 32'h300, 5, 32'h0000_1000, 32'h0, 4'h0, 1, 0, 1);
+	queue_vita_packets(0, 32'h0,   5, 32'h0000_2000, 32'h0, 4'h1, 0, 0, 0);
+	queue_vita_packets(0, 32'h0,   5, 32'h0000_3000, 32'h0, 4'h2, 0, 0, 0);
+
+	queue_vita_packets(0, 32'h400, 3, 32'h0000_4000, 32'h0, 4'h3, 1, 0, 1);
+	queue_vita_packets(0, 32'h0,   3, 32'h0000_5000, 32'h0, 4'h4, 0, 0, 0);
+	queue_vita_packets(0, 32'h0,   3, 32'h0000_6000, 32'h0, 4'h5, 0, 1, 0);
+
 	#300000 $finish;
      end
 
    task queue_vita_packets;
+      input [31:0] send_secs;
       input [31:0] sendtime;
       input [15:0] samples;
       input [15:0] word;
       input [31:0] trailer;
+      input [3:0]  seqnum;
+      input 	   sob;
+      input 	   eob;
+      input 	   sendat;
       
       reg [15:0]   i;
       
       begin
+	 src_rdy <= 0;
 	 @(posedge clk);
 	 src_rdy <= 1;
-	 data_o <= {4'b0001,4'h1,1'b0,|trailer,2'h3,8'hF0,(16'd5+samples+|trailer)}; // header
-	 @(posedge clk);
-	 data_o <= {4'b0000,32'h0}; // streamid
-	 @(posedge clk);
-	 data_o <= {4'b0000,32'h0}; // SECS
-	 @(posedge clk);
-	 data_o <= {4'b0000,32'h0}; // TICS
+	 data_o <= {4'b0001,4'h0,1'b0,|trailer,sob,eob,{2{sendat}},1'b0,sendat,seqnum,(16'd1+samples+|trailer+sendat+sendat+sendat)}; // header
 	 @(posedge clk);
-	 data_o <= {4'b0000,sendtime}; // TICS
-	 @(posedge clk);
-
+	 //data_o <= {4'b0000,32'h0}; // streamid
+	 //@(posedge clk);
+	 if(sendat)
+	   begin
+	      data_o <= {4'b0000,send_secs}; // SECS
+	      @(posedge clk);
+	      data_o <= {4'b0000,32'h0}; // TICS
+	      @(posedge clk);
+	      data_o <= {4'b0000,sendtime}; // TICS
+	      @(posedge clk);
+	   end
 	 for(i=0;i<samples-1;i=i+1)
 	   begin
 	      data_o <= {4'b0000,i,word}; // Payload
-- 
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