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author | Josh Blum <josh@joshknows.com> | 2011-03-10 14:57:01 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2011-03-10 14:57:01 -0800 |
commit | db2b80617d789484b463ab81a94605adfae39de9 (patch) | |
tree | 5f1a85be7a10d76b82ba9c300005573790d1a688 /fpga/usrp2/vrt | |
parent | 6d744744d88f8834f91c76742cd190e204f2ae8e (diff) | |
parent | 912a697adbfcf80cc64e9c0884f6d723e6d8f003 (diff) | |
download | uhd-db2b80617d789484b463ab81a94605adfae39de9.tar.gz uhd-db2b80617d789484b463ab81a94605adfae39de9.tar.bz2 uhd-db2b80617d789484b463ab81a94605adfae39de9.zip |
Merge branch 'packet_router_2nd_dsp' into next
Diffstat (limited to 'fpga/usrp2/vrt')
-rw-r--r-- | fpga/usrp2/vrt/vita_rx_chain.v | 19 | ||||
-rw-r--r-- | fpga/usrp2/vrt/vita_rx_control.v | 2 | ||||
-rw-r--r-- | fpga/usrp2/vrt/vita_rx_framer.v | 11 |
3 files changed, 18 insertions, 14 deletions
diff --git a/fpga/usrp2/vrt/vita_rx_chain.v b/fpga/usrp2/vrt/vita_rx_chain.v index f5578eb15..d7498286d 100644 --- a/fpga/usrp2/vrt/vita_rx_chain.v +++ b/fpga/usrp2/vrt/vita_rx_chain.v @@ -1,6 +1,8 @@ module vita_rx_chain - #(parameter BASE=0) + #(parameter BASE=0, + parameter UNIT=0, + parameter FIFOSIZE=10) (input clk, input reset, input clear, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, output overrun, @@ -9,8 +11,11 @@ module vita_rx_chain output [31:0] debug ); wire [100:0] sample_data; - wire sample_dst_rdy, sample_src_rdy; - wire [31:0] vrc_debug, vrf_debug; + wire sample_dst_rdy, sample_src_rdy; + wire [31:0] vrc_debug, vrf_debug; + + wire [35:0] rx_data_int; + wire rx_src_rdy_int, rx_dst_rdy_in; vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control (.clk(clk), .reset(reset), .clear(clear), @@ -24,10 +29,14 @@ module vita_rx_chain (.clk(clk), .reset(reset), .clear(clear), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .sample_fifo_i(sample_data), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy), - .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i), - .fifo_occupied(), .fifo_full(), .fifo_empty(), + .data_o(rx_data_int), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int), .debug_rx(vrf_debug) ); + dsp_framer36 #(.BUF_SIZE(FIFOSIZE), .PORT_SEL(UNIT)) dsp0_framer36 + (.clk(clk), .reset(reset), .clear(clear), + .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), + .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i) ); + assign debug = vrc_debug; // | vrf_debug; endmodule // vita_rx_chain diff --git a/fpga/usrp2/vrt/vita_rx_control.v b/fpga/usrp2/vrt/vita_rx_control.v index 0769f3a24..4c0cef50d 100644 --- a/fpga/usrp2/vrt/vita_rx_control.v +++ b/fpga/usrp2/vrt/vita_rx_control.v @@ -196,4 +196,4 @@ module vita_rx_control { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl }, { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; -endmodule // rx_control +endmodule // vita_rx_control diff --git a/fpga/usrp2/vrt/vita_rx_framer.v b/fpga/usrp2/vrt/vita_rx_framer.v index bce8fe334..04b636778 100644 --- a/fpga/usrp2/vrt/vita_rx_framer.v +++ b/fpga/usrp2/vrt/vita_rx_framer.v @@ -15,11 +15,6 @@ module vita_rx_framer input sample_fifo_src_rdy_i, output sample_fifo_dst_rdy_o, - // FIFO Levels - output [15:0] fifo_occupied, - output fifo_full, - output fifo_empty, - output [31:0] debug_rx ); @@ -200,8 +195,8 @@ module vita_rx_framer (.clk(clk), .reset(reset), .clear(clear), .datain(pkt_fifo_line), .src_rdy_i(req_write_pkt_fifo), .dst_rdy_o(pkt_fifo_rdy), .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), - .space(),.occupied(fifo_occupied[4:0]) ); - assign fifo_occupied[15:5] = 0; + .space(),.occupied() ); + assign data_o[35:34] = 2'b00; // Always write full lines assign sample_fifo_dst_rdy_o = pkt_fifo_rdy & ( ((vita_state==VITA_PAYLOAD) & @@ -211,4 +206,4 @@ module vita_rx_framer assign debug_rx = vita_state; -endmodule // rx_control +endmodule // vita_rx_framer |