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| author | Philip Balister <philip@opensdr.com> | 2011-02-01 07:20:56 -0800 |
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| committer | Philip Balister <philip@opensdr.com> | 2011-02-01 07:20:56 -0800 |
| commit | 15ae6f2859ecde28b6ebecbb7ec417f6d758b639 (patch) | |
| tree | 012627b3db03fd9858dc72a240f2337efa0e397f /fpga/usrp2/vrt | |
| parent | 781cddee31078e461202c2cf16f3de2f1f236a27 (diff) | |
| download | uhd-15ae6f2859ecde28b6ebecbb7ec417f6d758b639.tar.gz uhd-15ae6f2859ecde28b6ebecbb7ec417f6d758b639.tar.bz2 uhd-15ae6f2859ecde28b6ebecbb7ec417f6d758b639.zip | |
Fixes for timed fpga interface test program. Still need to solve the CRC
calculation failures.
Diffstat (limited to 'fpga/usrp2/vrt')
0 files changed, 0 insertions, 0 deletions