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authorJosh Blum <josh@joshknows.com>2010-06-15 18:24:33 -0700
committerJosh Blum <josh@joshknows.com>2010-06-15 18:24:33 -0700
commitedcc2df10ba59ed91ac9513c2dc1d36e155caaec (patch)
tree1a1ec2c0b5500990c991c27af03dbe48c10ce7ca /fpga/usrp2/vrt/vita_tx_deframer.v
parenta89d684ba2b81c6e18d348965dffb919edb56fea (diff)
parent9445315e6a5cdfb29c4ead73b0fcd4d5fd75b900 (diff)
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Merge branch 'master' of ettus.sourcerepo.com:ettus/fpga into uhd_master
Conflicts: fpga/.gitignore
Diffstat (limited to 'fpga/usrp2/vrt/vita_tx_deframer.v')
-rw-r--r--fpga/usrp2/vrt/vita_tx_deframer.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/vrt/vita_tx_deframer.v b/fpga/usrp2/vrt/vita_tx_deframer.v
index 49428ead5..220d3b061 100644
--- a/fpga/usrp2/vrt/vita_tx_deframer.v
+++ b/fpga/usrp2/vrt/vita_tx_deframer.v
@@ -28,7 +28,7 @@ module vita_tx_deframer
reg [3:0] vita_state;
wire has_streamid, has_classid, has_secs, has_tics, has_trailer;
- assign has_streamid = (data_i[31:28]==4'b001);
+ assign has_streamid = (data_i[31:28]==4'b0001);
assign has_classid = data_i[27];
assign has_secs = ~(data_i[23:22]==2'b00);
assign has_tics = ~(data_i[21:20]==2'b00);