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| author | Nick Foster <nick@nerdnetworks.org> | 2010-08-10 17:02:47 -0700 |
|---|---|---|
| committer | Nick Foster <nick@nerdnetworks.org> | 2010-08-10 17:02:47 -0700 |
| commit | 663808e847c4970551c6c8127c2c5d816e2a2014 (patch) | |
| tree | 12183a2d7ea5434880dccfa414d8a378ae134abc /fpga/usrp2/vrt/vita_rx_control.v | |
| parent | 90a5d84a18aaa338092e572ff257aab1fdcc8e6b (diff) | |
| parent | 9e419c7b7f35062ceb2ed4e508cadb163067593f (diff) | |
| download | uhd-663808e847c4970551c6c8127c2c5d816e2a2014.tar.gz uhd-663808e847c4970551c6c8127c2c5d816e2a2014.tar.bz2 uhd-663808e847c4970551c6c8127c2c5d816e2a2014.zip | |
Merge branch 'master' into usrp2p
this was the merge from hell
Conflicts:
firmware/microblaze/Makefile.am
firmware/microblaze/bootstrap
firmware/microblaze/configure.ac
firmware/microblaze/lib/Makefile.inc
host/lib/CMakeLists.txt
host/lib/usrp/mimo_usrp.cpp
host/lib/usrp/simple_usrp.cpp
host/lib/usrp/usrp2/clock_ctrl.cpp
host/lib/usrp/usrp2/codec_impl.cpp
host/lib/usrp/usrp2/dboard_impl.cpp
host/lib/usrp/usrp2/mboard_impl.cpp
host/lib/usrp/usrp2/usrp2_iface.hpp
host/lib/usrp/usrp2/usrp2_impl.hpp
host/lib/usrp/usrp2/usrp2_regs.hpp
host/test/CMakeLists.txt
Diffstat (limited to 'fpga/usrp2/vrt/vita_rx_control.v')
| -rw-r--r-- | fpga/usrp2/vrt/vita_rx_control.v | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/fpga/usrp2/vrt/vita_rx_control.v b/fpga/usrp2/vrt/vita_rx_control.v index 742dd47e0..93673d292 100644 --- a/fpga/usrp2/vrt/vita_rx_control.v +++ b/fpga/usrp2/vrt/vita_rx_control.v @@ -67,7 +67,7 @@ module vita_rx_control shortfifo #(.WIDTH(96)) commandfifo (.clk(clk),.rst(reset),.clear(clear_int), .datain({new_command,new_time}), .write(write_ctrl&~full_ctrl), .full(full_ctrl), - .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}), + .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}), .read(read_ctrl), .empty(empty_ctrl), .occupied(command_queue_len), .space() ); @@ -98,7 +98,7 @@ module vita_rx_control .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i), .space(), .occupied() ); - // Inband Signallling State Machine + // Inband Signalling State Machine time_compare time_compare (.time_now(vita_time), .trigger_time(rcvtime), .now(now), .early(early), .late(late)); @@ -189,4 +189,3 @@ module vita_rx_control { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; endmodule // rx_control - |