Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

7 files changed, 673 insertions, 0 deletions

diff --git a/fpga/usrp2/udp/Makefile.srcs b/fpga/usrp2/udp/Makefile.srcs
new file mode 100644
index 000000000..293094abe
--- /dev/null
+++ b/fpga/usrp2/udp/Makefile.srcs
@@ -0,0 +1,13 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# UDP Sources
+##################################################
+UDP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../udp/, \
+udp_wrapper.v \
+fifo19_rxrealign.v \
+prot_eng_tx.v \
+add_onescomp.v \
+))
diff --git a/fpga/usrp2/udp/add_onescomp.v b/fpga/usrp2/udp/add_onescomp.v
new file mode 100644
index 000000000..e02604114
--- /dev/null
+++ b/fpga/usrp2/udp/add_onescomp.v
@@ -0,0 +1,29 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+
+module add_onescomp
+  #(parameter WIDTH = 16)
+   (input [WIDTH-1:0] A,
+    input [WIDTH-1:0] B,
+    output [WIDTH-1:0] SUM);
+
+   wire [WIDTH:0] SUM_INT = {1'b0,A} + {1'b0,B};
+   assign SUM  = SUM_INT[WIDTH-1:0] + {{WIDTH-1{1'b0}},SUM_INT[WIDTH]};
+   
+endmodule // add_onescomp
diff --git a/fpga/usrp2/udp/fifo19_rxrealign.v b/fpga/usrp2/udp/fifo19_rxrealign.v
new file mode 100644
index 000000000..da5fd20af
--- /dev/null
+++ b/fpga/usrp2/udp/fifo19_rxrealign.v
@@ -0,0 +1,59 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+
+//  Adds a junk line at the beginning of every packet, which the
+//   following stages should ignore.  This gives us proper alignment due
+//   to the 14 byte ethernet header
+
+// Bit 18 -- odd length
+// Bit 17 -- eof
+// Bit 16 -- sof
+// Bit 15:0 -- data
+
+module fifo19_rxrealign
+  (input clk, input reset, input clear,
+   input [18:0] datain, input src_rdy_i, output dst_rdy_o,
+   output [18:0] dataout, output src_rdy_o, input dst_rdy_i);
+   
+   reg 	rxre_state;
+   localparam RXRE_DUMMY  = 0;
+   localparam RXRE_PKT 	  = 1;
+   
+   assign dataout[18] 	  = datain[18];
+   assign dataout[17] 	  = datain[17];
+   assign dataout[16] 	  = (rxre_state==RXRE_DUMMY) | (datain[17] & datain[16]);  // allows for passing error signal
+   assign dataout[15:0] = datain[15:0];
+   
+   always @(posedge clk)
+     if(reset | clear)
+       rxre_state <= RXRE_DUMMY;
+     else if(src_rdy_i & dst_rdy_i)
+       case(rxre_state)
+	 RXRE_DUMMY :
+	   rxre_state <= RXRE_PKT;
+	 RXRE_PKT :
+	   if(datain[17])   // if eof or error
+	     rxre_state <= RXRE_DUMMY;
+       endcase // case (rxre_state)
+
+   assign src_rdy_o 	 = src_rdy_i & dst_rdy_i;   // Send anytime both sides are ready
+   assign dst_rdy_o = src_rdy_i & dst_rdy_i & (rxre_state == RXRE_PKT);  // Only consume after the dummy
+   
+endmodule // fifo19_rxrealign
+
diff --git a/fpga/usrp2/udp/prot_eng_rx.v b/fpga/usrp2/udp/prot_eng_rx.v
new file mode 100644
index 000000000..ccb59b7ff
--- /dev/null
+++ b/fpga/usrp2/udp/prot_eng_rx.v
@@ -0,0 +1,138 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+
+
+// Protocol Engine Receiver
+//  Checks each line (16 bits) against values in setting regs
+//  3 options for each line -- 
+//      Error if mismatch, Slowpath if mismatch, or ignore line
+//  The engine increases the length of each packet by 32 or 48 bits,
+//   bringing the total length to a multiple of 32 bits.  The last line
+//   is entirely new, and contains the results of the matching operation:
+//      16 bits of flags, 16 bits of data.  Flags indicate error or slowpath
+//      Data indicates line that caused mismatch if any.
+
+
+//   Flags[2:0] is {occ, eop, sop}
+//   Protocol word format is:
+//             22   Last Header Line
+//             21   SLOWPATH if mismatch
+//             20   ERROR if mismatch
+//             19   This is the IP checksum
+//             18   This is the UDP checksum
+//             17   Compute IP checksum on this word
+//             16   Compute UDP checksum on this word
+//           15:0   data word to be matched
+
+module prot_eng_rx
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [18:0] datain, input src_rdy_i, output dst_rdy_o,
+    output [18:0] dataout, output src_rdy_o, input dst_rdy_i);
+
+   localparam HDR_WIDTH  = 16 + 7;  // 16 bits plus flags
+   localparam HDR_LEN 	 = 32;      // Up to 64 bytes of protocol
+   
+   // Store header values in a small dual-port (distributed) ram
+   reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1];
+   wire [HDR_WIDTH-1:0] header_word;
+   
+   always @(posedge clk)
+     if(set_stb & ((set_addr & 8'hE0) == BASE))
+       header_ram[set_addr[4:0]] <= set_data;
+
+   assign header_word 	= header_ram[state];
+
+   wire consume_input 	= src_rdy_i & dst_rdy_o;
+   wire produce_output 	= src_rdy_o & dst_rdy_i;
+   
+   // Main State Machine
+   reg [15:0] pkt_length, fail_word, dataout_int;
+   
+   reg slowpath, error, sof_o, eof_o, occ_o, odd;
+
+   assign dataout    = {occ_o, eof_o, sof_o, dataout_int};
+
+   wire [15:0] calc_ip_checksum, calc_udp_checksum;
+   reg [15:0] rx_ip_checksum, rx_udp_checksum;
+
+   always @(posedge clk) 
+     if(header_word[19]) 
+       rx_ip_checksum  <= datain[15:0];
+   always @(posedge clk) 
+     if(header_word[18]) 
+       rx_udp_checksum <= datain[15:0];
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  slowpath     <= 0;
+	  error        <= 0;
+	  state        <= 0;
+	  fail_word    <= 0;
+	  eof_o        <= 0;
+	  occ_o        <= 0;
+       end
+     else if(src_rdy_i & dst_rdy_i)
+       case (state)
+	 0 :
+	   begin
+	      slowpath 	   <= 0;
+	      error 	   <= 0;
+	      eof_o 	   <= 0;
+	      occ_o 	   <= 0;
+	      state 	   <= 1;
+	   end
+
+	 ST_SLOWPATH :
+	   ;
+	 ST_ERROR :
+	   ;
+	 ST_PAYLOAD :
+	   ;
+	 ST_FILLER :
+	   ;
+	 ST_END1 :
+	   ;
+	 ST_END2 :
+	   ;
+	 default :
+	   if(header_word[21] && mismatch)
+	     state <= ST_SLOWPATH;
+	   else if(header_word[20] && mismatch)
+	     state <= ST_ERROR;
+	   else if(header_word[22])
+	     state <= ST_PAYLOAD;
+	   else
+	     state <= state + 1;
+       endcase // case (state)
+   
+
+
+   // IP + UDP checksum state machines
+   checksum_sm ip_chk
+     (.clk(clk), .reset(reset), .in(datain), 
+      .calc(consume_input & header_word[17]), .clear(state==0), .checksum(ip_checksum));
+   
+   checksum_sm udp_chk
+     (.clk(clk), .reset(reset), .in(datain), 
+      .calc(consume_input & header_word[16]), .clear(state==0), .checksum(udp_checksum));
+   
+endmodule // prot_eng_rx
diff --git a/fpga/usrp2/udp/prot_eng_tx.v b/fpga/usrp2/udp/prot_eng_tx.v
new file mode 100644
index 000000000..40abf3c04
--- /dev/null
+++ b/fpga/usrp2/udp/prot_eng_tx.v
@@ -0,0 +1,127 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+module prot_eng_tx
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [35:0] datain, input src_rdy_i, output dst_rdy_o,
+    output [35:0] dataout, output src_rdy_o, input dst_rdy_i);
+
+   wire 	  src_rdy_int1, dst_rdy_int1;
+   wire 	  src_rdy_int2, dst_rdy_int2;
+   wire [35:0] 	  data_int1, data_int2;
+
+   // Shortfifo on input to guarantee no deadlock
+   fifo_short #(.WIDTH(36)) head_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
+      .space(),.occupied() );
+   
+   // Store header values in a small dual-port (distributed) ram
+   reg [31:0] 	  header_ram[0:63];
+   reg [3:0] 	  state;
+   reg [1:0] 	  port_sel;
+   
+   always @(posedge clk)
+     if(set_stb & ((set_addr & 8'hC0) == BASE))
+       header_ram[set_addr[5:0]] <= set_data;
+
+   wire [31:0] 	  header_word = header_ram[{port_sel[1:0],state[3:0]}];
+
+   reg [15:0] 	  pre_checksums [0:3];
+   always @(posedge clk)
+     if(set_stb & ((set_addr & 8'hCF)== (BASE+7)))
+       pre_checksums[set_addr[5:4]] <= set_data[15:0];
+
+   wire [15:0] 	  pre_checksum = pre_checksums[port_sel[1:0]];
+
+   // Protocol State Machine
+   reg [15:0] length;
+   wire [15:0] ip_length = length + 28;  // IP HDR + UDP HDR
+   wire [15:0] udp_length = length + 8;  //  UDP HDR
+   reg 	       sof_o;
+   reg [31:0]  prot_data;
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  state   <= 0;
+	  sof_o   <= 0;
+       end
+     else
+       if(src_rdy_int1 & dst_rdy_int2)
+	 case(state)
+	   0 :
+	     begin
+		port_sel <= data_int1[18:17];
+		length 	<= data_int1[15:0];
+		sof_o <= 1;
+		if(data_int1[16])
+		  state <= 1;
+		else
+		  state <= 12;
+	     end
+	   12 :
+	     begin
+		sof_o <= 0;
+		if(data_int1[33]) // eof
+		  state <= 0;
+	     end
+	   default :
+	     begin
+		sof_o 	<= 0;
+		state <= state + 1;
+	     end
+	 endcase // case (state)
+
+   wire [15:0] ip_checksum;
+   add_onescomp #(.WIDTH(16)) add_onescomp 
+     (.A(pre_checksum),.B(ip_length),.SUM(ip_checksum));
+   reg [15:0]  ip_checksum_reg;
+   always @(posedge clk) ip_checksum_reg <= ip_checksum;
+   
+   always @*
+     case(state)
+       1 : prot_data <= header_word;  // ETH, top half ignored
+       2 : prot_data <= header_word;  // ETH
+       3 : prot_data <= header_word;  // ETH
+       4 : prot_data <= header_word;  // ETH
+       5 : prot_data <= { header_word[31:16], ip_length }; // IP
+       6 : prot_data <= header_word; // IP
+       7 : prot_data <= { header_word[31:16], (16'hFFFF ^ ip_checksum_reg) }; // IP
+       8 : prot_data <= header_word; // IP
+       9 : prot_data <= header_word; // IP
+       10: prot_data <= header_word;  // UDP 
+       11: prot_data <= { udp_length, header_word[15:0]}; // UDP
+       default : prot_data <= data_int1[31:0];
+     endcase // case (state)
+
+   assign data_int2 = { data_int1[35:33] & {3{state[3]}},  sof_o, prot_data };
+   assign dst_rdy_int1 = dst_rdy_int2 & ((state == 0) | (state == 12));
+   assign src_rdy_int2 = src_rdy_int1 & (state != 0);
+   
+   // Shortfifo on output to guarantee no deadlock
+   fifo_short #(.WIDTH(36)) tail_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
+      .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
+      .space(),.occupied() );
+   
+endmodule // prot_eng_tx
diff --git a/fpga/usrp2/udp/prot_eng_tx_tb.v b/fpga/usrp2/udp/prot_eng_tx_tb.v
new file mode 100644
index 000000000..866093ef5
--- /dev/null
+++ b/fpga/usrp2/udp/prot_eng_tx_tb.v
@@ -0,0 +1,198 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+module prot_eng_tx_tb();
+
+   localparam BASE = 128;
+   reg clk    = 0;
+   reg rst    = 1;
+   reg clear  = 0;
+   initial #1000 rst = 0;
+   always #50 clk = ~clk;
+   
+   reg [31:0] f36_data;
+   reg [1:0]  f36_occ;
+   reg 	      f36_sof, f36_eof;
+   wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
+   reg 	       src_rdy_f36i  = 0;
+   wire        dst_rdy_f36i;
+
+
+   wire [35:0] casc_do;
+   wire        src_rdy_f36o, dst_rdy_f36o;
+
+   wire [35:0] prot_out;
+   wire        src_rdy_prot, dst_rdy_prot;
+
+   wire [35:0] realign_out;
+   wire        src_rdy_realign;
+   reg 	       dst_rdy_realign = 1;
+      
+   reg [15:0] count;
+
+   reg set_stb;
+   reg [7:0] set_addr;
+   reg [31:0] set_data;
+	
+   fifo_short #(.WIDTH(36)) fifo_cascade36
+     (.clk(clk),.reset(rst),.clear(clear),
+      .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
+      .dataout(casc_do),.src_rdy_o(src_rdy_f36o),.dst_rdy_i(dst_rdy_f36o));
+
+   prot_eng_tx #(.BASE(BASE)) prot_eng_tx
+     (.clk(clk), .reset(rst), .clear(0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .datain(casc_do),.src_rdy_i(src_rdy_f36o),.dst_rdy_o(dst_rdy_f36o),
+      .dataout(prot_out),.src_rdy_o(src_rdy_prot),.dst_rdy_i(dst_rdy_prot));
+
+   ethtx_realign ethtx_realign
+     (.clk(clk), .reset(rst), .clear(0),
+      .datain(prot_out),.src_rdy_i(src_rdy_prot),.dst_rdy_o(dst_rdy_prot),
+      .dataout(realign_out),.src_rdy_o(src_rdy_realign),.dst_rdy_i(dst_rdy_realign));
+
+   reg [35:0] printer;
+
+   task WriteSREG;
+      input [7:0] addr;
+      input [31:0] data;
+
+      begin
+	 @(posedge clk);
+	 set_addr <= addr;
+	 set_data <= data;
+	 set_stb  <= 1;
+	 @(posedge clk);
+	 set_stb <= 0;
+      end
+   endtask // WriteSREG
+   	
+   always @(posedge clk)
+     if(src_rdy_realign)
+       $display("Read: %h",realign_out);
+
+   
+   task ReadFromFIFO36;
+      begin
+	 $display("Read from FIFO36");
+	 #1 dst_rdy_realign <= 1;
+	 while(~src_rdy_prot)
+	   @(posedge clk);
+	 while(1)
+	   begin
+	      while(~src_rdy_prot)
+		@(posedge clk);
+	      $display("Read: %h",realign_out);
+	      @(posedge clk);
+	   end
+      end
+   endtask // ReadFromFIFO36
+   
+   task PutPacketInFIFO36;
+      input [31:0] data_start;
+      input [31:0] data_len;
+      begin
+	 count 	      <= 4;
+	 src_rdy_f36i <= 1;
+	 f36_data     <= 32'h0001_000c;
+	 f36_sof      <= 1;
+	 f36_eof      <= 0;
+	 f36_occ      <= 0;
+	
+	 $display("Put Packet in FIFO36");
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 $display("PPI_FIFO36: Entered First Line");
+	 f36_sof  <= 0;
+	 f36_data <= data_start;
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 while(count+4 < data_len)
+	   begin
+	      f36_data <= f36_data + 32'h01010101;
+	      count    <= count + 4;
+	      while(~dst_rdy_f36i)
+		@(posedge clk);
+	      @(posedge clk);
+	      $display("PPI_FIFO36: Entered New Line");
+	   end
+	 f36_data  <= f36_data + 32'h01010101;
+	 f36_eof   <= 1;
+	 if(count + 4 == data_len)
+	   f36_occ <= 0;
+	 else if(count + 3 == data_len)
+	   f36_occ <= 3;
+	 else if(count + 2 == data_len)
+	   f36_occ <= 2;
+	 else
+	   f36_occ <= 1;
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 f36_occ      <= 0;
+	 f36_eof      <= 0;
+	 f36_data     <= 0;
+	 src_rdy_f36i <= 0;
+	 $display("PPI_FIFO36: Entered Last Line");
+      end
+   endtask // PutPacketInFIFO36
+   
+   initial $dumpfile("prot_eng_tx_tb.vcd");
+   initial $dumpvars(0,prot_eng_tx_tb);
+
+   initial
+     begin
+	#10000;
+	@(posedge clk);
+	//ReadFromFIFO36;
+     end
+   
+   initial
+     begin
+	@(negedge rst);
+	@(posedge clk);
+	WriteSREG(BASE, 32'h89AB_CDEF);
+	WriteSREG(BASE+1, 32'h1111_2222);
+	WriteSREG(BASE+2, 32'h3333_4444);
+	WriteSREG(BASE+3, 32'h5555_6666);
+	WriteSREG(BASE+4, 32'h7777_8888);
+	WriteSREG(BASE+5, 32'h9999_aaaa);
+	WriteSREG(BASE+6, 32'hbbbb_cccc);
+	WriteSREG(BASE+7, 32'hdddd_eeee);
+	WriteSREG(BASE+8, 32'h0f0f_0011);
+	WriteSREG(BASE+9, 32'h0022_0033);
+	WriteSREG(BASE+10, 32'h0044_0055);
+	WriteSREG(BASE+11, 32'h0066_0077);
+	WriteSREG(BASE+12, 32'h0088_0099);
+	@(posedge clk);
+	
+	PutPacketInFIFO36(32'hA0B0C0D0,16);
+	@(posedge clk);
+	@(posedge clk);
+	#10000;
+	@(posedge clk);
+	//PutPacketInFIFO36(32'hE0F0A0B0,36);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+     end
+
+   initial #20000 $finish;
+endmodule // prot_eng_tx_tb
diff --git a/fpga/usrp2/udp/udp_wrapper.v b/fpga/usrp2/udp/udp_wrapper.v
new file mode 100644
index 000000000..20bcb477b
--- /dev/null
+++ b/fpga/usrp2/udp/udp_wrapper.v
@@ -0,0 +1,109 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+module udp_wrapper
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [18:0] rx_f19_data, input rx_f19_src_rdy_i, output rx_f19_dst_rdy_o,
+    output [18:0] tx_f19_data, output tx_f19_src_rdy_o, input tx_f19_dst_rdy_i,
+    
+    output [35:0] rx_f36_data, output rx_f36_src_rdy_o, input rx_f36_dst_rdy_i,
+    input [35:0] tx_f36_data, input tx_f36_src_rdy_i, output tx_f36_dst_rdy_o,
+    output [31:0] debug
+    );
+
+   wire 	 tx_int1_src_rdy, tx_int1_dst_rdy;
+   wire [18:0] 	 tx_int1_data;
+   
+   wire 	 tx_int2_src_rdy, tx_int2_dst_rdy;
+   wire [18:0] 	 tx_int2_data;
+   wire [31:0] 	 debug_state;
+   
+   // TX side
+   fifo36_to_fifo19 fifo36_to_fifo19
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy_i), .f36_dst_rdy_o(tx_f36_dst_rdy_o),
+      .f19_dataout(tx_int1_data), .f19_src_rdy_o(tx_int1_src_rdy), .f19_dst_rdy_i(tx_int1_dst_rdy) );
+
+   fifo_short #(.WIDTH(19)) shortfifo19_a
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(tx_int1_data), .src_rdy_i(tx_int1_src_rdy), .dst_rdy_o(tx_int1_dst_rdy),
+      .dataout(tx_int2_data), .src_rdy_o(tx_int2_src_rdy), .dst_rdy_i(tx_int2_dst_rdy),
+      .space(), .occupied() );
+     
+   prot_eng_tx #(.BASE(BASE)) prot_eng_tx
+     (.clk(clk), .reset(reset), .clear(clear),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .datain(tx_int2_data), .src_rdy_i(tx_int2_src_rdy), .dst_rdy_o(tx_int2_dst_rdy),
+      .dataout(tx_f19_data), .src_rdy_o(tx_f19_src_rdy_o), .dst_rdy_i(tx_f19_dst_rdy_i) );
+
+   // RX side
+   wire rx_int1_src_rdy, rx_int1_dst_rdy;
+   wire [18:0] rx_int1_data;
+      
+   wire rx_int2_src_rdy, rx_int2_dst_rdy;
+   wire [18:0] rx_int2_data;
+      
+   //wire        rx_int3_src_rdy, rx_int3_dst_rdy;
+   //wire [35:0] rx_int3_data;
+   
+`ifdef USE_PROT_ENG
+   prot_eng_rx #(.BASE(BASE+32)) prot_eng_rx
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o),
+      .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) );
+`else
+   fifo19_rxrealign fifo19_rxrealign
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o),
+      .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) );
+`endif // !`ifdef USE_PROT_ENG
+   
+   fifo_short #(.WIDTH(19)) shortfifo19_b
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_int1_data), .src_rdy_i(rx_int1_src_rdy), .dst_rdy_o(rx_int1_dst_rdy),
+      .dataout(rx_int2_data), .src_rdy_o(rx_int2_src_rdy), .dst_rdy_i(rx_int2_dst_rdy),
+      .space(), .occupied() );
+
+   fifo19_to_fifo36 fifo19_to_fifo36
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f19_datain(rx_int2_data), .f19_src_rdy_i(rx_int2_src_rdy), .f19_dst_rdy_o(rx_int2_dst_rdy),
+      .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy_o), .f36_dst_rdy_i(rx_f36_dst_rdy_i),
+      .debug(debug_state));
+
+   /*
+   fifo_cascade #(.WIDTH(36),.SIZE(RXFIFOSIZE)) eth0_rxfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy),
+      .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i),
+      .space(), .occupied() );
+*/
+   /*
+   assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i },
+		    { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy},
+		    { rx_int3_data[35:32], rx_f36_data[35:32] },
+		    { debug_state[1:0], rx_int1_data[18:16], rx_int2_data[18:16] } };
+    */
+
+   assign debug = { { 3'd0, tx_int1_src_rdy, tx_int1_dst_rdy, tx_int1_data[18:16] },
+		    { 3'd0, tx_int2_src_rdy, tx_int2_dst_rdy, tx_int2_data[18:16] },
+		    { tx_int2_data[15:8] },
+		    { tx_int2_data[7:0] } };
+   
+endmodule // udp_wrapper