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| author | Josh Blum <josh@joshknows.com> | 2010-12-22 19:25:06 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-12-22 19:25:06 -0800 |
| commit | aebd62b626a8910f5ca92694b56162940f9a09fa (patch) | |
| tree | fbe15be93391be35e837fec567f97d07fe8c6e3d /fpga/usrp2/udp/prot_eng_tx_tb.v | |
| parent | d34565968a4f764252a492de42c0e8f93f2e7666 (diff) | |
| parent | 195c8f9a53b4737478ca4c46fe226bd1d8c6857f (diff) | |
| download | uhd-aebd62b626a8910f5ca92694b56162940f9a09fa.tar.gz uhd-aebd62b626a8910f5ca92694b56162940f9a09fa.tar.bz2 uhd-aebd62b626a8910f5ca92694b56162940f9a09fa.zip | |
Merge branch 'fpga_next' into uhd_next
Diffstat (limited to 'fpga/usrp2/udp/prot_eng_tx_tb.v')
| -rw-r--r-- | fpga/usrp2/udp/prot_eng_tx_tb.v | 27 |
1 files changed, 17 insertions, 10 deletions
diff --git a/fpga/usrp2/udp/prot_eng_tx_tb.v b/fpga/usrp2/udp/prot_eng_tx_tb.v index e7ffeb5e1..c8fffe605 100644 --- a/fpga/usrp2/udp/prot_eng_tx_tb.v +++ b/fpga/usrp2/udp/prot_eng_tx_tb.v @@ -80,7 +80,7 @@ module prot_eng_tx_tb(); begin count <= 4; src_rdy_f36i <= 1; - f36_data <= 32'h0001_000c; + f36_data <= 32'h0003_000c; f36_sof <= 1; f36_eof <= 0; f36_occ <= 0; @@ -140,16 +140,23 @@ module prot_eng_tx_tb(); @(negedge rst); @(posedge clk); WriteSREG(BASE, {12'b0, 4'h0, 16'h0000}); - WriteSREG(BASE+1, {12'b0, 4'h0, 16'h0000}); - WriteSREG(BASE+2, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+3, {12'b0, 4'h0, 16'h1234}); - WriteSREG(BASE+4, {12'b0, 4'h8, 16'h5678}); - WriteSREG(BASE+5, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+6, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+7, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+8, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+9, {12'b0, 4'h0, 16'hABCD}); + WriteSREG(BASE+1, {11'b0, 5'h00, 16'h0000}); + WriteSREG(BASE+2, {11'b0, 5'h00, 16'hABCD}); + WriteSREG(BASE+3, {11'b0, 5'h00, 16'h1234}); + WriteSREG(BASE+4, {11'b0, 5'h00, 16'h5678}); + WriteSREG(BASE+5, {11'b0, 5'h00, 16'hF00D}); + WriteSREG(BASE+6, {11'b0, 5'h00, 16'hBEEF}); + WriteSREG(BASE+7, {11'b0, 5'h10, 16'hDCBA}); + WriteSREG(BASE+8, {11'b0, 5'h00, 16'h4321}); + WriteSREG(BASE+9, {11'b0, 5'h04, 16'hABCD}); + WriteSREG(BASE+10, {11'b0, 5'h08, 16'hABCD}); @(posedge clk); + + WriteSREG(BASE+24, 16'h6666); + WriteSREG(BASE+25, 16'h7777); + WriteSREG(BASE+26, 16'h8888); + WriteSREG(BASE+27, 16'h9999); + PutPacketInFIFO36(32'hA0B0C0D0,16); @(posedge clk); @(posedge clk); |