Merge branch 'fpga_maint' into maint

4 files changed, 19 insertions, 8 deletions

diff --git a/fpga/usrp2/top/B100/B100.v b/fpga/usrp2/top/B100/B100.v
index dcda974b4..e333e82aa 100644
--- a/fpga/usrp2/top/B100/B100.v
+++ b/fpga/usrp2/top/B100/B100.v
@@ -143,13 +143,13 @@ module B100
    always @(posedge clk_fpga)
      if(rxsync_0)
        begin
-	  rx_i <= rx_b;
-	  rx_q <= rx_a;
+	  rx_i <= ~rx_b;
+	  rx_q <= ~rx_a;
        end
      else
        begin
-	  rx_i <= rx_a;
-	  rx_q <= rx_b;
+	  rx_i <= ~rx_a;
+	  rx_q <= ~rx_b;
        end
    
    // /////////////////////////////////////////////////////////////////////////
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index c1d6767d1..74151ce98 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -413,7 +413,7 @@ module u1plus_core
    // Readback mux 32 -- Slave #7
 
    //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = {16'd9, 16'd3}; //major, minor
+   localparam compat_num = {16'd9, 16'd4}; //major, minor
 
    wire [31:0] reg_test32;
 
diff --git a/fpga/usrp2/top/E1x0/u1e.v b/fpga/usrp2/top/E1x0/u1e.v
index 903ef7a6f..cdf2a7f0d 100644
--- a/fpga/usrp2/top/E1x0/u1e.v
+++ b/fpga/usrp2/top/E1x0/u1e.v
@@ -121,7 +121,18 @@ module u1e
 		.D1(1'b1),   // 1-bit data input (associated with C1)
 		.R(1'b0),       // 1-bit reset input
 		.S(1'b0));      // 1-bit set input
-   
+
+   // /////////////////////////////////////////////////////////////////////////
+   // RX ADC -- handles inversion
+
+    reg [11:0] rx_i, rx_q;
+    always @(posedge clk_fpga) begin
+        rx_i <= ~DA;
+        rx_q <= ~DB;
+    end
+
+   // /////////////////////////////////////////////////////////////////////////
+
    // /////////////////////////////////////////////////////////////////////////
    // Main U1E Core
    u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb),
@@ -138,7 +149,7 @@ module u1e
 		     .rx_have_data(overo_gpio146),
 		     .io_tx(io_tx), .io_rx(io_rx),
 		     .tx_i(tx_i), .tx_q(tx_q), 
-		     .rx_i(DA), .rx_q(DB),
+		     .rx_i(rx_i), .rx_q(rx_q),
 		     .pps_in(PPS_IN), .proc_int(proc_int) );
 
    // /////////////////////////////////////////////////////////////////////////
diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v
index bd19d6076..408aeb240 100644
--- a/fpga/usrp2/top/E1x0/u1e_core.v
+++ b/fpga/usrp2/top/E1x0/u1e_core.v
@@ -454,7 +454,7 @@ module u1e_core
    // Readback mux 32 -- Slave #7
 
    //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = {16'd9, 16'd3}; //major, minor
+   localparam compat_num = {16'd9, 16'd4}; //major, minor
 
    wire [31:0] reg_test32;