Merge branch 'udp' of git@ettus.sourcerepo.com:ettus/fpga into work

1 files changed, 0 insertions, 102 deletions

diff --git a/fpga/usrp2/top/u2_rev1/u2_fpga_top.prj b/fpga/usrp2/top/u2_rev1/u2_fpga_top.prj
deleted file mode 100644
index 544415f4d..000000000
--- a/fpga/usrp2/top/u2_rev1/u2_fpga_top.prj
+++ /dev/null
@@ -1,102 +0,0 @@
-verilog work "../../opencores/uart16550/rtl/verilog/raminfr.v"
-verilog work "../../control_lib/ram_2port.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v"
-verilog work "../../coregen/fifo_generator_v4_1.v"
-verilog work "../../control_lib/shortfifo.v"
-verilog work "../../control_lib/longfifo.v"
-verilog work "../../sdr_lib/sign_extend.v"
-verilog work "../../sdr_lib/cordic_stage.v"
-verilog work "../../sdr_lib/cic_int_shifter.v"
-verilog work "../../sdr_lib/cic_dec_shifter.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_transmitter.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_sync_flops.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_receiver.v"
-verilog work "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_xecu.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_regf.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_ibuf.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_ctrl.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v"
-verilog work "../../opencores/8b10b/encode_8b10b.v"
-verilog work "../../opencores/8b10b/decode_8b10b.v"
-verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v"
-verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v"
-verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v"
-verilog work "../../eth/rtl/verilog/Reg_int.v"
-verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v"
-verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/Random_gen.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
-verilog work "../../control_lib/ss_rcvr.v"
-verilog work "../../control_lib/cascadefifo2.v"
-verilog work "../../control_lib/CRC16_D16.v"
-verilog work "../../timing/time_sender.v"
-verilog work "../../timing/time_receiver.v"
-verilog work "../../serdes/serdes_tx.v"
-verilog work "../../serdes/serdes_rx.v"
-verilog work "../../serdes/serdes_fc_tx.v"
-verilog work "../../serdes/serdes_fc_rx.v"
-verilog work "../../sdr_lib/round.v"
-verilog work "../../sdr_lib/cordic.v"
-verilog work "../../sdr_lib/cic_interp.v"
-verilog work "../../sdr_lib/cic_decim.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_wb.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_regs.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_debug_if.v"
-verilog work "../../opencores/spi/rtl/verilog/spi_shift.v"
-verilog work "../../opencores/spi/rtl/verilog/spi_clgen.v"
-verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_edk32.v"
-verilog work "../../eth/rtl/verilog/flow_ctrl_tx.v"
-verilog work "../../eth/rtl/verilog/flow_ctrl_rx.v"
-verilog work "../../eth/rtl/verilog/eth_miim.v"
-verilog work "../../eth/rtl/verilog/RMON.v"
-verilog work "../../eth/rtl/verilog/Phy_int.v"
-verilog work "../../eth/rtl/verilog/MAC_tx.v"
-verilog work "../../eth/rtl/verilog/MAC_rx.v"
-verilog work "../../eth/rtl/verilog/Clk_ctrl.v"
-verilog work "../../control_lib/strobe_gen.v"
-verilog work "../../control_lib/setting_reg.v"
-verilog work "../../control_lib/mux8.v"
-verilog work "../../control_lib/mux4.v"
-verilog work "../../control_lib/icache.v"
-verilog work "../../control_lib/dpram32.v"
-verilog work "../../control_lib/decoder_3_8.v"
-verilog work "../../control_lib/dcache.v"
-verilog work "../../control_lib/buffer_int.v"
-verilog work "../../timing/timer.v"
-verilog work "../../timing/time_sync.v"
-verilog work "../../serdes/serdes.v"
-verilog work "../../sdr_lib/tx_control.v"
-verilog work "../../sdr_lib/rx_control.v"
-verilog work "../../sdr_lib/dsp_core_tx.v"
-verilog work "../../sdr_lib/dsp_core_rx.v"
-verilog work "../../opencores/uart16550/rtl/verilog/uart_top.v"
-verilog work "../../opencores/spi/rtl/verilog/spi_top.v"
-verilog work "../../opencores/simple_pic/rtl/simple_pic.v"
-verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v"
-verilog work "../../eth/rtl/verilog/MAC_top.v"
-verilog work "../../eth/mac_txfifo_int.v"
-verilog work "../../eth/mac_rxfifo_int.v"
-verilog work "../../control_lib/wb_readback_mux.v"
-verilog work "../../control_lib/wb_1master.v"
-verilog work "../../control_lib/system_control.v"
-verilog work "../../control_lib/settings_bus.v"
-verilog work "../../control_lib/ram_loader.v"
-verilog work "../../control_lib/ram_harv_cache.v"
-verilog work "../../control_lib/nsgpio.v"
-verilog work "../../control_lib/extram_interface.v"
-verilog work "../../control_lib/buffer_pool.v"
-verilog work "../../control_lib/atr_controller.v"
-verilog work "../u2_basic/u2_basic.v"
-verilog work "u2_fpga_top.v"