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authorJosh Blum <josh@joshknows.com>2011-03-17 13:53:48 -0700
committerJosh Blum <josh@joshknows.com>2011-03-17 13:53:48 -0700
commitee424d797fc37a8c3c2a82a58218bf1e85456226 (patch)
tree74b179d55122df0a156f82ef25dd42895bb52487 /fpga/usrp2/top/u1e
parentb52877b3d9af48ecde6f5378755e8c2337a41921 (diff)
parentbe2c1b95c1d6f4ad2ea663bb926a04463edb9358 (diff)
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Merge branch 'fpga_memory_reorg' into usrp2/new_reg_map
Diffstat (limited to 'fpga/usrp2/top/u1e')
-rw-r--r--fpga/usrp2/top/u1e/u1e_core.v1
1 files changed, 0 insertions, 1 deletions
diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v
index a5a477202..b3d71b4ab 100644
--- a/fpga/usrp2/top/u1e/u1e_core.v
+++ b/fpga/usrp2/top/u1e/u1e_core.v
@@ -152,7 +152,6 @@ module u1e_core
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy),
.data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy),
- .fifo_occupied(), .fifo_full(), .fifo_empty(),
.debug_rx(vrf_debug) );
fifo36_mux #(.prio(0)) mux_err_stream