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authorJosh Blum <josh@joshknows.com>2010-11-23 13:53:14 -0800
committerJosh Blum <josh@joshknows.com>2010-11-23 13:53:14 -0800
commit18ce33d2286a428705bc19e5dc091f2d6a6d4d5b (patch)
treec355fbde9d8804b29ab76bef7412874fe03955a1 /fpga/usrp2/top/u1e
parent30ce5acedd3e0dc6fc97d7597781a0a4828812f2 (diff)
parent74bb6b39d9a677e6a7a41b6e3d62488aa265f706 (diff)
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Merge branch 'fpga_next' into next
Conflicts: fpga/usrp2/top/u1e_passthru/.gitignore fpga/usrp2/top/u1e_passthru/Makefile fpga/usrp2/top/u2plus/.gitignore fpga/usrp2/top/u2plus/Makefile usrp2/top/u1e_passthru/.gitignore usrp2/top/u1e_passthru/Makefile
Diffstat (limited to 'fpga/usrp2/top/u1e')
-rw-r--r--fpga/usrp2/top/u1e/u1e_core.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v
index 619e44b8a..e7e798b34 100644
--- a/fpga/usrp2/top/u1e/u1e_core.v
+++ b/fpga/usrp2/top/u1e/u1e_core.v
@@ -36,7 +36,7 @@ module u1e_core
localparam SR_TX_CTRL = 24; // 2 regs
localparam SR_TIME64 = 28; // 4 regs
- wire COMPAT_NUM = 8'd2;
+ wire [7:0] COMPAT_NUM = 8'd2;
wire wb_clk = clk_fpga;
wire wb_rst = rst_fpga;
@@ -344,7 +344,7 @@ module u1e_core
assign rx_enable = xfer_rate[14];
assign rate = xfer_rate[7:0];
- assign { debug_led[3:0] } = {run_rx,run_tx,reg_leds[1:0]};
+ assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]};
assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds :