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author | Josh Blum <josh@joshknows.com> | 2010-11-23 13:36:42 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-11-23 13:36:42 -0800 |
commit | bb0572a960edf54486a4be746c681adaac0fa398 (patch) | |
tree | 7afb46e99eaf799a478fcde841eb78d7698e9c39 /fpga/usrp2/top/u1e/timing.ucf | |
parent | 8ce75a3ca7a51f4bdee87d78a610a0f2519473ae (diff) | |
download | uhd-bb0572a960edf54486a4be746c681adaac0fa398.tar.gz uhd-bb0572a960edf54486a4be746c681adaac0fa398.tar.bz2 uhd-bb0572a960edf54486a4be746c681adaac0fa398.zip |
fpga: performed a forceful checkout of fpga to overwrite with current fpga code
Diffstat (limited to 'fpga/usrp2/top/u1e/timing.ucf')
-rw-r--r-- | fpga/usrp2/top/u1e/timing.ucf | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/fpga/usrp2/top/u1e/timing.ucf b/fpga/usrp2/top/u1e/timing.ucf new file mode 100644 index 000000000..8df28c9d3 --- /dev/null +++ b/fpga/usrp2/top/u1e/timing.ucf @@ -0,0 +1,13 @@ + +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + + + + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; |