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| author | Josh Blum <josh@joshknows.com> | 2011-05-16 11:58:03 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-05-16 11:58:03 -0700 |
| commit | 13be023531fa1be8d43b999c3ea5ab477f101fdc (patch) | |
| tree | 9a24a949aa0d30b9a992d89c232ae1b812b3c09f /fpga/usrp2/top/u1e/core_compile | |
| parent | e6e010e02a12359a31e70ac7fe2ae7c39fa3e9d6 (diff) | |
| parent | c8565df0e51922443426a0392f5f1fb4e3743ce1 (diff) | |
| download | uhd-13be023531fa1be8d43b999c3ea5ab477f101fdc.tar.gz uhd-13be023531fa1be8d43b999c3ea5ab477f101fdc.tar.bz2 uhd-13be023531fa1be8d43b999c3ea5ab477f101fdc.zip | |
Merge branch 'use_vita_length' into next
Diffstat (limited to 'fpga/usrp2/top/u1e/core_compile')
| -rwxr-xr-x | fpga/usrp2/top/u1e/core_compile | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/fpga/usrp2/top/u1e/core_compile b/fpga/usrp2/top/u1e/core_compile new file mode 100755 index 000000000..dc0cd081e --- /dev/null +++ b/fpga/usrp2/top/u1e/core_compile @@ -0,0 +1,3 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models + + |