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authorJosh Blum <josh@joshknows.com>2010-11-23 15:35:48 -0800
committerJosh Blum <josh@joshknows.com>2010-11-23 15:35:48 -0800
commitf56c1247cbe7b7e90acee2711b5dda3356b9486a (patch)
tree81dadc83537c2c50550cd94e224571e472176c6f /fpga/usrp2/top/u1e/cmdfile
parent9f94ef843ceca63bcb83b2d473cbba709c9110b6 (diff)
parenteb26e8adb4a5718ee3db3bb7f32c0cd31d060af9 (diff)
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Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next
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+
+# My stuff
+-y .
+-y ../../control_lib
+-y ../../control_lib/newfifo
+-y ../../sdr_lib
+-y ../../timing
+-y ../../coregen
+-y ../../gpmc
+
+# Models
+-y ../../models
+-y /opt/Xilinx/10.1/ISE/verilog/src/unisims
+
+# Open Cores
+-y ../../opencores/spi/rtl/verilog
++incdir+../../opencores/spi/rtl/verilog
+-y ../../opencores/i2c/rtl/verilog
++incdir+../../opencores/i2c/rtl/verilog
+