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| author | Josh Blum <josh@joshknows.com> | 2010-11-23 13:36:42 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-23 13:36:42 -0800 |
| commit | bb0572a960edf54486a4be746c681adaac0fa398 (patch) | |
| tree | 7afb46e99eaf799a478fcde841eb78d7698e9c39 /fpga/usrp2/top/u1e/cmdfile | |
| parent | 8ce75a3ca7a51f4bdee87d78a610a0f2519473ae (diff) | |
| download | uhd-bb0572a960edf54486a4be746c681adaac0fa398.tar.gz uhd-bb0572a960edf54486a4be746c681adaac0fa398.tar.bz2 uhd-bb0572a960edf54486a4be746c681adaac0fa398.zip | |
fpga: performed a forceful checkout of fpga to overwrite with current fpga code
Diffstat (limited to 'fpga/usrp2/top/u1e/cmdfile')
| -rw-r--r-- | fpga/usrp2/top/u1e/cmdfile | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/fpga/usrp2/top/u1e/cmdfile b/fpga/usrp2/top/u1e/cmdfile new file mode 100644 index 000000000..291c723b8 --- /dev/null +++ b/fpga/usrp2/top/u1e/cmdfile @@ -0,0 +1,20 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims + +# Open Cores +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog + |