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| author | Philip Balister <philip@opensdr.com> | 2010-11-04 08:02:10 -0400 |
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| committer | Philip Balister <philip@opensdr.com> | 2010-11-04 08:02:10 -0400 |
| commit | 40080e474268291c915f8d68e99506e8ae2a3f75 (patch) | |
| tree | 99581ec02c77b08a11f38af901dc9db35adcbe3a /fpga/usrp2/top/u1e/cmdfile | |
| parent | 7f8d7b0e2fef1b2d5bb9c8047380dcf958c0c49c (diff) | |
| parent | 16351339eb6962288844cefefbdb3f6eece8aca1 (diff) | |
| download | uhd-40080e474268291c915f8d68e99506e8ae2a3f75.tar.gz uhd-40080e474268291c915f8d68e99506e8ae2a3f75.tar.bz2 uhd-40080e474268291c915f8d68e99506e8ae2a3f75.zip | |
Merge remote branch 'origin/usrp_e_next' into usrp_e_next
Diffstat (limited to 'fpga/usrp2/top/u1e/cmdfile')
| -rw-r--r-- | fpga/usrp2/top/u1e/cmdfile | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/fpga/usrp2/top/u1e/cmdfile b/fpga/usrp2/top/u1e/cmdfile new file mode 100644 index 000000000..291c723b8 --- /dev/null +++ b/fpga/usrp2/top/u1e/cmdfile @@ -0,0 +1,20 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims + +# Open Cores +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog + |