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| author | Josh Blum <josh@joshknows.com> | 2010-11-23 13:50:37 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-23 13:50:37 -0800 |
| commit | 30ce5acedd3e0dc6fc97d7597781a0a4828812f2 (patch) | |
| tree | 28d010c0938121f587e1820849c34ee900e7f74b /fpga/usrp2/top/u1e/cmdfile | |
| parent | 8ce75a3ca7a51f4bdee87d78a610a0f2519473ae (diff) | |
| parent | 13ae4786e091d5581baf31c9967dca822ef15e39 (diff) | |
| download | uhd-30ce5acedd3e0dc6fc97d7597781a0a4828812f2.tar.gz uhd-30ce5acedd3e0dc6fc97d7597781a0a4828812f2.tar.bz2 uhd-30ce5acedd3e0dc6fc97d7597781a0a4828812f2.zip | |
Merge branch 'usrp_e100' into next
Conflicts:
images/Makefile
Diffstat (limited to 'fpga/usrp2/top/u1e/cmdfile')
| -rw-r--r-- | fpga/usrp2/top/u1e/cmdfile | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/fpga/usrp2/top/u1e/cmdfile b/fpga/usrp2/top/u1e/cmdfile new file mode 100644 index 000000000..291c723b8 --- /dev/null +++ b/fpga/usrp2/top/u1e/cmdfile @@ -0,0 +1,20 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims + +# Open Cores +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog + |