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| author | Josh Blum <josh@joshknows.com> | 2012-07-19 21:06:07 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-07-19 21:06:07 -0700 |
| commit | 73c2c25c11069e32918eb592209539bb563e55c2 (patch) | |
| tree | 14d8134a93987c5353108494e68d2cde8ec29412 /fpga/usrp2/top/E1x0/core_compile | |
| parent | b4f3b83acbe8d3b69767d7c23b4bc798095c8214 (diff) | |
| parent | a8a02f97a89597aac8310dd1adff6909e62cb7b4 (diff) | |
| download | uhd-73c2c25c11069e32918eb592209539bb563e55c2.tar.gz uhd-73c2c25c11069e32918eb592209539bb563e55c2.tar.bz2 uhd-73c2c25c11069e32918eb592209539bb563e55c2.zip | |
Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/top/E1x0/core_compile')
| -rwxr-xr-x | fpga/usrp2/top/E1x0/core_compile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/E1x0/core_compile b/fpga/usrp2/top/E1x0/core_compile index dd88094ff..ab992f29d 100755 --- a/fpga/usrp2/top/E1x0/core_compile +++ b/fpga/usrp2/top/E1x0/core_compile @@ -1,3 +1,3 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../B100 -y $XILINX/verilog/src/unisims E100.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../B100 -y $XILINX/verilog/src/unisims E1x0.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |