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| author | Josh Blum <josh@joshknows.com> | 2012-02-17 18:18:26 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-17 18:18:26 -0800 |
| commit | 3ddbcb6078593c39cb0e4bc8f9769f818a61466f (patch) | |
| tree | 408e3f6a64e31b7d830b9f884ecebdaf100a5d2d /fpga/usrp2/top/E1x0/core_compile | |
| parent | 1fab7e9d477aa98e489400c25a08358952c69c90 (diff) | |
| parent | ace4489066d1621a09e70650a00d736f0b03ed8c (diff) | |
| download | uhd-3ddbcb6078593c39cb0e4bc8f9769f818a61466f.tar.gz uhd-3ddbcb6078593c39cb0e4bc8f9769f818a61466f.tar.bz2 uhd-3ddbcb6078593c39cb0e4bc8f9769f818a61466f.zip | |
Merge branch 'next'
Diffstat (limited to 'fpga/usrp2/top/E1x0/core_compile')
| -rwxr-xr-x | fpga/usrp2/top/E1x0/core_compile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/E1x0/core_compile b/fpga/usrp2/top/E1x0/core_compile index 02d7f006e..14e138fa3 100755 --- a/fpga/usrp2/top/E1x0/core_compile +++ b/fpga/usrp2/top/E1x0/core_compile @@ -1,3 +1,3 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |