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| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp2/top/E1x0/cmdfile | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp2/top/E1x0/cmdfile')
| -rw-r--r-- | fpga/usrp2/top/E1x0/cmdfile | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/fpga/usrp2/top/E1x0/cmdfile b/fpga/usrp2/top/E1x0/cmdfile deleted file mode 100644 index 291c723b8..000000000 --- a/fpga/usrp2/top/E1x0/cmdfile +++ /dev/null @@ -1,20 +0,0 @@ - -# My stuff --y . --y ../../control_lib --y ../../control_lib/newfifo --y ../../sdr_lib --y ../../timing --y ../../coregen --y ../../gpmc - -# Models --y ../../models --y /opt/Xilinx/10.1/ISE/verilog/src/unisims - -# Open Cores --y ../../opencores/spi/rtl/verilog -+incdir+../../opencores/spi/rtl/verilog --y ../../opencores/i2c/rtl/verilog -+incdir+../../opencores/i2c/rtl/verilog - |