diff options
| author | Josh Blum <josh@joshknows.com> | 2011-06-15 14:50:02 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-06-15 14:50:02 -0700 |
| commit | 0cef788d3d34a298c975e32c488e800a5c65ccce (patch) | |
| tree | 14b7f4242a28927b1701a73a3e8ec0df3fa04811 /fpga/usrp2/top/E1x0/cmdfile | |
| parent | 7951170c6161d9266726ec19e8c009500cf11f75 (diff) | |
| parent | 27f1622d439ceb787e7dada733d0eb82270c5532 (diff) | |
| download | uhd-0cef788d3d34a298c975e32c488e800a5c65ccce.tar.gz uhd-0cef788d3d34a298c975e32c488e800a5c65ccce.tar.bz2 uhd-0cef788d3d34a298c975e32c488e800a5c65ccce.zip | |
Merge branch 'next'
Diffstat (limited to 'fpga/usrp2/top/E1x0/cmdfile')
| -rw-r--r-- | fpga/usrp2/top/E1x0/cmdfile | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/fpga/usrp2/top/E1x0/cmdfile b/fpga/usrp2/top/E1x0/cmdfile new file mode 100644 index 000000000..291c723b8 --- /dev/null +++ b/fpga/usrp2/top/E1x0/cmdfile @@ -0,0 +1,20 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims + +# Open Cores +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog + |