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| author | Josh Blum <josh@joshknows.com> | 2012-10-05 12:50:08 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-10-05 12:50:08 -0700 |
| commit | d14ff607b2b475dfd249fb99d7071ed367521a98 (patch) | |
| tree | 7460f566f0b42341ea2ea0e2eff0ec2c75d9f783 /fpga/usrp2/top/B100/u1plus_core.v | |
| parent | 390752c6d9cca370e6b6d6781e54b42ac4eac9a2 (diff) | |
| parent | 02b246fff2f272dd7b17e8c1fdca3a20dd17280a (diff) | |
| download | uhd-d14ff607b2b475dfd249fb99d7071ed367521a98.tar.gz uhd-d14ff607b2b475dfd249fb99d7071ed367521a98.tar.bz2 uhd-d14ff607b2b475dfd249fb99d7071ed367521a98.zip | |
Merge branch 'b100_2rx'
Diffstat (limited to 'fpga/usrp2/top/B100/u1plus_core.v')
| -rw-r--r-- | fpga/usrp2/top/B100/u1plus_core.v | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v index 9ffbaa202..ef0ce51f7 100644 --- a/fpga/usrp2/top/B100/u1plus_core.v +++ b/fpga/usrp2/top/B100/u1plus_core.v @@ -316,6 +316,12 @@ module u1plus_core wire [31:0] sample_tx; wire strobe_tx, clear_tx; +`ifdef DISABLE_TX_DSP + assign tx_dst_rdy = 1; //null sink + assign run_tx = 0; + assign tx_i = 0; + assign tx_q = 0; +`else vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE), .POST_ENGINE_FIFOSIZE(DSP_TX_XTRA_FIFOSIZE), @@ -346,7 +352,7 @@ module u1plus_core .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1), .dac_a(tx_i), .dac_b(tx_q)); - +`endif // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry |