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| author | Josh Blum <josh@joshknows.com> | 2011-06-14 17:29:21 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-06-14 17:29:21 -0700 |
| commit | dd157937466f3ee18b08712625eba84582a913f3 (patch) | |
| tree | 6a4eadb148a2c8141032b78d3c521d56c1f34910 /fpga/usrp2/top/B100/core_compile | |
| parent | a1f36ebf436fccbb6cc81bb5f32a790d444772c2 (diff) | |
| parent | c0fadece89314f3a00892122c28caf187ce1a717 (diff) | |
| download | uhd-dd157937466f3ee18b08712625eba84582a913f3.tar.gz uhd-dd157937466f3ee18b08712625eba84582a913f3.tar.bz2 uhd-dd157937466f3ee18b08712625eba84582a913f3.zip | |
Merge branch 'fpga_next' into uhd_next
Diffstat (limited to 'fpga/usrp2/top/B100/core_compile')
| -rwxr-xr-x | fpga/usrp2/top/B100/core_compile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/usrp2/top/B100/core_compile b/fpga/usrp2/top/B100/core_compile new file mode 100755 index 000000000..b2ccc8b49 --- /dev/null +++ b/fpga/usrp2/top/B100/core_compile @@ -0,0 +1 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |