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| author | Josh Blum <josh@joshknows.com> | 2012-02-17 16:55:59 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-17 16:55:59 -0800 |
| commit | ace4489066d1621a09e70650a00d736f0b03ed8c (patch) | |
| tree | f02b34b70da9e9beb0f34dc5e64d48daa5aa4bf6 /fpga/usrp2/top/B100/core_compile | |
| parent | 8f8ac3397aaa85b64aaa8722efdc1c0c40e93052 (diff) | |
| parent | 2e37dd87234e5beddd6f76fcda714916f761f812 (diff) | |
| download | uhd-ace4489066d1621a09e70650a00d736f0b03ed8c.tar.gz uhd-ace4489066d1621a09e70650a00d736f0b03ed8c.tar.bz2 uhd-ace4489066d1621a09e70650a00d736f0b03ed8c.zip | |
Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/top/B100/core_compile')
| -rwxr-xr-x | fpga/usrp2/top/B100/core_compile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/B100/core_compile b/fpga/usrp2/top/B100/core_compile index b2ccc8b49..b62cbaee0 100755 --- a/fpga/usrp2/top/B100/core_compile +++ b/fpga/usrp2/top/B100/core_compile @@ -1 +1 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |