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| author | Josh Blum <josh@joshknows.com> | 2012-07-02 14:11:43 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-07-02 14:11:43 -0700 |
| commit | 45c1af8152d02cd7d4e5d5d603e1cca65f6dd539 (patch) | |
| tree | 2a48c592cef637476c2566fc64675dcdac8a7b05 /fpga/usrp2/top/B100/core_compile | |
| parent | 7a1824e8fddadd915e2d7490a8b57764b815b09f (diff) | |
| parent | 295c7e7b98df98989f3fb4505e44f0be52813d81 (diff) | |
| download | uhd-45c1af8152d02cd7d4e5d5d603e1cca65f6dd539.tar.gz uhd-45c1af8152d02cd7d4e5d5d603e1cca65f6dd539.tar.bz2 uhd-45c1af8152d02cd7d4e5d5d603e1cca65f6dd539.zip | |
Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/top/B100/core_compile')
| -rwxr-xr-x | fpga/usrp2/top/B100/core_compile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/B100/core_compile b/fpga/usrp2/top/B100/core_compile index b62cbaee0..2192bfa94 100755 --- a/fpga/usrp2/top/B100/core_compile +++ b/fpga/usrp2/top/B100/core_compile @@ -1 +1 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac B100.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |