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| author | Josh Blum <josh@joshknows.com> | 2011-06-15 14:50:02 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-06-15 14:50:02 -0700 |
| commit | 0cef788d3d34a298c975e32c488e800a5c65ccce (patch) | |
| tree | 14b7f4242a28927b1701a73a3e8ec0df3fa04811 /fpga/usrp2/top/B100/core_compile | |
| parent | 7951170c6161d9266726ec19e8c009500cf11f75 (diff) | |
| parent | 27f1622d439ceb787e7dada733d0eb82270c5532 (diff) | |
| download | uhd-0cef788d3d34a298c975e32c488e800a5c65ccce.tar.gz uhd-0cef788d3d34a298c975e32c488e800a5c65ccce.tar.bz2 uhd-0cef788d3d34a298c975e32c488e800a5c65ccce.zip | |
Merge branch 'next'
Diffstat (limited to 'fpga/usrp2/top/B100/core_compile')
| -rwxr-xr-x | fpga/usrp2/top/B100/core_compile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/usrp2/top/B100/core_compile b/fpga/usrp2/top/B100/core_compile new file mode 100755 index 000000000..b2ccc8b49 --- /dev/null +++ b/fpga/usrp2/top/B100/core_compile @@ -0,0 +1 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |