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authorJosh Blum <josh@joshknows.com>2010-04-15 11:24:41 -0700
committerJosh Blum <josh@joshknows.com>2010-04-15 11:24:41 -0700
commit3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch)
tree784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp2/timing/timer.v
parentcbf7a0916f0455743d8446a8edc0f0775e3e63ed (diff)
parent05d77f772317de5d925301aa11bb9a880656dd05 (diff)
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Merge branch 'udp'
Diffstat (limited to 'fpga/usrp2/timing/timer.v')
-rw-r--r--fpga/usrp2/timing/timer.v40
1 files changed, 40 insertions, 0 deletions
diff --git a/fpga/usrp2/timing/timer.v b/fpga/usrp2/timing/timer.v
new file mode 100644
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+++ b/fpga/usrp2/timing/timer.v
@@ -0,0 +1,40 @@
+
+
+module timer
+ (input wb_clk_i, input rst_i,
+ input cyc_i, input stb_i, input [2:0] adr_i,
+ input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o,
+ input sys_clk_i, input [31:0] master_time_i,
+ output int_o );
+
+ reg [31:0] time_wb;
+ always @(posedge wb_clk_i)
+ time_wb <= master_time_i;
+
+ assign ack_o = stb_i;
+
+ reg [31:0] int_time;
+ reg int_reg;
+
+ always @(posedge sys_clk_i)
+ if(rst_i)
+ begin
+ int_time <= 0;
+ int_reg <= 0;
+ end
+ else if(|int_time && (master_time_i == int_time))
+ begin
+ int_time <= 0;
+ int_reg <= 1;
+ end
+ else if(stb_i & we_i)
+ begin
+ int_time <= dat_i;
+ int_reg <= 0;
+ end
+
+ assign dat_o = time_wb;
+ assign int_o = int_reg;
+
+endmodule // timer
+