From 05d77f772317de5d925301aa11bb9a880656dd05 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Thu, 15 Apr 2010 11:24:24 -0700
Subject: moved usrp1 and usrp2 fpga dirs into fpga subdirectory

---
 fpga/usrp2/timing/timer.v | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 fpga/usrp2/timing/timer.v

(limited to 'fpga/usrp2/timing/timer.v')

diff --git a/fpga/usrp2/timing/timer.v b/fpga/usrp2/timing/timer.v
new file mode 100644
index 000000000..70c9746be
--- /dev/null
+++ b/fpga/usrp2/timing/timer.v
@@ -0,0 +1,40 @@
+
+
+module timer
+  (input wb_clk_i, input rst_i,
+   input cyc_i, input stb_i, input [2:0] adr_i,
+   input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o,
+   input sys_clk_i, input [31:0] master_time_i,
+   output int_o );
+
+   reg [31:0] time_wb;
+   always @(posedge wb_clk_i)
+     time_wb <= master_time_i;
+
+   assign     ack_o = stb_i;
+
+   reg [31:0] int_time;
+   reg 	      int_reg;
+   
+   always @(posedge sys_clk_i)
+     if(rst_i)
+       begin
+	  int_time <= 0;
+	  int_reg <= 0;
+       end
+     else if(|int_time && (master_time_i == int_time))
+       begin
+	  int_time <= 0;
+	  int_reg <= 1;
+       end
+     else if(stb_i & we_i)
+       begin
+	  int_time <= dat_i;
+	  int_reg <= 0;
+       end
+
+   assign dat_o = time_wb;
+   assign int_o = int_reg;
+   
+endmodule // timer
+
-- 
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