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author | Josh Blum <josh@joshknows.com> | 2010-04-16 09:42:46 +0000 |
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committer | Josh Blum <josh@joshknows.com> | 2010-04-16 09:42:46 +0000 |
commit | 835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25 (patch) | |
tree | 4fe48bdaf92311deedfbe1a5e77dd209468a2d7d /fpga/usrp2/timing/time_compare.v | |
parent | f1838b9284a124fcfb5996eaf1647a69b4473278 (diff) | |
parent | 067491b58676cbdaa754334949a8ffc2daf32979 (diff) | |
download | uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.tar.gz uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.tar.bz2 uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.zip |
Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts:
.gitignore
Diffstat (limited to 'fpga/usrp2/timing/time_compare.v')
-rw-r--r-- | fpga/usrp2/timing/time_compare.v | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/fpga/usrp2/timing/time_compare.v b/fpga/usrp2/timing/time_compare.v new file mode 100644 index 000000000..a21c9f8e0 --- /dev/null +++ b/fpga/usrp2/timing/time_compare.v @@ -0,0 +1,23 @@ + +// Top 32 bits are integer seconds, bottom 32 are clock ticks within a second + +module time_compare + (input [63:0] time_now, + input [63:0] trigger_time, + output now, + output early, + output late, + output too_early); + + wire sec_match = (time_now[63:32] == trigger_time[63:32]); + wire sec_late = (time_now[63:32] > trigger_time[63:32]); + + wire tick_match = (time_now[31:0] == trigger_time[31:0]); + wire tick_late = (time_now[31:0] > trigger_time[31:0]); + + assign now = sec_match & tick_match; + assign late = sec_late | (sec_match & tick_late); + assign early = ~now & ~late; + assign too_early = (trigger_time[63:32] > (time_now[63:32] + 4)); // Don't wait too long + +endmodule // time_compare |