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authorJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
committerJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
commit835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25 (patch)
tree4fe48bdaf92311deedfbe1a5e77dd209468a2d7d /fpga/usrp2/timing/time_compare.v
parentf1838b9284a124fcfb5996eaf1647a69b4473278 (diff)
parent067491b58676cbdaa754334949a8ffc2daf32979 (diff)
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Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts: .gitignore
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diff --git a/fpga/usrp2/timing/time_compare.v b/fpga/usrp2/timing/time_compare.v
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+
+// Top 32 bits are integer seconds, bottom 32 are clock ticks within a second
+
+module time_compare
+ (input [63:0] time_now,
+ input [63:0] trigger_time,
+ output now,
+ output early,
+ output late,
+ output too_early);
+
+ wire sec_match = (time_now[63:32] == trigger_time[63:32]);
+ wire sec_late = (time_now[63:32] > trigger_time[63:32]);
+
+ wire tick_match = (time_now[31:0] == trigger_time[31:0]);
+ wire tick_late = (time_now[31:0] > trigger_time[31:0]);
+
+ assign now = sec_match & tick_match;
+ assign late = sec_late | (sec_match & tick_late);
+ assign early = ~now & ~late;
+ assign too_early = (trigger_time[63:32] > (time_now[63:32] + 4)); // Don't wait too long
+
+endmodule // time_compare