Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

4 files changed, 928 insertions, 0 deletions

diff --git a/fpga/usrp2/simple_gemac/miim/eth_clockgen.v b/fpga/usrp2/simple_gemac/miim/eth_clockgen.v
new file mode 100644
index 000000000..5fe9001b2
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/miim/eth_clockgen.v
@@ -0,0 +1,141 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  eth_clockgen.v                                              ////
+////                                                              ////
+////  This file is part of the Ethernet IP core project           ////
+////  http://www.opencores.org/projects/ethmac/                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Igor Mohor (igorM@opencores.org)                      ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2001 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: eth_clockgen.v,v $
+// Revision 1.2  2005/12/13 12:54:49  maverickist
+// first simulation passed
+//
+// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
+// no message
+//
+// Revision 1.2  2005/04/27 15:58:45  Administrator
+// no message
+//
+// Revision 1.1.1.1  2004/12/15 06:38:54  Administrator
+// no message
+//
+// Revision 1.3  2002/01/23 10:28:16  mohor
+// Link in the header changed.
+//
+// Revision 1.2  2001/10/19 08:43:51  mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1  2001/08/06 14:44:29  mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1  2001/07/30 21:23:42  mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3  2001/06/01 22:28:55  mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
+//
+//
+
+module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
+
+//parameter Tp=1;
+
+input       Clk;              // Input clock (Host clock)
+input       Reset;            // Reset signal
+input [7:0] Divider;          // Divider (input clock will be divided by the Divider[7:0])
+
+output      Mdc;              // Output clock
+output      MdcEn;            // Enable signal is asserted for one Clk period before Mdc rises.
+output      MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.
+
+reg         Mdc;
+reg   [7:0] Counter;
+
+wire        CountEq0;
+wire  [7:0] CounterPreset;
+wire  [7:0] TempDivider;
+
+
+assign TempDivider[7:0]   = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
+assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1;               // We are counting half of period
+
+
+// Counter counts half period
+always @ (posedge Clk or posedge Reset)
+begin
+  if(Reset)
+    Counter[7:0] <= 8'h1;
+  else
+    begin
+      if(CountEq0)
+        begin
+          Counter[7:0] <= CounterPreset[7:0];
+        end
+      else
+        Counter[7:0] <= Counter - 8'h1;
+    end
+end
+
+
+// Mdc is asserted every other half period
+always @ (posedge Clk or posedge Reset)
+begin
+  if(Reset)
+    Mdc <= 1'b0;
+  else
+    begin
+      if(CountEq0)
+        Mdc <= ~Mdc;
+    end
+end
+
+
+assign CountEq0 = Counter == 8'h0;
+assign MdcEn = CountEq0 & ~Mdc;
+assign MdcEn_n = CountEq0 & Mdc;
+
+endmodule
+
+
diff --git a/fpga/usrp2/simple_gemac/miim/eth_miim.v b/fpga/usrp2/simple_gemac/miim/eth_miim.v
new file mode 100644
index 000000000..ed851e482
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/miim/eth_miim.v
@@ -0,0 +1,470 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  eth_miim.v                                                  ////
+////                                                              ////
+////  This file is part of the Ethernet IP core project           ////
+////  http://www.opencores.org/projects/ethmac/                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Igor Mohor (igorM@opencores.org)                      ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2001 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: eth_miim.v,v $
+// Revision 1.3  2006/01/19 14:07:53  maverickist
+// verification is complete.
+//
+// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
+// no message
+//
+// Revision 1.4  2005/08/16 12:07:57  Administrator
+// no message
+//
+// Revision 1.3  2005/05/19 07:04:29  Administrator
+// no message
+//
+// Revision 1.2  2005/04/27 15:58:46  Administrator
+// no message
+//
+// Revision 1.1.1.1  2004/12/15 06:38:54  Administrator
+// no message
+//
+// Revision 1.5  2003/05/16 10:08:27  mohor
+// Busy was set 2 cycles too late. Reported by Dennis Scott.
+//
+// Revision 1.4  2002/08/14 18:32:10  mohor
+// - Busy signal was not set on time when scan status operation was performed
+// and clock was divided with more than 2.
+// - Nvalid remains valid two more clocks (was previously cleared too soon).
+//
+// Revision 1.3  2002/01/23 10:28:16  mohor
+// Link in the header changed.
+//
+// Revision 1.2  2001/10/19 08:43:51  mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1  2001/08/06 14:44:29  mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.2  2001/08/02 09:25:31  mohor
+// Unconnected signals are now connected.
+//
+// Revision 1.1  2001/07/30 21:23:42  mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3  2001/06/01 22:28:56  mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
+//
+//
+
+module eth_miim
+(
+  Clk,
+  Reset,
+  Divider,
+  NoPre,
+  CtrlData,
+  Rgad,
+  Fiad,
+  WCtrlData,
+  RStat,
+  ScanStat,
+  Mdio,
+  Mdc,
+  Busy,
+  Prsd,
+  LinkFail,
+  Nvalid,
+  WCtrlDataStart,
+  RStatStart,
+  UpdateMIIRX_DATAReg
+);
+
+input         Clk;                // Host Clock
+input         Reset;              // General Reset
+input   [7:0] Divider;            // Divider for the host clock
+input  [15:0] CtrlData;           // Control Data (to be written to the PHY reg.)
+input   [4:0] Rgad;               // Register Address (within the PHY)
+input   [4:0] Fiad;               // PHY Address
+input         NoPre;              // No Preamble (no 32-bit preamble)
+input         WCtrlData;          // Write Control Data operation
+input         RStat;              // Read Status operation
+input         ScanStat;           // Scan Status operation
+inout         Mdio;                // MII Management Data In
+
+output        Mdc;                // MII Management Data Clock
+
+output        Busy;               // Busy Signal
+output        LinkFail;           // Link Integrity Signal
+output        Nvalid;             // Invalid Status (qualifier for the valid scan result)
+
+output [15:0] Prsd;               // Read Status Data (data read from the PHY)
+
+output        WCtrlDataStart;     // This signals resets the WCTRLDATA bit in the MIIM Command register
+output        RStatStart;         // This signal resets the RSTAT BIT in the MIIM Command register
+output        UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
+
+//parameter Tp = 1;
+
+
+reg           Nvalid;
+reg           EndBusy_d;          // Pre-end Busy signal
+reg           EndBusy;            // End Busy signal (stops the operation in progress)
+
+reg           WCtrlData_q1;       // Write Control Data operation delayed 1 Clk cycle
+reg           WCtrlData_q2;       // Write Control Data operation delayed 2 Clk cycles
+reg           WCtrlData_q3;       // Write Control Data operation delayed 3 Clk cycles
+reg           WCtrlDataStart;     // Start Write Control Data Command (positive edge detected)
+reg           WCtrlDataStart_q;
+reg           WCtrlDataStart_q1;  // Start Write Control Data Command delayed 1 Mdc cycle
+reg           WCtrlDataStart_q2;  // Start Write Control Data Command delayed 2 Mdc cycles
+
+reg           RStat_q1;           // Read Status operation delayed 1 Clk cycle
+reg           RStat_q2;           // Read Status operation delayed 2 Clk cycles
+reg           RStat_q3;           // Read Status operation delayed 3 Clk cycles
+reg           RStatStart;         // Start Read Status Command (positive edge detected)
+reg           RStatStart_q1;      // Start Read Status Command delayed 1 Mdc cycle
+reg           RStatStart_q2;      // Start Read Status Command delayed 2 Mdc cycles
+
+reg           ScanStat_q1;        // Scan Status operation delayed 1 cycle
+reg           ScanStat_q2;        // Scan Status operation delayed 2 cycles
+reg           SyncStatMdcEn;      // Scan Status operation delayed at least cycles and synchronized to MdcEn
+
+wire          WriteDataOp;        // Write Data Operation (positive edge detected)
+wire          ReadStatusOp;       // Read Status Operation (positive edge detected)
+wire          ScanStatusOp;       // Scan Status Operation (positive edge detected)
+wire          StartOp;            // Start Operation (start of any of the preceding operations)
+wire          EndOp;              // End of Operation
+
+reg           InProgress;         // Operation in progress
+reg           InProgress_q1;      // Operation in progress delayed 1 Mdc cycle
+reg           InProgress_q2;      // Operation in progress delayed 2 Mdc cycles
+reg           InProgress_q3;      // Operation in progress delayed 3 Mdc cycles
+
+reg           WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
+reg     [6:0] BitCounter;         // Bit Counter
+
+
+wire    [3:0] ByteSelect;         // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
+wire          MdcEn;              // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
+wire          ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal
+
+
+wire          LatchByte1_d2;
+wire          LatchByte0_d2;
+reg           LatchByte1_d;
+reg           LatchByte0_d;
+reg     [1:0] LatchByte;          // Latch Byte selects which part of Read Status Data is updated from the shift register
+
+reg           UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
+
+wire        Mdo;                // MII Management Data Output
+wire        MdoEn;              // MII Management Data Output Enable
+wire		Mdi;
+
+assign  Mdi=Mdio;
+assign  Mdio=MdoEn?Mdo:1'bz;
+
+
+
+// Generation of the EndBusy signal. It is used for ending the MII Management operation.
+always @ (posedge Clk or posedge Reset)
+begin
+  if(Reset)
+    begin
+      EndBusy_d <= 1'b0;
+      EndBusy <= 1'b0;
+    end
+  else
+    begin
+      EndBusy_d <= ~InProgress_q2 & InProgress_q3;
+      EndBusy   <= EndBusy_d;
+    end
+end
+
+
+// Update MII RX_DATA register
+always @ (posedge Clk or posedge Reset)
+begin
+  if(Reset)
+    UpdateMIIRX_DATAReg <= 0;
+  else
+  if(EndBusy & ~WCtrlDataStart_q)
+    UpdateMIIRX_DATAReg <= 1;
+  else
+    UpdateMIIRX_DATAReg <= 0;    
+end
+
+
+
+// Generation of the delayed signals used for positive edge triggering.
+always @ (posedge Clk or posedge Reset)
+begin
+  if(Reset)
+    begin
+      WCtrlData_q1 <= 1'b0;
+      WCtrlData_q2 <= 1'b0;
+      WCtrlData_q3 <= 1'b0;
+      
+      RStat_q1 <= 1'b0;
+      RStat_q2 <= 1'b0;
+      RStat_q3 <= 1'b0;
+
+      ScanStat_q1  <= 1'b0;
+      ScanStat_q2  <= 1'b0;
+      SyncStatMdcEn <= 1'b0;
+    end
+  else
+    begin
+      WCtrlData_q1 <= WCtrlData;
+      WCtrlData_q2 <= WCtrlData_q1;
+      WCtrlData_q3 <= WCtrlData_q2;
+
+      RStat_q1 <= RStat;
+      RStat_q2 <= RStat_q1;
+      RStat_q3 <= RStat_q2;
+
+      ScanStat_q1  <= ScanStat;
+      ScanStat_q2  <= ScanStat_q1;
+      if(MdcEn)
+        SyncStatMdcEn  <= ScanStat_q2;
+    end
+end
+
+
+// Generation of the Start Commands (Write Control Data or Read Status)
+always @ (posedge Clk or posedge Reset)
+begin
+  if(Reset)
+    begin
+      WCtrlDataStart <= 1'b0;
+      WCtrlDataStart_q <= 1'b0;
+      RStatStart <= 1'b0;
+    end
+  else
+    begin
+      if(EndBusy)
+        begin
+          WCtrlDataStart <= 1'b0;
+          RStatStart <= 1'b0;
+        end
+      else
+        begin
+          if(WCtrlData_q2 & ~WCtrlData_q3)
+            WCtrlDataStart <= 1'b1;
+          if(RStat_q2 & ~RStat_q3)
+            RStatStart <= 1'b1;
+          WCtrlDataStart_q <= WCtrlDataStart;
+        end
+    end
+end 
+
+
+// Generation of the Nvalid signal (indicates when the status is invalid)
+always @ (posedge Clk or posedge Reset)
+begin
+  if(Reset)
+    Nvalid <= 1'b0;
+  else
+    begin
+      if(~InProgress_q2 & InProgress_q3)
+        begin
+          Nvalid <= 1'b0;
+        end
+      else
+        begin
+          if(ScanStat_q2  & ~SyncStatMdcEn)
+            Nvalid <= 1'b1;
+        end
+    end
+end 
+
+// Signals used for the generation of the Operation signals (positive edge)
+always @ (posedge Clk or posedge Reset)
+begin
+  if(Reset)
+    begin
+      WCtrlDataStart_q1 <= 1'b0;
+      WCtrlDataStart_q2 <= 1'b0;
+
+      RStatStart_q1 <= 1'b0;
+      RStatStart_q2 <= 1'b0;
+
+      InProgress_q1 <= 1'b0;
+      InProgress_q2 <= 1'b0;
+      InProgress_q3 <= 1'b0;
+
+  	  LatchByte0_d <= 1'b0;
+  	  LatchByte1_d <= 1'b0;
+
+  	  LatchByte <= 2'b00;
+    end
+  else
+    begin
+      if(MdcEn)
+        begin
+          WCtrlDataStart_q1 <= WCtrlDataStart;
+          WCtrlDataStart_q2 <= WCtrlDataStart_q1;
+
+          RStatStart_q1 <= RStatStart;
+          RStatStart_q2 <= RStatStart_q1;
+
+          LatchByte[0] <= LatchByte0_d;
+          LatchByte[1] <= LatchByte1_d;
+
+          LatchByte0_d <= LatchByte0_d2;
+          LatchByte1_d <= LatchByte1_d2;
+
+          InProgress_q1 <= InProgress;
+          InProgress_q2 <= InProgress_q1;
+          InProgress_q3 <= InProgress_q2;
+        end
+    end
+end 
+
+
+// Generation of the Operation signals
+assign WriteDataOp  = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;    
+assign ReadStatusOp = RStatStart_q1     & ~RStatStart_q2;
+assign ScanStatusOp = SyncStatMdcEn     & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
+assign StartOp      = WriteDataOp | ReadStatusOp | ScanStatusOp;
+
+// Busy
+reg		Busy;
+always @ (posedge Clk or posedge Reset)
+	if (Reset)
+		Busy	<=0;
+	else if(WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid)
+		Busy	<=1;
+	else
+		Busy	<=0;
+		
+//assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
+
+
+// Generation of the InProgress signal (indicates when an operation is in progress)
+// Generation of the WriteOp signal (indicates when a write is in progress)
+always @ (posedge Clk or posedge Reset)
+begin
+  if(Reset)
+    begin
+      InProgress <= 1'b0;
+      WriteOp <= 1'b0;
+    end
+  else
+    begin
+      if(MdcEn)
+        begin
+          if(StartOp)
+            begin
+              if(~InProgress)
+                WriteOp <= WriteDataOp;
+              InProgress <= 1'b1;
+            end
+          else
+            begin
+              if(EndOp)
+                begin
+                  InProgress <= 1'b0;
+                  WriteOp <= 1'b0;
+                end
+            end
+        end
+    end
+end
+
+
+
+// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
+always @ (posedge Clk or posedge Reset)
+begin
+  if(Reset)
+    BitCounter[6:0] <= 7'h0;
+  else
+    begin
+      if(MdcEn)
+        begin
+          if(InProgress)
+            begin
+              if(NoPre & ( BitCounter == 7'h0 ))
+                BitCounter[6:0] <= 7'h21;
+              else
+                BitCounter[6:0] <= BitCounter[6:0] + 1'b1;
+            end
+          else
+            BitCounter[6:0] <= 7'h0;
+        end
+    end
+end
+
+
+// Operation ends when the Bit Counter reaches 63
+assign EndOp = BitCounter==63;
+
+assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
+assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
+assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
+assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
+
+
+// Latch Byte selects which part of Read Status Data is updated from the shift register
+assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
+assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
+
+wire MdcEn_n;
+
+// Connecting the Clock Generator Module
+eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) 
+                   );
+
+// Connecting the Shift Register Module
+eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), 
+                    .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), 
+                    .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
+                   );
+
+// Connecting the Output Control Module
+eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), 
+                          .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), 
+                          .Mdo(Mdo), .MdoEn(MdoEn)
+                         );
+
+endmodule
diff --git a/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v b/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v
new file mode 100644
index 000000000..99c125823
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v
@@ -0,0 +1,158 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  eth_outputcontrol.v                                         ////
+////                                                              ////
+////  This file is part of the Ethernet IP core project           ////
+////  http://www.opencores.org/projects/ethmac/                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Igor Mohor (igorM@opencores.org)                      ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2001 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: eth_outputcontrol.v,v $
+// Revision 1.2  2005/12/13 12:54:49  maverickist
+// first simulation passed
+//
+// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
+// no message
+//
+// Revision 1.2  2005/04/27 15:58:46  Administrator
+// no message
+//
+// Revision 1.1.1.1  2004/12/15 06:38:54  Administrator
+// no message
+//
+// Revision 1.4  2002/07/09 20:11:59  mohor
+// Comment removed.
+//
+// Revision 1.3  2002/01/23 10:28:16  mohor
+// Link in the header changed.
+//
+// Revision 1.2  2001/10/19 08:43:51  mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1  2001/08/06 14:44:29  mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1  2001/07/30 21:23:42  mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3  2001/06/01 22:28:56  mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
+//
+//
+
+module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
+
+input         Clk;                // Host Clock
+input         Reset;              // General Reset
+input         WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
+input         NoPre;              // No Preamble (no 32-bit preamble)
+input         InProgress;         // Operation in progress
+input         ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal
+input   [6:0] BitCounter;         // Bit Counter
+input         MdcEn_n;            // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
+
+output        Mdo;                // MII Management Data Output
+output        MdoEn;              // MII Management Data Output Enable
+
+wire          SerialEn;
+
+reg           MdoEn_2d;
+reg           MdoEn_d;
+reg           MdoEn;
+
+reg           Mdo_2d;
+reg           Mdo_d;
+reg           Mdo;                // MII Management Data Output
+
+
+
+// Generation of the Serial Enable signal (enables the serialization of the data)
+assign SerialEn =  WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
+                | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
+
+
+// Generation of the MdoEn signal
+always @ (posedge Clk or posedge Reset)
+begin
+  if(Reset)
+    begin
+      MdoEn_2d <= 1'b0;
+      MdoEn_d <= 1'b0;
+      MdoEn <= 1'b0;
+    end
+  else
+    begin
+      if(MdcEn_n)
+        begin
+          MdoEn_2d <= SerialEn | InProgress & BitCounter<32;
+          MdoEn_d <= MdoEn_2d;
+          MdoEn <= MdoEn_d;
+        end
+    end
+end
+
+
+// Generation of the Mdo signal.
+always @ (posedge Clk or posedge Reset)
+begin
+  if(Reset)
+    begin
+      Mdo_2d <= 1'b0;
+      Mdo_d <= 1'b0;
+      Mdo <= 1'b0;
+    end
+  else
+    begin
+      if(MdcEn_n)
+        begin
+          Mdo_2d <= ~SerialEn & BitCounter<32;
+          Mdo_d <= ShiftedBit | Mdo_2d;
+          Mdo <= Mdo_d;
+        end
+    end
+end
+
+
+
+endmodule
diff --git a/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v b/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v
new file mode 100644
index 000000000..9aa350b2b
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v
@@ -0,0 +1,159 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  eth_shiftreg.v                                              ////
+////                                                              ////
+////  This file is part of the Ethernet IP core project           ////
+////  http://www.opencores.org/projects/ethmac/                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Igor Mohor (igorM@opencores.org)                      ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2001 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: eth_shiftreg.v,v $
+// Revision 1.2  2005/12/13 12:54:49  maverickist
+// first simulation passed
+//
+// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
+// no message
+//
+// Revision 1.2  2005/04/27 15:58:47  Administrator
+// no message
+//
+// Revision 1.1.1.1  2004/12/15 06:38:54  Administrator
+// no message
+//
+// Revision 1.5  2002/08/14 18:16:59  mohor
+// LinkFail signal was not latching appropriate bit.
+//
+// Revision 1.4  2002/03/02 21:06:01  mohor
+// LinkFail signal was not latching appropriate bit.
+//
+// Revision 1.3  2002/01/23 10:28:16  mohor
+// Link in the header changed.
+//
+// Revision 1.2  2001/10/19 08:43:51  mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1  2001/08/06 14:44:29  mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1  2001/07/30 21:23:42  mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3  2001/06/01 22:28:56  mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
+//
+//
+
+module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, 
+                    LatchByte, ShiftedBit, Prsd, LinkFail);
+
+
+input       Clk;              // Input clock (Host clock)
+input       Reset;            // Reset signal
+input       MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.
+input       Mdi;              // MII input data
+input [4:0] Fiad;             // PHY address
+input [4:0] Rgad;             // Register address (within the selected PHY)
+input [15:0]CtrlData;         // Control data (data to be written to the PHY)
+input       WriteOp;          // The current operation is a PHY register write operation
+input [3:0] ByteSelect;       // Byte select
+input [1:0] LatchByte;        // Byte select for latching (read operation)
+
+output      ShiftedBit;       // Bit shifted out of the shift register
+output[15:0]Prsd;             // Read Status Data (data read from the PHY)
+output      LinkFail;         // Link Integrity Signal
+
+reg   [7:0] ShiftReg;         // Shift register for shifting the data in and out
+reg   [15:0]Prsd;
+reg         LinkFail;
+
+
+
+
+// ShiftReg[7:0] :: Shift Register Data
+always @ (posedge Clk or posedge Reset) 
+begin
+  if(Reset)
+    begin
+      ShiftReg[7:0] <= 8'h0;
+      Prsd[15:0] <= 16'h0;
+      LinkFail <= 1'b0;
+    end
+  else
+    begin
+      if(MdcEn_n)
+        begin 
+          if(|ByteSelect)
+            begin
+              case (ByteSelect[3:0])
+                4'h1 :    ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
+                4'h2 :    ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
+                4'h4 :    ShiftReg[7:0] <= CtrlData[15:8];
+                4'h8 :    ShiftReg[7:0] <= CtrlData[7:0];
+                default : ShiftReg[7:0] <= 8'h0;
+              endcase
+            end 
+          else
+            begin
+              ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
+              if(LatchByte[0])
+                begin
+                  Prsd[7:0] <= {ShiftReg[6:0], Mdi};
+                  if(Rgad == 5'h01)
+                    LinkFail <= ~ShiftReg[1];  // this is bit [2], because it is not shifted yet
+                end
+              else
+                begin
+                  if(LatchByte[1])
+                    Prsd[15:8] <= {ShiftReg[6:0], Mdi};
+                end
+            end
+        end
+    end
+end
+
+
+assign ShiftedBit = ShiftReg[7];
+
+
+endmodule